Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CCMN (register, 64-bit)

Test 1: uops

Code:

  ccmn x0, x1, #0, hi
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)9fl1d cache writeback (a8)a9cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)f5f6f7f8fd
10041035706191725100010001000622501103510358053882100010003000103510411100110001000007322722990100010361036103610361036
10041035706191725100010001000622501103510358053882100010003000103510411100110001000007322722990100010361036103610361036
10041035806191725100010001000622500103510358053882100010003000103510411100110001000007322722990100010361036103610361036
10041035806191725100010001000622500103510358053882100010003000103510411100110001000007322722990100010361036103610361036
10041081806191725100010001000622500103510358053882100010003000103510411100110001000007322722990100010361036103610361036
10041035706191725100010001000622501103510358053882100010003000103510411100110001000007322722990100010361036103610361036
10041035706191725100010001000622501103510358053882100010003000103510411100110001000007322722990100010361036103610361036
10041035806191725100010001000622501103510358053882100010003000103510411100110001000007322722990100010361036103610361036
10041035706191725100010001000622501103510358053882100010003000103510411100110001000007322722990100010361036103610361036
10041035806191725100010001000622501103510358053882100010003000103510411100110001000007322722990100010361036103610361036

Test 2: Latency 3->1

Chain cycles: 1

Code:

  ccmn x0, x1, #0, hi
  cset x0, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03091e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2020420035150006119926252010020100201001297150049169552003520035174063174812010020200402002003510411202011009910020100201000013101228221999220000101002003620036200362003620036
2020420035150006119926252010020100201001297150049169552003520035174063174812010020200402002003510411202011009910020100201000313101228321999220000101002003620036200362003620036
2020420035150006119926252010020100201001297150049169552003520066174063174812010020200402002003510411202011009910020100201003013101228221999220000101002003620036200362003620036
2020420035150006119926252010020100201001297150049169552003520035174063174812010020200402002003510411202011009910020100201000013101228221999220000101002003620036200362003620036
20204200351500012619926252010020100201001297150049169552003520035174063174812010020200402002003510411202011009910020100201000013101228221999220000101002003620036200362003620036
20204200351500012419926252010020100201001297150049169552003520035174063174812010020200402002003510411202011009910020100201000013101228221999220000101002003620036200362003620036
2020420035150006119926252010020100201001297150049169552003520035174063174812010020200402002003510411202011009910020100201000013101228221999220000101002003620036200362003620036
20204200351500010319926252010020100201001297150049169552003520035174063174812010020200402002003510411202011009910020100201000013101328221999220000101002003620036200362003620036
2020420035150006119926252010020100201001297150049169552003520035174063174812010020200402002003510411202011009910020100201000013101228221999220000101002003620036200362003620036
2020420035150006119926252010020100201001297150049169552003520035174063174812010020200402002003510411202011009910020100201000013101228221999220000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03093f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2002420035150061199182520010200102001012972474916955200352003517428317504200102002040020200351041120021109102001020010031270127121999520000100102003620036200362003620036
2002420035150061199182520010200102001012972474916955200352003517428317504200102002040020200351041120021109102001020010001270127121999520000100102008120036200802003620036
200242003515007261991825200102001020010129724749169552003520035174283175042001020020400202003510411200211091020010200101361270327121999520000100102003620036200362003620036
2002420035150061199182520010200102001012972474916955200352003517428317504200102002040020200351041120021109102001020010031270227311999520000100102003620036200362003620036
2002420035150061199182520010200102001012972474916955200352003517428317527200102002040020200351041120021109102001020010001270127121999520000100102003620036200362003620036
2002420035149061199182520010200102001012972474916955200352003517428317504200102002040020200351041120021109102001020010001270127111999520000100102003620036200362003620036
2002420035150082199182520010200102001012972474916955200352003517428317504200102002040020200351041120021109102001020010001270227211999520000100102003620036200362003620036
2002420035149061199182520010200102001012972474916955200352003517428317504200102002040020200351041120021109102001020010031270227211999520000100102003620036200362003620036
2002420035150061199182520010200102001012972474916955200352003517428317504200102002040020200351041120021109102001020010001270227111999520000100102003620036200362003620036
2002420035150061199182520010200102001012972474916955200352003517428317504200102002040020200351041120021109102001020010031270227321999520000100102003620036200362003620036

Test 3: Latency 3->2

Chain cycles: 1

Code:

  ccmn x0, x1, #0, hi
  cset x1, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20204200351500000006119930252010020100201121297233491695520035200351742561748720112202244024820035104112020110099100201002010000000011113180116112001120000101002003620036200362003620036
20204200351500000006119930252010020100201121297233491695520035200351742561748720112202244024820035104112020110099100201002010000000011113180116112001120000101002003620036200362003620036
202042003515000001206119926252010020100201001297150491695520035200351740631748120100202004020020035104112020110099100201002010000000000013101328331999220000101002003620036200362003620036
20204200351500000006119926252010020100201001297150491695520035200351740631748120100202004020020035104112020110099100201002010000000000013101328431999220000101002003620036200362003620036
202042003515000000018719926252010020100201001297150491695520035200351740631748120100202004020020035104112020110099100201002010000003000013101328331999220000101002003620036200362003620036
20204200351500000006119926252010020100201001297150491695520035200351740631748120100202004020020035104112020110099100201002010000000000013101328331999220000101002003620036200362003620036
20204200351500000008219926252010020100201001297150491695520035200351740631748120100202004020020035104112020110099100201002010000000000013101328331999220000101002003620036200362003620036
202042003515000000061199262520100201002010012971504916955200352003517406111743720100202004020020035104112020110099100201002010000000000013101328331999220000101002003620036200362003620036
202042003515000000016819926252010020100201001297150491695520035200351740631748120100202004020020035104112020110099100201002010000000000013101328331999220000101002003620036200362003620036
202042003515000000014519926252010020100201001297150491695520035200351740631748120100202004020020035104112020110099100201002010000000000013101328331999220000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
200242003515000611991825200102001020010129724714916955200352003517428317504200102002040020200351041120021109102001020010001270527111999520000100102003620036200362003620036
2002420035150006119918252001020010200101297247149169552003520035174283175042001020020400202003510411200211091020010200100931270127211999520000100102003620036200362003620036
20024200351500061199182520010200102001012972471491695520035200351742831750420010200204002020035104112002110910200102001001321270127211999520000100102003620036200362003620036
200242003514900611991825200102001020010129724714916955200352003517428317504200102002040020200351041120021109102001020010101270127111999520000100102003620036200362003620036
200242003515000611991825200102001020010129724714916955200352003517428317504200102002040020200351041120021109102001020010031270127111999520000100102003620036200362003620036
200242003515000611991825200102001020010129724714916955200352003517428317504200102002040020200351041120021109102001020010001270127111999520000100102003620036200362003620036
200242003515000611991825200102001020010129724714916955200352003517428317504200102002040020200351041120021109102001020010001270127111999520000100102003620036200362003620036
20024200351500061199182520010200102001012991281491695520035200351742831750420010200204002020035104112002110910200102001001351270127111999520000100102003620036200362003620036
20024200351500010481991825200102001020102129724714916955200352003517428317504200102002040020200351041120021109102001020010031270127111999520000100102003620036200362003620036
20024200351500061199182520010200102001012972471491695520035200351742831750420010200204002020035104112002110910200102001026901270127111999520000100102003620036200362003620036

Test 4: Latency 3->3

Code:

  ccmn x0, x1, #0, hi
  mov x0, 1
  mov x1, 2

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102041003575016899202510200102001020064765204969551003510035865638732102001020030200100351101110201100991010010000000710227249990101001001003610036100361003610036
10204100357506199202510200102001020064765204969551003510035865638732102001020030200100351101110201100991010010000000710227229990101001001003610036100361003610036
10204100357506199202510200102001020064765214969551003510035865638732102001020030200100351101110201100991010010000000710227229990101001001003610036100361003610036
10204100357506199202510200102001020064765204969551003510035865638732102001020030200100351101110201100991010010000000710227229990101001001003610036100361003610036
10204100357506199202510200102001020064765204969551003510035865638732102001020030200100351101110201100991010010000000710227229990101001001003610036100361003610036
10204100357506199202510200102001020064765204969551003510035865638732102001020030200100351101110201100991010010000000710227229990101001001003610036100361003610036
10204100357506199202510200102001020064765214969551003510035865638732102001020030200100351101110201100991010010000000710227229990101001001003610036100361003610036
10204100357506199202510200102001020064765204969551003510035865638732102001020030200100351101110201100991010010000000710227229990101001001003610036100361003610036
10204100357506199202510200102001020064765204969551003510035865638732102001020030200100351101110201100991010010000000710227229990101001001003610036100361003610036
10204100357506199202510200102001020064765204969551003510035865638732102001020030200100351101110201100991010010000000710227229990101001001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03191e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst int alu (97)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100241003575008299182510020100201002064729614969551003510035867838754100201002030020100351041110021109100101000000064022722999310010101003610036100361003610036
100241003575006199182510020100201002064729614969551003510035867838754100201002030020100351041110021109100101000000064022722999310010101003610036100361003610036
100241003575008499182510020100201002064729604969551003510035867838754100201002030020100351041110021109100101000002064022722999310010101003610036100361003610036
100241003575006199182510020100201002064729614969551003510035867838754100201002030020100351041110021109100101000000064022722999310010101003610036100361003610036
100241003576006199182510020100201002064729614969551003510035867838754100201002030020100351041110021109100101000000064022722999310010101003610036100361003610036
100241003575006199182510020100201002064729614969551003510035867838754100201002030020100351041110021109100101000000064022722999310010101003610036100361003610036
100241003575006199182510020100201002064729614969551003510035867838754100201002030020100351041110021109100101000000064022722999310010101003610036100361003610036
100241003575006199182510020100201002064729614969551003510035867838754100201002030020100351041110021109100101000000064022722999310010101003610036100361003610036
100241003575006199182510020100201002064729614969551003510035867838754100201002030020100351041110021109100101000000064022722999310010101003610036100361003610036
100241003576008299182510020100201002064729614969551003510035867838754100201002030020100351041110021109100101000000064022722999310010101003610036100361003610036

Test 5: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  ccmn x0, x1, #0, hi
  ands xzr, xzr, xzr
  ccmn x0, x1, #0, hi
  ands xzr, xzr, xzr
  ccmn x0, x1, #0, hi
  ands xzr, xzr, xzr
  ccmn x0, x1, #0, hi
  ands xzr, xzr, xzr
  ccmn x0, x1, #0, hi
  ands xzr, xzr, xzr
  ccmn x0, x1, #0, hi
  ands xzr, xzr, xzr
  ccmn x0, x1, #0, hi
  ands xzr, xzr, xzr
  ccmn x0, x1, #0, hi
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

retire uop (01)cycle (02)03181e1f3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
160204534404000600372516010016010016010010635880495032453404534043333933335916010016020024020053404661116020110099100160100801000000001011011911534001600001005340553405534055340553405
160204534044000240372516010016010016010010635880495032453404534043333933335916010016020024020053404661116020110099100160100801000000011011011911534001600001005340553405534055340553405
160204534043990210372516010016010016010010635880495032453404534043333933335916010016020024020053404661116020110099100160100801000000001011011911534001600001005340553405534055340553405
16020453404399100372516010016010016010010635880495032453458534043333933335916010016020024020053404661116020110099100160100801000000001011011911534001600001005340553405534055340553405
160204534044000630372516010016010016010010635880495032453404534043333933335916010016020024020053404661116020110099100160100801000000001011011911534001600001005340553405534055340553405
160204534044000600372516010016010016010010635880495032453404534043333933335916010016020024020053404661116020110099100160100801000000001011011911534001600001005340553448534055340553405
160204534044000540372516010016010016010010635880495032453404534043333933335916010016020024020053404661116020110099100160100801000000001011011911534001600001005340553405534055340553405
160204534044000360372516010016010016010010635880495032453404534043333933335916010016020024020053404661116020110099100160100801000000001011011911534001600001005340553405534055340553405
160204534044000150372516010016010016010010635880495032453404534043333933335916010016020024020053404661116020110099100160100801000000001011011911534001600001005340553405534055340553405
160204534044000630372516010016010016010010635880495032453404534043333933335916010016020024020053404661116020110099100160100801000000001011011911534001600001005340553405534055340553405

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6672

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)5f6061696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaeb? int retires (ef)f5f6f7f8fd
160024533904000000000000432516001016001016001010293881110495029453374533743333133335116001016002024002053374661116002110910160010800100000000010022132110192111010533701600002011105337553375533755337553375
160024533744000000000000432516001016001016001010293881110495029453374533743333133335116001016002024002053374661116002110910160010800100000000010022135111192111011533701600002011105337553375533755337553375
160024533744000000000000582516001016001016001010293881110495029453374533743333133335116001016002024002053374661116002110910160010800100000000010022135111192311113533701600002011105337553375533755337553375
160024533743990000000000432516001016001016001010293881110495029453374533743333133337316001016002024002053374661116002110910160010800100000000010024166211193121110533701600002022105337553375533755337553375
1600245337440000000000001942516001016001016001010293881110495029453374533743333133335116001016002024002053374661116002110910160010800100000000010022135110192111211533701600002011105337553375533755337553375
160024533744000000000000432516001016001016001010293881110495029453374533743333133335116001016002024002053374661116002110910160010800100000000010022135113192111211533701600002011105337553375533755337553375
160024533744000000000000432516001016001016001010293881110495029453374533743333133335116001016002024002053374661116002110910160010800100000000010022135112192111312533701600002011105337553375533755337553375
1600245337440000000000002332516001016001016001010293881110495029453374533743333133335116001016002024002053374661116002110910160010800100000000010024135110192211113533701600002011105337553375533755337553375
16002453374400000000000043251600101600101600101029388111049502945337453374333313333511600101600202400205337466111600211091016001080010000000001002213511119211910533701600002011105337553375533755337553375
160024533744000000000001108251600101600101600101029388111049502945337453374333313333511600861600202400205337466111600211091016001080010000000001002213511319211129533701600002011105337553375533755337553375

Test 6: throughput

Count: 4

Code:

  fcmp s0, s0
  ccmn x0, x1, #0, hi
  ccmn x0, x1, #0, hi
  ccmn x0, x1, #0, hi
  ccmn x0, x1, #0, hi
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3353

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
502041348310000872550100401001000040100100005747578000011338513414134146128245637119501004020010000120200200001341413414115020110099100401001000040100000032102191113411400001001341513415134151341513415
5020413414101005202550100401001000040100100005747578000011338513414134146128245637119501004020010000120200200001341413414115020110099100401001000040100002032101191113411400001001341513415134151341513415
502041341410000452550100401001000040100100005747578000011338513414134146128246737119501004020010000120200200001341413414115020110099100401001000040100000032101191113411400001001341513415134151341513415
502041341410000452550100401001000040100100005747578000011338513414134146130245637119501004020010000120200200001341413414115020110099100401001000040100000032101191113411400001001341513415134151341513415
5020413414101003412550100401001000040100100005747578000011338513414134146130246737119501004020010000120200200001341413414115020110099100401001000040100130032101191113411400001001341513415134151341513415
5020413414101001082550100401001000040100100005747578000011338513414134146130246737119501004020010000120200200001341413414115020110099100401001000040100030032101191113411400001001341513415134151341513415
502041341410400452550100401001000040100100005747578000011338513414134146128246737119501004020010000120200200001341413414115020110099100401001000040100000032101191113411400001001341513415134151341513415
502041341410100452550100401001000040100100005747578000011338513414134146128245637119501004020010000120200200001341413414115020110099100401001000040100030032101191113411400001001341513415134151341513415
502041341410000872550100401001000040100100005747578000011338513414134146130245637119501004020010000120200200001341413414115020110099100401001000040100060032101191113411400001001341513415134151341513415
502041341410000452550100401001000040100100005747578000011338513414134146128245637119501004020010000120200200001341413414115020110099100401001000040100030032101191113411400001001341513415134151341513415

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3346

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
500241338310000452550010400101000040010100005734568000001335313382133825575379537109500104002010000120020200001338213382115002110910400101000040010003140519221337940000101338313383133831338313383
5002413382100027872550010400101000040010100005734568000001335313382133825577378437109500104002010000120020200001338213382115002110910400101000040010003140219221337940000101338313383133831338313383
5002413382100001102550010400101000040010100005734568000011335313382133825577379537109500104002010000120020200001338213382115002110910400101000040010003140219221337940000101338313383133831338313383
500241338210000872550010400101000040010100005734568000011335313382133825577379537109500104002010000120020200001338213382115002110910400101000040010003140219221337940000101338313383133831338313383
5002413382100003362550010400101000040010100005734568000001335313382133825577379537109500104002010000120020200001338213382115002110910400101000040010003140219221337940000101338313383133831338313383
500241338210000452550010400101000040010100005734568000001335313382133825577378437109500104002010000120020200001338213382115002110910400101000040010003140219221337940000101338313383133831338313383
500241338210000452550010400101000040010100005734568000011335313382133825575378437109500104002010000120020200001338213382115002110910400101000040010003140219221337940000101338313383133831338313383
5002413382100004732550010400101000040010100005734568000011335313382133825575378437109500104002010000120020200001338213382115002110910400101000040010003140219221337940000101338313383133831338313383
5002413382100003362550010400101000040010100005734568000001335313382133825575378437109500104002010000120020200001338213382115002110910400101000040010003140219221337940000101338313383133831338313383
500241338210100452550010400101000040010100005734568000001335313382133825575379537109500104002010000120020200001338213382115002110910400101000040010033140219221337940000101338313383133831338313383