Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

DMB (ISH)

Test 1: uops

Code:

  dmb ish

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)60696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)8283flush restart other nonspec (84)85inst all (8c)inst barrier (9c)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)f5f6f7f8fd
1004302723003012200110001000100060001343026303532884100010003027303511100110000100000073116113024100030283036302830363028
1004302722003020200010001000100060001333027303532893100010003035302711100110000100000073116113032100030283036302730363027
1004302622003011200110001000100060001343025303532893100010003035302711100110000100000073116113023100030273036302830363028
1004302723003012200910001000100060001423035302632885100010003026303511100110000100000073116113032100030283036302730363028
1004302723003020200110001000100060001423035302632884100010003026303511100110000100000073116113024100030283036302730363028
1004302723003011200010081000100060001343035302732884100010003027303511100110000100000073116113022100030363027303630263036
1004303523003010200110001000100060001333027303532893100010003035302711100110000100040073116113032100030273036302630363028
1004302722003020200910001000100060001423035302732884100010003027303511100110000100000073116113032100030363027303630273036
10043035230030202009100010001000600014230273035328931000100030353027111001100001000130073116113032100030283036302830363027
1004302623003012200110001000100060001333027303532893100010003035302611100110000100000073116113032100030363026303630273036

Test 2: throughput

Code:

  dmb ish

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.9135

retire uop (01)cycle (02)03091e3f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)696a6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst barrier (9c)9fl1d tlb access (a0)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? int retires (ef)f5f6f7f8fd
102042909321800291201900810100100100001001000050059800492605529035291353277431010020010000200290352329511102011009910010010000100001000000071021622291320100001002904429136290362913629044
102042904321800290281890810100100100001001000050059800492605529034291353278431010020010000200291352322211102011009910010010000100001000000071021622290390100001002902929136290352913629028
102042902721800291201900810100100100001001000050059800492596329135290343277351010020010000200290282329511102011009910010010000100001000000071021622291320100001002913629026291362903629136
102042913521800291201900810100100100001211000050059800492596329135290433277431010020010000200290352329511102011009910010010000100001000000071021622291320100001002902629136290362913629029
1020429028219002901918908101001001000010010000500598004925963291352904332774310100200100002002903523295111020110099100100100001000010000012071021622290250100001002913629044291362903529136
102042913521800291201900810100100100001001000050059800492596329027291353278431010020010000200291352322111102011009910010010000100001000000071021622291320100001002913629029291362903529136
102042913521800290281900810100100100001001000050059800492596429135290433277431010020010000200290342329511102011009910010010000100001000000071021622291320100001002913629044291362903529136
102042913521700291201900810125100100001001000050059800492594729135290363277511010020010000200290442329511102011009910010010000100001000000071021622291320100001002904429136290442913629043
102042904221800290291889910100100100001001000050059800492594529135290353277501010020010000200290432329511102011009910010010000100001000000071021622290320100001002904429136290362913629044
102042904321800290191891710100100100001001000050059800492605529043291353277501010020010000200290432329511102011009910010010000100001000000071021622290320100001002913629036291362904529136

1000 unrolls and 10 iterations

Result (median cycles for code): 2.9867

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696a6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst barrier (9c)9fst unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)? int retires (ef)f5f6f7f8fd
100242995122402993619915100101010000101000050599821492687129867299513285961001020100002029867299511110021109101010000101000000640316332986410000102986629952298672995229865
100242986422402985219831100101010000101000050599821492687129866299513286811001020100002029951298661110021109101010000101000000640216332986410000102986729952298682995229868
100242986722502993619829100101010000101000050599821492687129867299513286811001020100002029951298651110021109101010000101000000640316222986210000102995229866299522986529952
100242995122302993619915100101010000101000050599821492687129866299513286811001020100002029951298671110021109101010000101000000640216322986410000102995229868299522986729952
100242995122402993619915100101010000101000050599821492678629951298653285971001020100002029864299511110021109101010000101000000640316232986310000102995229866299522986629952
100242995122402985119830100101010000101000050599821492687129865299513286811001020100002029951298661110021109101010000101000000640316222994810000102986729952298672995229868
100242986722402993619915100101010000101000050599821492678429951298663285961001020100002029867299511110021109101010000101000000640216222986310000102995229867299522986829952
100242995122302993619915100101010000101000050599821492687129866299513286811001020100002029951298671110021109101010000101000000640316232986110000102986729952298662995229868
100242986722502993619915100101010000101000050599821492678529951298653285971001020100002029951298651110021109101010000101000000640316222994810000102995229867299522986829952
100242995122402985019830100101010000101000050599821492687129866299513286811001020100002029951298661110021109101010000101000000640216332986310000102986829952298672995229868