Firestorm: LDRB measurements

Code:

  ldrb w0, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	394	3	1	1	44	1	0	1	383	2	1	1	24	25	1000	1000	1000	15267	1	398	398	221	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	1	1000	43	1038	0	38	1038	6	1	39	44	73	1	16	1	1	395	14	10	7	1000	399	395	399	399	399
1004	398	3	1	0	44	0	0	1	381	2	1	1	19	25	1000	1000	1000	15208	0	398	398	221	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	6	1	39	44	73	1	16	1	1	391	14	10	7	1000	399	399	399	399	399
1004	398	3	0	0	44	0	0	1	383	2	12	1	19	25	1000	1000	1000	15267	0	398	394	221	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	6	1	39	44	73	1	16	1	1	395	14	14	7	1000	399	399	399	399	399
1004	398	3	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15267	0	398	398	224	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	1	1000	43	1038	0	38	1038	6	1	39	44	73	1	16	1	1	395	14	14	7	1000	399	399	399	399	399
1004	398	3	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15274	0	398	398	221	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	1	1000	43	1038	0	38	1038	6	1	38	44	73	1	16	1	1	395	14	14	7	1000	399	399	399	399	399
1004	398	3	0	0	44	0	0	1	383	2	12	1	16	25	1000	1000	1000	15274	0	398	398	217	3	252	1000	1000	1000	398	77	1	1	1001	1000	1000	1	1000	43	1038	0	38	1038	6	1	39	44	73	1	16	1	1	395	14	10	7	1000	399	399	399	399	399
1004	398	3	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15208	0	398	398	221	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	44	1038	0	38	1038	6	1	38	43	73	1	16	1	1	395	14	14	7	1000	399	399	399	399	399
1004	394	3	0	0	44	1	0	1	383	2	12	1	21	25	1000	1000	1000	15208	0	398	398	221	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	44	1038	0	38	1038	6	1	38	44	73	1	16	1	1	395	14	14	7	1000	399	399	399	399	399
1004	398	3	0	0	44	0	0	1	383	3	12	1	16	25	1000	1000	1000	15267	0	398	398	217	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	38	44	73	1	16	1	1	395	14	14	7	1000	399	399	399	399	399
1004	398	3	0	0	44	0	0	1	383	2	1	1	20	25	1000	1000	1000	15267	0	403	398	221	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	1	1000	44	1038	0	38	1039	6	1	39	43	73	1	16	1	1	395	14	14	7	1000	399	399	399	395	399

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrb w0, [x6]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0053

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70053	524	1	1	1	0	0	0	0	2	0	1	0	1	70038	69784	59701	25	40108	30103	10002	30100	10000	616149	3352528	1	49	66973	70041	70041	64637	3	64956	40100	30200	10000	60200	10000	70065	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	3	0	10002	0	1	4	10000	1	1	0	1	0	2610	2	71	1	1	70121	30006	6	6	0	10000	30100	70054	70054	70054	70054	70054
40204	70053	524	1	0	1	0	0	0	0	2	0	1	0	0	70038	69702	59701	25	40104	30106	10002	30100	10000	616032	3342350	1	49	66973	70053	70053	64649	3	64956	40100	30200	10000	60200	10221	70053	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10003	0	1	1	10000	1	1	1	1	2	2610	1	71	1	1	69816	30006	6	6	0	10000	30100	70042	70055	70042	70056	70054
40204	70053	524	1	1	1	0	0	2	1	307	0	1	0	1	70038	69702	59701	25	40108	30103	10001	30100	10000	616078	3342350	1	49	66973	70053	70041	64649	3	64956	40100	30200	10000	60200	10000	70053	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	1	10018	0	0	1	10000	1	1	1	1	1	2610	1	71	1	1	69816	30006	6	6	6	10000	30100	70054	70054	70079	70048	70054
40204	70053	525	1	1	0	0	0	0	0	4	0	1	0	1	70038	69702	59712	25	40108	30106	10002	30100	10000	616032	3342350	1	49	66973	70053	70053	64649	3	64944	40100	30200	10000	60200	10000	70053	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	1	10001	0	1	1	10000	1	1	1	1	3	2610	1	71	1	1	69816	30006	6	6	6	10000	30100	70054	70054	70054	70042	70054
40204	70053	524	1	0	0	0	0	0	0	7	0	1	0	1	70038	69702	59701	25	40108	30106	10002	30100	10000	616032	3341769	1	49	66973	70041	70053	64637	3	64956	40100	30200	10000	60200	10000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	0	10001	0	2	1	10000	0	1	1	1	0	2610	1	71	1	1	69816	30006	6	6	6	10000	30100	70049	70054	70054	70054	70054
40204	70041	525	1	0	0	0	0	0	0	2	0	1	0	1	70131	69702	59712	25	40108	30106	10002	30100	10000	616032	3341769	1	49	66973	70041	70053	64649	3	64956	40100	30200	10000	60200	10000	70053	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	0	10002	0	2	1	10000	1	1	1	1	2	2610	1	71	1	1	69804	30006	6	6	6	10000	30100	70422	70054	70042	70054	70042
40204	70053	524	1	1	0	1	1	0	0	2	0	0	0	0	70038	69784	59712	25	40104	30106	10001	30100	10000	616032	3341769	1	49	66961	70053	70053	64649	3	64952	40100	30200	10000	60200	10000	70053	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10002	0	1	1	10000	1	1	1	1	1	2610	1	71	1	1	69816	30006	6	6	6	10000	30100	70054	70054	70054	70054	70054
40204	70053	524	1	1	1	0	1	0	0	2	0	0	0	1	70038	69702	59701	25	40122	30113	10002	30100	10000	616078	3342350	1	49	66973	70053	70053	64649	3	64959	40100	30200	10000	60200	10000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	4	1	10002	0	3	1	10000	1	1	1	1	1	2610	1	71	1	1	69816	30006	6	6	6	10000	30100	70054	70054	70054	70054	70042
40204	70053	524	1	1	1	0	0	0	0	1	0	1	0	0	70038	69784	59713	124	40108	30106	10002	30100	10000	616032	3341769	1	49	66973	70053	70053	64649	3	64956	40100	30200	10000	60200	10000	70053	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10001	5	3	1	10000	1	1	0	1	1	2610	1	71	1	1	69816	30006	6	6	6	10000	30100	70042	70042	70054	70054	70054
40204	70053	525	1	2	1	1	0	0	0	7	0	1	0	0	70038	69785	59788	25	40108	30106	10002	30100	10000	616032	3342350	1	49	67251	70041	70053	64643	3	64956	40100	30200	10000	60200	10000	70053	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	0	10002	0	0	1	10000	1	1	1	1	1	2610	1	71	1	1	69816	30006	6	6	0	10000	30100	70042	70054	70042	70054	70054

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70057	524	1	1	1	0	0	0	0	2	0	0	0	70020	69743	59710	25	40014	30013	10001	30010	10000	616991	3342254	1	49	66971	70051	70051	64669	0	3	64965	40010	30020	10000	60020	10000	70051	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	10000	1	1	2520	1	71	1	1	69814	30003	0	10	10	10000	30010	70052	70052	70036	70057	70052
40024	70051	524	0	0	0	0	0	0	0	6	0	0	0	70036	69775	59710	25	40014	30013	10001	30010	10000	616991	3342254	1	49	66971	70035	70051	64672	0	3	64976	40010	30020	10000	60020	10000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10003	0	3	10000	1	1	2520	1	71	1	1	69814	30003	0	10	10	10000	30010	70052	70052	70036	70052	70052
40024	70051	525	0	0	0	0	0	0	0	1	0	1	0	70020	69775	59695	25	40014	30013	10001	30010	10000	616991	3342254	1	49	66955	70051	70051	64653	0	3	64976	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	2520	1	71	1	1	69814	30003	0	10	10	10000	30010	70036	70052	70052	70052	70052
40024	70035	526	0	0	0	0	0	0	0	1	0	1	0	70020	69775	59713	44	40014	30013	10000	30010	10000	616991	3342254	1	49	66971	70051	70051	64653	0	3	64960	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	10000	0	0	10000	1	0	2520	1	71	1	1	69814	30003	0	0	13	10000	30010	70036	70052	70036	70052	70036
40024	70051	524	0	0	0	0	0	0	0	1	0	1	0	70020	69775	59710	25	40014	30013	10001	30010	10000	616991	3342254	1	49	66971	70051	70051	64669	0	3	64976	40010	30020	10000	60020	10000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	10000	0	1	2555	1	71	1	1	69814	30003	10	10	10	10000	30010	70052	70036	70052	70036	70052
40024	70051	524	0	0	0	0	0	0	0	1	0	0	0	70036	69775	59710	25	40010	30010	10001	30010	10000	617068	3341470	1	49	66971	70051	70035	64669	0	3	64976	40010	30020	10000	60020	10000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	1	0	10000	1	1	2520	1	71	1	1	69814	30000	13	10	10	10000	30010	70052	70036	70052	70052	70055
40024	70051	525	0	0	0	0	0	0	0	1	0	1	0	70036	69743	59710	25	40014	30010	10001	30010	10000	616991	3342254	1	49	66971	70051	70051	64653	0	3	64976	40010	30020	10000	60020	10000	70073	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	3	12	10003	1	1	2520	1	71	1	1	69814	30003	10	10	10	10000	30010	70055	70052	70052	70036	70036
40024	70051	525	0	0	0	0	0	0	0	1	0	0	0	70020	69743	59710	25	40014	30013	10001	30010	10000	616991	3341470	1	49	66971	70051	70051	64669	0	3	64976	40010	30020	10000	60020	10000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	2520	1	71	1	1	69817	30000	10	10	13	10000	30010	70052	70052	70052	70052	70036
40024	70051	524	0	0	0	0	0	0	0	1	0	1	0	70036	69775	59710	25	40014	30013	10001	30010	10000	617068	3342254	1	49	66971	70035	70035	64669	7	3	64960	40010	30020	10000	60020	10000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	2520	1	71	1	1	69817	30000	0	10	0	10000	30010	70052	70036	70055	70052	70052
40024	70051	525	0	0	0	0	0	0	0	1	0	1	0	70036	69778	59710	25	40014	30013	10001	30010	10000	616991	3342254	1	49	66971	70051	70051	64669	0	3	64960	40010	30020	10000	60020	10000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	1	0	10000	1	0	2520	1	71	1	1	69814	30003	0	10	0	10000	30010	70052	70052	70036	70052	70052

Test 3: throughput

Count: 8

Code:

  ldrb w0, [x6]
  ldrb w0, [x6]
  ldrb w0, [x6]
  ldrb w0, [x6]
  ldrb w0, [x6]
  ldrb w0, [x6]
  ldrb w0, [x6]
  ldrb w0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26728	201	0	0	0	1	1	0	1	0	1	26712	2	12	12	0	25	80100	100	80000	100	80000	500	1165789	1	49	23647	26727	26727	16650	3	16788	80100	200	80000	200	80000	26730	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	0	0	39	80039	6	1	39	43	0	0	5110	1	16	1	1	26724	10	10	4	80000	100	26708	26728	26728	26728	26728
80204	26727	200	0	0	0	0	1	45	1	0	0	26692	2	12	12	16	25	80100	100	80000	100	80000	500	1167231	0	49	23647	26707	26727	16650	3	16715	80100	200	80000	200	80000	26735	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	0	0	39	80039	0	1	39	43	0	0	5110	1	16	1	1	26724	10	10	4	80000	100	26728	26728	26708	26728	26728
80204	26727	200	0	0	0	0	0	45	1	0	1	26712	2	12	12	16	25	80100	100	80000	100	80000	500	1166525	0	49	23647	26727	26707	16650	3	16824	80100	200	80000	200	80000	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80000	0	0	0	39	80039	6	1	39	43	0	0	5110	1	16	1	1	26704	0	10	0	80000	100	26728	26708	26728	26708	26708
80204	26707	200	0	0	0	0	0	45	1	0	0	26712	2	12	12	16	25	80100	100	80000	100	80000	500	1165789	0	49	23647	26727	26727	16650	3	16797	80100	200	80000	200	80000	26710	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	1	0	42	80000	6	1	39	43	0	0	5176	1	16	1	1	26724	10	0	4	80000	100	26728	26728	26728	26728	26728
80204	26727	200	0	0	0	0	1	45	1	0	1	26712	2	12	12	16	25	80100	100	80000	100	80000	500	1165789	0	49	23627	26727	26727	16630	3	16748	80100	200	80000	200	80000	26707	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	0	0	39	80039	6	1	39	43	0	0	5110	1	16	1	1	26724	10	10	0	80000	100	26728	26737	26728	26728	26708
80204	26727	200	0	0	0	0	0	45	1	0	1	26712	2	12	12	16	25	80100	100	80000	100	80000	500	1167231	0	49	23647	26727	26727	16650	3	16774	80100	200	80000	200	80000	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80039	0	0	0	3	80039	0	1	39	43	0	0	5110	1	40	1	1	26724	10	10	0	80000	100	26728	26732	26728	26728	26728
80204	26727	201	0	0	0	0	0	45	1	0	0	26696	2	12	12	16	25	80100	100	80000	100	80178	500	1167677	1	49	23809	26727	26729	16650	3	16813	80100	200	80000	200	80000	26727	77	1	1	80201	100	99	100	80000	100	80000	1	100	80000	0	43	80000	0	0	0	39	80039	6	1	0	43	0	0	5110	1	16	1	1	26726	10	10	0	80000	100	26728	26728	26708	26728	26728
80204	26727	200	0	0	0	0	0	45	1	0	1	26712	2	12	12	16	25	80100	100	80000	100	80000	500	1167231	0	49	23647	26727	26727	16650	3	16738	80100	200	80000	200	80000	26727	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	0	0	42	80039	6	1	39	43	0	0	5110	1	16	1	1	26726	10	0	4	80000	100	26708	26728	26728	26728	26728
80204	26727	200	0	0	0	0	0	45	1	0	1	26716	2	12	12	0	25	80100	100	80000	100	80000	500	1167435	0	49	23627	26727	26727	16650	3	16753	80100	200	80000	200	80000	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80299	0	0	0	39	80039	6	1	39	43	0	0	5110	3	16	1	1	26728	0	0	4	80000	100	26728	26732	26737	26729	26728
80204	26727	200	0	0	0	0	0	45	0	1	1	26712	0	12	12	16	25	80100	100	80000	100	80000	500	1167231	0	49	23647	26727	26727	16650	3	16685	80100	200	80000	200	80000	26736	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	1	0	39	80039	0	1	39	43	0	0	5110	1	16	1	1	26724	10	0	4	80000	100	26728	26708	26728	26728	26728

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d2	d5	map dispatch bubble (d6)	d9	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26736	200	1	0	1	1	1	0	66	1	0	0	3	26722	0	7	7	19	25	80010	10	80000	10	80000	50	1167791	0	1	49	23656	0	26737	26715	16660	3	16703	80010	20	80000	20	80000	26736	85	1	1	80021	10	9	10	80000	10	80000	10	80020	20	0	80019	1	0	2	23	80040	6	0	58	43	19	0	0	5020	1	11	17	0	0	10	8	26728	14	10	0	80000	10	26732	26729	26729	26732	26732
80024	26731	200	0	0	0	0	0	0	45	1	0	0	0	26722	2	7	7	19	25	80010	10	80000	10	80000	50	1166960	0	1	49	23656	0	26736	26737	16681	3	16721	80010	20	80000	20	80000	26737	86	1	1	80021	10	9	10	80000	10	80000	10	80019	19	43	80059	1	0	0	61	80039	0	1	19	43	19	0	0	5020	0	7	16	0	0	10	10	26733	13	13	5	80000	10	26716	26737	26738	26738	26737
80024	26736	200	1	0	1	1	0	0	553	0	0	0	2	26721	3	7	7	20	25	80010	10	80000	10	80000	50	1167385	0	1	49	23657	0	26736	26736	16682	3	16724	80010	20	80000	20	80000	26737	86	1	1	80021	10	9	10	80000	10	80000	10	80020	19	43	80019	0	0	1	60	80040	6	0	19	43	19	1	1	5020	0	10	16	0	0	7	10	26705	14	0	4	80000	10	26732	26732	26709	26732	26709
80024	26731	200	0	0	0	0	0	0	45	1	0	0	1	26717	2	1	1	0	25	80010	10	80000	10	80000	50	1166750	0	1	49	23653	0	26731	26731	16672	3	16715	80010	20	80000	20	80000	26731	77	1	1	80021	10	9	10	80000	10	80000	10	80000	0	44	80000	0	0	0	38	80039	6	1	39	0	0	0	0	5020	0	10	16	0	0	10	7	26733	13	13	5	80000	10	26737	26737	26716	26716	26715
80024	26714	200	1	0	1	1	0	0	67	1	0	0	0	26716	2	1	12	19	25	80010	10	80000	10	80000	50	1167201	0	0	49	23655	0	26731	26728	16678	3	16724	80010	20	80000	20	80000	26737	64	1	1	80021	10	9	10	80000	10	80000	10	80020	19	0	80019	0	0	0	21	80040	6	1	19	43	19	0	0	5020	0	7	16	0	0	7	10	26736	13	13	5	80000	10	26737	26737	26737	26716	26737
80024	26736	200	1	1	1	0	0	0	66	1	0	0	0	26721	3	7	0	20	25	80010	10	80000	10	80000	50	1167106	0	1	49	23657	0	26736	26736	16682	3	16875	80010	20	80000	20	80000	26736	85	1	1	80021	10	9	10	80000	10	80000	10	80020	19	43	80058	0	0	0	21	80039	6	1	19	0	19	0	0	5020	0	10	16	0	0	10	10	26733	13	13	5	80000	10	26715	26737	26716	26737	26738
80024	26715	200	1	0	0	0	0	0	66	1	0	0	3	26721	3	0	7	20	25	80010	10	80000	10	80000	50	1166800	0	1	49	23656	0	26736	26715	16660	3	16721	80010	20	80000	20	80000	26736	85	1	1	80021	10	9	10	80000	10	80000	10	80019	19	43	80019	1	0	1	60	80040	6	0	60	0	19	0	0	5020	0	8	16	0	0	7	10	26733	7	0	5	80000	10	26737	26715	26737	26737	26738
80025	26737	200	1	0	1	0	0	0	67	1	0	0	0	26721	3	7	7	20	25	80010	10	80000	10	80000	50	1167852	0	1	49	23656	0	26736	26736	16660	3	16726	80010	20	80000	20	80000	26715	85	1	1	80021	10	9	10	80000	10	80000	10	80020	19	43	80019	0	0	1	61	80040	6	1	59	43	19	0	0	5020	0	7	16	0	0	10	10	26733	0	13	5	80000	10	26738	26738	26715	26738	26737
80024	26736	200	1	0	0	1	0	0	66	1	0	0	1	26716	2	1	1	0	25	80010	10	80000	10	80000	50	1167201	0	1	49	23651	0	26731	26731	16676	3	16853	80010	20	80000	20	80000	26736	64	1	1	80021	10	9	10	80000	10	80000	10	80020	20	43	80019	1	0	0	61	80039	6	1	59	0	19	1	0	5020	0	7	16	0	0	7	10	26734	13	0	0	80000	10	26716	26738	26738	26737	26737
80024	26736	200	1	0	0	1	0	1	183	1	0	0	3	26700	2	7	7	21	25	80010	10	80000	10	80000	50	1173975	0	1	49	23656	0	26736	26714	16660	3	16695	80010	20	80000	20	80000	26736	64	1	1	80021	10	9	10	80000	10	80000	10	80020	20	43	80059	1	0	0	61	80039	6	1	59	43	19	3	0	5020	0	10	16	0	0	10	7	26734	0	13	0	80000	10	26738	26737	26715	26737	26737

LDRB

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations