Firestorm: MRS (APRR) measurements

Code:

  mrs x0, s3_6_c15_c1_5

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	82	83	flush restart other nonspec (84)	85	inst all (8c)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1037	8	0	1022	26	1000	1000	1	1037	1037	865	3	885	1037	164	1	1	1001	0	0	73	1	26	1	1	1034	1000	1000	1038	1038	1038	1038	1038
1004	1037	8	0	1022	26	1000	1000	0	1037	1037	865	3	885	1037	164	1	1	1001	0	6	73	1	26	1	1	1034	1000	1000	1038	1038	1038	1038	1038
1004	1037	8	0	1022	26	1000	1000	0	1037	1037	865	3	885	1037	164	1	1	1001	0	3	73	1	26	1	1	1034	1000	1000	1038	1038	1038	1038	1038
1004	1037	8	0	1022	26	1000	1000	1	1037	1037	865	3	885	1037	164	1	1	1001	0	0	73	1	26	1	1	1034	1000	1000	1038	1038	1038	1038	1038
1004	1037	8	0	1022	26	1000	1000	1	1037	1037	865	3	885	1037	164	1	1	1001	0	0	73	1	26	1	1	1034	1000	1000	1038	1038	1038	1038	1038
1004	1037	8	12	1022	26	1000	1000	1	1037	1037	865	3	885	1037	164	1	1	1001	0	0	73	1	26	1	1	1034	1000	1000	1038	1038	1038	1038	1038
1004	1037	8	0	1022	26	1000	1000	1	1037	1037	865	3	885	1037	164	1	1	1001	0	3	73	1	26	1	1	1034	1000	1000	1038	1038	1038	1038	1038
1004	1037	8	9	1022	26	1000	1000	1	1037	1037	865	3	885	1037	164	1	1	1001	0	0	73	1	26	1	1	1034	1000	1000	1038	1038	1038	1038	1038
1004	1037	8	0	1022	26	1000	1000	0	1037	1037	865	3	885	1037	164	1	1	1001	1	0	73	1	26	1	1	1034	1000	1000	1038	1038	1038	1038	1038
1004	1037	8	12	1022	26	1000	1000	1	1037	1037	865	3	885	1037	164	1	1	1001	0	0	73	1	26	1	1	1034	1000	1000	1038	1038	1038	1038	1038

Count: 8

Code:

  mrs x0, s3_6_c15_c1_5
  mrs x1, s3_6_c15_c1_5
  mrs x2, s3_6_c15_c1_5
  mrs x3, s3_6_c15_c1_5
  mrs x4, s3_6_c15_c1_5
  mrs x5, s3_6_c15_c1_5
  mrs x6, s3_6_c15_c1_5
  mrs x7, s3_6_c15_c1_5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80062	620	0	0	0	80022	26	80100	80100	100	500	0	49	76957	80037	80037	69966	3	69986	100	200	200	80037	164	1	1	80201	100	99	100	100	100	0	0	0	5110	3	25	3	3	80034	80000	80100	80038	80038	80038	80038	80038
80204	80037	620	0	0	0	80022	26	80100	80100	100	500	1	49	76957	80037	80037	69966	3	69986	100	200	200	80037	164	1	1	80201	100	99	100	100	100	0	3	0	5131	3	25	3	3	80034	80000	80100	80038	80038	80038	80038	80038
80204	80073	621	0	9	0	80022	26	80100	80100	100	500	1	49	76957	80037	80037	69966	3	69986	100	200	200	80037	164	1	1	80201	100	99	100	100	100	0	0	0	5110	3	25	3	3	80034	80000	80100	80038	80038	80038	80038	80038
80204	80037	620	0	0	0	80022	26	80100	80100	100	500	0	49	76957	80037	80037	69966	3	69986	100	200	200	80037	164	1	1	80201	100	99	100	100	100	0	0	0	5110	3	25	3	3	80034	80000	80100	80038	80038	80038	80038	80038
80204	80037	621	0	0	0	80022	26	80100	80100	102	566	0	49	76957	80037	80037	69966	3	69986	100	200	200	80037	164	1	1	80201	100	99	100	100	100	0	3	0	5110	3	25	3	3	80034	80000	80100	80038	80038	80038	80038	80038
80204	80037	620	0	0	0	80022	26	80100	80100	114	500	1	49	76957	80037	80037	69966	3	69986	100	200	200	80037	164	1	1	80201	100	99	100	100	100	0	0	0	5110	3	25	3	3	80034	80000	80100	80038	80038	80038	80038	80038
80204	80037	621	0	0	0	80022	26	80100	80100	100	500	0	49	76957	80037	80037	69966	3	69986	100	200	200	80037	164	1	1	80201	100	99	100	100	100	0	0	0	5110	3	25	2	3	80034	80000	80100	80038	80038	80038	80038	80038
80204	80037	620	0	0	0	80022	26	80100	80100	100	500	0	49	76957	80037	80037	69966	3	69986	100	200	200	80037	164	1	1	80201	100	99	100	100	100	1	0	0	5110	3	25	3	3	80034	80000	80100	80038	80038	80038	80038	80038
80204	80037	620	0	0	0	80022	26	80100	80100	100	500	1	49	76957	80037	80037	69966	3	69986	100	200	200	80037	164	1	1	80201	100	99	100	100	100	0	0	0	5110	3	25	3	3	80034	80000	80100	80038	80038	80038	80038	80038
80204	80037	621	0	0	0	80022	26	80100	80100	100	500	1	49	76957	80037	80037	69966	3	69986	100	200	200	80037	164	1	1	80201	100	99	100	100	100	0	0	0	5110	3	25	3	3	80034	80000	80100	80038	80038	80038	80038	80038

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	80050	621	0	0	0	80022	26	80010	80010	10	50	0	49	76957	80037	80037	69988	12	70008	10	20	20	80037	164	1	1	80021	10	9	10	10	10	8	0	0	0	5020	4	25	5	4	80034	80000	80010	80038	80038	80038	80038	80038
80024	80037	620	0	0	0	80022	26	80010	80010	10	50	1	49	76957	80037	80037	69988	3	70008	10	20	20	80037	164	1	1	80021	10	9	10	10	10	29	0	0	0	5020	4	25	4	2	80034	80000	80010	80038	80038	80038	80038	80038
80024	80037	621	0	0	0	80022	26	80010	80010	10	50	0	49	76957	80037	80037	69988	3	70008	10	20	20	80037	164	1	1	80021	10	9	10	10	10	81	0	6	0	5020	4	25	4	2	80034	80000	80010	80038	80038	80038	80038	80038
80024	80037	621	0	0	0	80022	26	80010	80010	10	50	1	49	76957	80037	80037	69988	3	70008	10	20	20	80037	164	1	1	80021	10	9	10	10	10	74	0	0	0	5020	4	25	4	4	80034	80000	80010	80038	80038	80038	80038	80038
80024	80037	620	0	0	0	80022	26	80010	80010	10	50	1	49	76957	80037	80037	69988	3	70008	10	20	20	80037	164	1	1	80021	10	9	10	10	10	65	0	0	0	5020	4	25	5	3	80034	80000	80010	80038	80038	80038	80038	80038
80024	80037	621	0	0	0	80022	26	80010	80010	10	50	0	49	76957	80037	80037	69988	3	70008	10	20	20	80037	164	1	1	80021	10	9	10	10	10	10	0	0	0	5020	6	25	4	3	80034	80000	80010	80038	80038	80038	80038	80038
80024	80037	621	0	0	0	80022	26	80010	80010	10	50	1	49	76957	80037	80037	69988	3	70008	10	20	20	80037	164	1	1	80021	10	9	10	10	10	82	0	0	0	5020	2	25	5	2	80034	80000	80010	80038	80038	80038	80038	80038
80024	80037	620	0	0	0	80022	26	80010	80010	10	50	1	49	76957	80037	80037	69988	3	70008	10	20	20	80037	164	1	1	80021	10	9	10	10	10	80	0	0	0	5020	2	25	4	2	80034	80000	80010	80038	80038	80038	80038	80038
80024	80037	621	0	0	0	80022	26	80010	80010	10	50	1	49	76957	80037	80037	69988	3	70008	10	20	20	80037	164	1	1	80021	10	9	10	10	10	63	0	0	0	5020	5	25	4	2	80034	80000	80010	80038	80038	80038	80038	80038
80024	80037	620	0	0	0	80022	26	80010	80070	10	50	1	49	76957	80037	80037	69988	3	70008	10	20	20	80037	164	1	1	80021	10	9	10	10	10	35	0	0	0	5020	2	25	2	5	80034	80000	80010	80038	80038	80038	80038	80038

MRS (APRR)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations