Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MRS (APRR)

Test 1: uops

Code:

  mrs x0, s3_6_c15_c1_5

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)606d6emap stall dispatch (70)map rewind (75)map stall (76)8283flush restart other nonspec (84)85inst all (8c)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1004103780102226100010001103710378653885103716411100100731261110341000100010381038103810381038
1004103780102226100010000103710378653885103716411100106731261110341000100010381038103810381038
1004103780102226100010000103710378653885103716411100103731261110341000100010381038103810381038
1004103780102226100010001103710378653885103716411100100731261110341000100010381038103810381038
1004103780102226100010001103710378653885103716411100100731261110341000100010381038103810381038
10041037812102226100010001103710378653885103716411100100731261110341000100010381038103810381038
1004103780102226100010001103710378653885103716411100103731261110341000100010381038103810381038
1004103789102226100010001103710378653885103716411100100731261110341000100010381038103810381038
1004103780102226100010000103710378653885103716411100110731261110341000100010381038103810381038
10041037812102226100010001103710378653885103716411100100731261110341000100010381038103810381038

Test 2: throughput

Count: 8

Code:

  mrs x0, s3_6_c15_c1_5
  mrs x1, s3_6_c15_c1_5
  mrs x2, s3_6_c15_c1_5
  mrs x3, s3_6_c15_c1_5
  mrs x4, s3_6_c15_c1_5
  mrs x5, s3_6_c15_c1_5
  mrs x6, s3_6_c15_c1_5
  mrs x7, s3_6_c15_c1_5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03191e1f3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80204800626200008002226801008010010050004976957800378003769966369986100200200800371641180201100991001001000005110325338003480000801008003880038800388003880038
80204800376200008002226801008010010050014976957800378003769966369986100200200800371641180201100991001001000305131325338003480000801008003880038800388003880038
80204800736210908002226801008010010050014976957800378003769966369986100200200800371641180201100991001001000005110325338003480000801008003880038800388003880038
80204800376200008002226801008010010050004976957800378003769966369986100200200800371641180201100991001001000005110325338003480000801008003880038800388003880038
80204800376210008002226801008010010256604976957800378003769966369986100200200800371641180201100991001001000305110325338003480000801008003880038800388003880038
80204800376200008002226801008010011450014976957800378003769966369986100200200800371641180201100991001001000005110325338003480000801008003880038800388003880038
80204800376210008002226801008010010050004976957800378003769966369986100200200800371641180201100991001001000005110325238003480000801008003880038800388003880038
80204800376200008002226801008010010050004976957800378003769966369986100200200800371641180201100991001001001005110325338003480000801008003880038800388003880038
80204800376200008002226801008010010050014976957800378003769966369986100200200800371641180201100991001001000005110325338003480000801008003880038800388003880038
80204800376210008002226801008010010050014976957800378003769966369986100200200800371641180201100991001001000005110325338003480000801008003880038800388003880038

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03mmu table walk data (08)1e1f3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
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800248003762000080022268001080010105014976957800378003769988370008102020800371641180021109101010290005020425428003480000800108003880038800388003880038
800248003762100080022268001080010105004976957800378003769988370008102020800371641180021109101010810605020425428003480000800108003880038800388003880038
800248003762100080022268001080010105014976957800378003769988370008102020800371641180021109101010740005020425448003480000800108003880038800388003880038
800248003762000080022268001080010105014976957800378003769988370008102020800371641180021109101010650005020425538003480000800108003880038800388003880038
800248003762100080022268001080010105004976957800378003769988370008102020800371641180021109101010100005020625438003480000800108003880038800388003880038
800248003762100080022268001080010105014976957800378003769988370008102020800371641180021109101010820005020225528003480000800108003880038800388003880038
800248003762000080022268001080010105014976957800378003769988370008102020800371641180021109101010800005020225428003480000800108003880038800388003880038
800248003762100080022268001080010105014976957800378003769988370008102020800371641180021109101010630005020525428003480000800108003880038800388003880038
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