Firestorm: LDRSH (post-index, 32-bit) measurements

Code:

  ldrsh w0, [x6], #8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	1e	20	22	24	2b	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
2005	1040	8	1	2	1	0	73	22	1	0	0	5	12	1025	0	4	11	6	42	25	2000	1000	1000	1000	1000	52804	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1008	9	0	88	1073	7	1	64	28	29	1031	70	8	33	56	7	0	0	73	1	16	1	1	1036	1000	40	34	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	1	1	0	43	30	2	0	0	5	0	1025	0	2	1	5	32	25	2000	1000	1000	1000	1000	52824	45823	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1007	9	0	77	1041	0	0	42	14	27	1051	45	4	27	62	6	2	0	73	1	16	1	1	1036	1000	42	39	1000	1000	1041	1041	1044	1041	1041
2004	1040	7	1	0	1	0	70	24	0	0	0	3	0	1025	19	3	6	5	21	25	2000	1000	1000	1000	1000	52836	45824	1	1050	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1039	7	1	98	1061	13	1	28	20	36	1050	45	8	27	26	6	0	1	73	1	16	1	1	1037	1000	33	41	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	1	1	2	94	22	1	0	0	3	0	1025	22	3	8	8	23	25	2000	1000	1000	1000	1000	52824	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1038	8	0	81	1057	8	0	26	24	44	1061	50	6	38	56	7	1	0	73	1	16	1	1	1037	1000	23	12	1000	1000	1041	1041	1041	1041	1044
2004	1040	8	1	1	1	0	95	0	0	0	0	3	0	1025	0	2	4	4	17	25	2000	1000	1000	1000	1000	52792	45825	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1026	7	1	41	1041	4	0	28	6	36	1056	57	8	38	40	7	4	0	73	1	16	1	1	1036	1000	25	20	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	1	0	0	90	26	0	0	0	2	0	1025	12	2	3	6	32	25	2000	1000	1000	1000	1000	52820	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1008	7	0	100	1037	0	0	23	20	34	1051	52	8	36	48	7	1	0	73	1	16	1	1	1037	1000	43	24	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	0	1	0	89	23	0	0	0	2	0	1025	15	3	4	10	26	25	2000	1000	1000	1000	1000	52824	45823	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1027	19	0	61	1073	7	0	22	20	27	1047	40	7	23	40	7	4	0	73	1	16	1	1	1036	1000	40	20	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	1	1	0	0	55	21	0	0	0	3	0	1025	25	2	6	10	31	25	2000	1000	1000	1000	1000	52824	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1007	7	1	90	1054	4	0	32	6	26	1018	51	7	28	48	6	1	0	73	1	16	1	1	1037	1000	29	31	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	1	0	1	0	72	24	0	0	0	3	0	1025	0	1	1	5	23	25	2000	1000	1000	1000	1000	52836	45825	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1034	6	1	55	1041	1	0	14	8	24	1040	40	7	36	56	7	1	0	73	1	16	1	1	1036	1000	33	32	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	1	1	0	92	0	0	0	0	1	0	1025	0	3	4	3	20	25	2000	1000	1000	1000	1000	52836	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1020	9	1	55	1043	15	1	27	0	33	1054	53	9	41	72	7	2	0	73	1	16	1	1	1037	1000	26	25	1000	1000	1041	1041	1041	1041	1041

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh w0, [x6], #8
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1871

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	20	22	29	3a	3e	3f	40	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50209	71943	538	1	0	0	0	0	443	849	1	720	2	120	71733	773	71805	25	50750	40612	10128	40100	10000	613250	2727160	0	49	68846	71965	71746	65263	0	3	65739	50100	40200	10000	70200	10000	71776	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10977	3	133	495	10666	268	11	895	52	23	10936	124	1	138	2	0	3	2610	2	58	1	1	71613	40524	1153	1040	1021	10000	40100	71893	71763	71992	71898	72277
50204	71898	538	0	0	0	0	0	487	884	1	680	3	140	71729	782	71767	25	50735	40604	10144	40100	10000	616449	2718638	0	49	68665	71952	72026	65516	0	3	65776	50100	40200	10000	70200	10000	71780	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10897	1	153	526	10651	264	12	904	172	67	10913	128	2	125	1	0	3	2610	1	58	1	1	71454	40540	1045	1091	1040	10000	40100	71869	72178	72012	71837	71836
50204	71989	539	1	0	0	0	0	495	869	1	696	1	152	71823	797	71614	25	50660	40628	10126	40100	10000	614143	2724792	0	49	68891	71837	71687	65179	0	3	65470	50100	40200	10000	70200	10000	71689	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10910	3	152	536	10685	280	11	882	30	29	10912	125	2	114	1	0	5	2610	1	58	1	1	71614	40432	1125	1053	1038	10000	40100	71951	71908	71889	72019	71844
50204	71829	538	1	0	0	0	0	486	799	1	736	1	108	71824	805	71545	25	50730	40616	10147	40100	10000	614697	2723845	1	49	68689	72016	71668	65285	0	3	65631	50100	40200	10000	70200	10000	71799	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10913	1	158	498	10641	258	13	961	68	13	10937	127	2	127	2	0	4	2610	1	58	1	1	71743	40573	1023	1109	1133	10000	40100	72061	71757	71817	71777	71775
50204	72016	539	2	1	0	0	0	481	862	1	616	1	116	71959	812	71471	25	50765	40548	10130	40100	10000	613400	2719573	0	49	68969	71855	71704	65339	0	3	65753	50100	40200	10000	70200	10000	71822	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10927	2	144	510	10644	264	15	898	68	32	10940	128	0	140	1	3	3	2610	1	58	1	1	71698	40484	1068	1030	1054	10000	40100	71895	71915	71905	71843	71809
50204	71699	540	1	0	0	0	0	409	831	2	712	1	140	71833	808	71575	25	50760	40604	10136	40100	10000	613166	2725576	0	49	68468	71972	71767	65312	0	3	65541	50100	40200	10000	70200	10000	71923	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10896	2	153	483	10631	275	14	987	72	26	10922	117	2	123	1	0	5	2610	1	58	1	1	71665	40540	1123	1081	1166	10000	40100	71897	71868	71769	71995	71812
50204	71863	538	1	0	0	0	0	458	845	1	696	1	116	71860	783	71449	25	50695	40584	10118	40100	10000	614729	2720658	0	49	68699	71918	71878	65271	0	3	65428	50100	40200	10000	70200	10000	71859	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10893	2	161	517	10653	266	12	918	34	35	10984	126	3	118	1	1	5	2610	1	58	1	1	71644	40540	1041	1044	950	10000	40100	72101	71869	71799	71890	71787
50204	71817	538	2	0	0	0	0	460	784	1	752	1	160	71895	788	71658	25	50825	40656	10119	40100	10000	615427	2721983	0	49	68887	72129	71950	65358	0	3	65542	50100	40200	10000	70200	10000	71863	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10906	0	171	497	10600	265	12	907	26	34	10946	136	2	127	1	1	5	2610	1	58	1	1	71678	40472	1080	1140	1108	10000	40100	71963	71965	71833	72091	71860
50204	71673	538	1	0	1	0	0	459	810	2	696	2	216	71883	783	71555	25	50690	40628	10125	40100	10000	615740	2729218	0	49	68682	71775	71947	65245	0	3	65510	50100	40200	10000	70200	10000	71893	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10922	4	154	490	10687	267	11	978	42	25	10968	131	2	125	1	3	5	2610	1	58	1	1	71659	40540	1169	1083	1068	10000	40100	71940	72052	71886	71777	71900
50204	71860	540	1	0	0	0	0	440	842	1	600	2	156	71929	780	71562	25	50755	40588	10136	40100	10000	615731	2727772	0	49	68844	71705	71913	65259	0	3	65455	50100	40200	10000	70200	10000	71674	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10937	3	147	501	10672	256	16	892	82	14	10920	123	2	124	1	0	5	2610	1	58	1	1	71725	40536	1054	1061	1116	10000	40100	72104	71891	72121	71998	71950

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1819

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50029	72096	539	0	0	0	0	0	2	519	861	2	528	0	292	71783	842	7	3	71557	25	50690	40518	10150	40010	10000	631361	2712595	0	49	68756	0	71734	71943	65524	3	65519	50010	40020	10000	70020	10000	71936	35	2	1	40021	10	9	10	10000	30010	10000	2	10	10908	0	133	535	10673	260	13	920	112	40	10938	147	6	120	0	0	19	0	0	2520	0	5	65	1	1	71645	40544	830	936	822	10000	40010	71828	71857	71784	71706	71799
50024	71800	537	0	0	0	0	0	0	506	831	2	416	1	256	71641	795	6	3	71442	25	50725	40530	10142	40010	10000	629518	2721492	0	49	68676	0	71832	71887	65487	3	65522	50010	40020	10000	70020	10000	71710	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10904	1	168	512	10639	286	12	922	70	60	10912	134	7	133	1	25	7	0	0	2520	0	1	65	1	1	71493	40580	970	946	1004	10000	40010	71954	71840	71882	71902	71796
50024	71779	538	1	0	0	0	0	2	479	850	2	504	1	292	71967	812	5	2	71570	25	50645	40514	10130	40010	10000	628838	2712220	0	49	68763	0	71750	71892	65240	3	65491	50010	40020	10000	70020	10000	71766	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10896	1	167	545	10635	226	8	891	112	41	10929	137	7	136	1	6	4	0	0	2520	0	2	65	2	2	71641	40560	984	842	902	10000	40010	72049	71972	71805	71933	71984
50024	71774	538	1	0	0	0	0	0	493	846	2	568	1	248	71681	824	5	4	71807	25	50705	40538	10134	40010	10000	630136	2718269	0	49	68593	0	71731	71870	65290	3	65372	50010	40020	10000	70020	10000	71837	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10908	1	179	501	10663	275	10	910	80	42	10924	135	6	123	1	8	13	2	0	2520	0	2	65	1	1	71846	40544	996	952	898	10000	40010	71754	71959	71839	71918	71696
50024	71919	538	0	0	0	0	0	1	494	875	2	560	0	264	71982	815	7	2	71589	25	50675	40542	10126	40010	10000	629702	2720379	0	49	68532	0	71817	71993	65226	3	65615	50010	40020	10000	70020	10000	71891	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10894	0	151	524	10671	268	12	896	70	35	10913	128	7	128	0	36	12	0	0	2520	0	1	65	2	2	71798	40584	822	928	966	10000	40010	72223	71852	71848	71977	71736
50024	71763	536	0	0	0	0	0	0	542	848	2	488	1	260	71761	799	5	2	71583	25	50705	40578	10148	40010	10000	630475	2725638	0	49	68688	0	71742	71882	65252	3	65612	50010	40020	10000	70020	10000	71832	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10918	0	159	516	10653	266	14	926	80	38	10934	113	6	133	0	6	10	0	0	2520	0	1	65	1	1	71681	40544	1044	1060	960	10000	40010	72033	71698	71681	71996	71755
50024	71816	537	0	0	0	0	0	0	463	874	2	512	0	252	71698	815	7	4	71617	25	50685	40543	10139	40010	10000	631071	2723257	0	49	68711	0	71913	71647	65259	3	65766	50010	40020	10000	70020	10000	71875	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10897	1	161	522	10675	282	10	917	116	42	10955	122	7	132	1	0	13	0	0	2520	0	1	65	1	1	71750	40512	964	994	874	10000	40010	71771	71816	71751	71962	71962
50024	71817	538	0	0	0	0	0	0	529	836	2	536	0	216	71648	818	5	3	71677	25	50625	40518	10130	40010	10000	630167	2726388	0	49	68738	0	71911	71995	65010	3	65450	50010	40020	10000	70020	10000	71857	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10936	0	144	498	10664	260	11	925	80	49	10939	127	5	141	0	0	5	0	0	2520	0	1	57	1	1	71706	40580	876	986	890	10000	40010	71772	71945	71872	71814	71716
50024	71709	539	0	0	0	0	0	2	561	860	2	608	0	308	71869	829	7	3	71723	25	50715	40494	10135	40010	10000	632890	2716574	0	49	68683	0	71907	71860	65068	3	65412	50010	40020	10000	70020	10000	71665	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10907	0	142	547	10658	251	14	911	68	55	10916	133	7	128	0	0	2	0	0	2520	0	2	57	2	2	71656	40572	862	960	1006	10000	40010	71804	71770	71747	71873	71927
50024	71921	538	1	0	0	0	0	0	512	887	2	536	0	236	71770	823	5	5	71723	25	50650	40462	10137	40010	10000	629297	2713700	0	49	68759	0	71936	71897	65129	3	65640	50010	40020	10000	70020	10000	71883	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10919	1	160	509	10667	279	10	900	106	44	10925	132	6	123	1	14	11	0	0	2520	0	1	65	1	1	71804	40552	846	898	912	10000	40010	71985	71867	71831	71763	71883

Test 3: throughput

Count: 8

Code:

  ldrsh w0, [x6], #8
  ldrsh w0, [x7], #8
  ldrsh w0, [x8], #8
  ldrsh w0, [x9], #8
  ldrsh w0, [x10], #8
  ldrsh w0, [x11], #8
  ldrsh w0, [x12], #8
  ldrsh w0, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3688

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	19	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160209	30148	221	4	0	0	0	0	0	6944	821	1	736	111	120	29542	819	473	1845	1721	2143	25	160176	80170	80000	80100	80000	400780	1302303	1	62	49	26416	29370	29469	9339	0	3	9548	160100	80200	80000	80200	80000	29254	35	1	1	80201	100	99	39	100	80000	100	80000	100	80961	70	413	5782	85187	693	11	957	74	5314	85807	766	139	4703	5950	51	3	4	5110	1	16	1	1	29532	35	80058	599	577	102	80000	80100	29421	29575	29446	29381	29371
160204	29530	219	4	0	0	1	0	0	6921	855	1	792	105	152	29305	777	493	1806	1876	2243	25	160170	80161	80000	80100	80000	400772	1304242	0	68	49	26259	29555	29333	9392	0	3	9333	160100	80200	80000	80200	80000	29426	35	1	1	80201	100	99	50	100	80000	100	80000	100	80955	72	421	5181	85060	723	9	924	38	4510	86801	669	115	5275	4908	49	1	4	5110	1	16	1	1	29379	30	80050	614	584	102	80000	80100	29317	29276	29311	29456	29433
160204	29145	220	3	0	3	0	0	0	6797	823	1	720	122	104	29193	813	407	1622	1835	2061	25	160170	80153	80000	80100	80000	400745	1298476	0	61	49	26558	29404	29354	9336	0	3	9333	160100	80200	80000	80200	80000	29384	35	1	1	80201	100	99	41	100	80000	100	80000	100	80964	51	447	5492	84617	731	14	915	122	5380	85769	830	135	4563	4337	50	3	9	5110	1	16	1	1	29365	34	80056	570	655	115	80000	80100	29533	29450	29351	29362	29398
160204	29574	220	3	0	0	0	1	0	7215	846	1	688	119	108	29341	824	453	1607	1680	1960	25	160157	80153	80000	80100	80000	400764	1298024	0	58	49	26507	29527	29376	9255	0	3	9372	160100	80200	80000	80200	80000	29503	35	1	1	80201	100	99	40	100	80000	100	80000	100	80970	31	407	5279	85214	647	15	952	86	4787	85664	753	132	4836	5705	17	0	8	5110	1	16	1	1	29379	22	80069	612	702	104	80000	80100	29466	29528	29424	29233	29413
160204	29553	233	2	0	0	0	0	0	7217	848	1	776	130	120	29283	813	441	1565	1795	2063	25	160169	80154	80000	80100	80000	400761	1298561	1	57	49	26535	29402	29522	9468	0	3	9606	160100	80200	80000	80200	80000	29546	35	1	1	80201	100	99	52	100	80000	100	80000	100	80992	54	400	5468	84857	668	14	934	80	5395	86191	746	122	4868	4611	44	3	4	5110	1	16	1	1	29579	40	80064	654	582	110	80000	80100	29359	29693	29312	29438	29330
160204	29550	220	3	0	0	0	0	0	6985	837	1	768	116	208	29612	801	499	1520	1607	2262	25	160163	80162	80000	80100	80000	400804	1298699	1	66	49	26590	29644	29335	9463	0	3	9453	160100	80200	80000	80200	80000	29356	35	1	1	80201	100	99	64	100	80000	100	80000	100	80988	74	464	5404	85384	672	11	926	40	5216	85440	735	137	5328	4692	49	6	0	5110	1	16	1	1	29319	28	80052	604	595	118	80000	80100	29509	29700	29359	29471	29309
160204	29430	221	3	0	0	0	0	0	7373	835	1	688	119	156	29363	827	469	1775	1643	2245	25	160169	80154	80000	80100	80000	400823	1302413	1	68	49	26665	29401	29394	9334	0	3	9303	160100	80200	80000	80200	80000	29465	80	1	1	80201	100	99	46	100	80000	100	80000	100	81008	53	459	5721	85619	650	11	915	56	4793	85731	722	119	5080	4719	53	3	5	5110	1	16	1	1	29543	35	80054	569	652	106	80000	80100	29623	29436	29523	29450	29585
160204	29524	221	3	0	0	0	0	0	7511	827	1	752	106	132	29401	821	440	1721	1818	2308	25	160159	80171	80000	80100	80000	400801	1300728	1	71	49	26453	29561	29543	9391	0	3	9403	160100	80200	80000	80200	80000	29322	35	1	1	80201	100	99	39	100	80000	100	80000	100	80939	56	414	5919	85523	677	10	924	34	5168	86105	711	122	5486	5186	18	0	3	5110	1	16	1	1	29329	21	80072	702	534	115	80000	80100	29371	29332	29409	29545	29490
160204	29495	221	1	0	1	0	0	0	6829	834	1	784	117	100	29752	819	446	1770	1714	2240	25	160169	80165	80000	80100	80000	400779	1298543	0	66	49	26401	29390	29516	9489	0	3	9411	160100	80200	80000	80200	80000	29529	35	1	1	80201	100	99	37	100	80000	100	80000	100	80958	50	384	5696	85368	683	12	895	36	5193	86035	715	133	5261	5149	70	0	4	5110	1	16	1	1	29942	26	80047	628	648	113	80000	80100	29493	29546	29313	29448	29762
160204	29573	220	3	3	0	0	0	0	7077	862	1	544	106	148	29620	815	458	1677	1957	2016	25	160145	80181	80000	80100	80000	400791	1306477	1	65	49	26572	29744	29398	9437	0	3	9585	160100	80200	80000	80200	80000	29487	35	1	1	80201	100	99	28	100	80000	100	80000	100	80999	53	456	5748	85234	729	12	980	40	5352	86257	765	135	5307	5216	70	6	8	5110	1	16	1	1	29597	33	80054	609	600	112	80000	80100	29454	29241	29547	29370	29493

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3682

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160029	30029	223	5	5	0	2	0	1	0	6357	809	1	696	105	112	29572	765	366	2114	1719	2156	25	160081	80077	80000	80010	80000	400333	1299111	0	61	49	26273	0	29562	29573	9316	3	9411	160010	80020	80000	80020	80000	29245	35	1	1	80021	10	9	28	10	80000	10	80000	0	10	80973	80	399	5537	85884	676	16	926	72	5614	86058	915	135	5102	5310	88	0	9	5020	0	0	1	16	0	0	0	1	1	29477	22	80072	577	475	114	80000	80010	29421	29422	29180	29203	29486
160024	29691	220	4	2	0	0	0	0	0	7603	815	1	720	109	152	29262	786	412	2042	1882	2117	25	160070	80066	80000	80010	80000	400354	1308694	0	62	49	26402	0	29449	29557	9357	3	9409	160010	80020	80000	80020	80000	29248	35	1	1	80021	10	9	30	10	80000	10	80000	0	10	80977	81	399	5078	85491	695	12	902	38	5528	86263	723	135	5570	5388	86	0	6	5020	0	0	1	16	0	0	0	1	1	29530	18	80065	539	490	113	80000	80010	29377	29498	29291	29238	29497
160024	29662	222	4	0	1	0	0	0	0	6649	804	1	712	104	132	29466	747	389	1951	2041	2136	25	160072	80079	80000	80010	80000	400343	1297234	0	62	49	26133	0	29549	29524	9387	3	9504	160010	80020	80000	80020	80000	29631	35	1	1	80021	10	9	48	10	80000	10	80000	0	10	80939	44	377	5829	85362	624	12	875	42	5320	86480	767	128	5393	5553	72	0	10	5020	0	0	1	16	0	0	0	1	1	29552	26	80064	495	509	112	80000	80010	29266	29407	29406	29603	29525
160024	29500	223	4	0	1	0	0	1	0	6899	781	1	752	109	80	29385	794	404	2073	1767	2211	25	160073	80070	80000	80010	80000	400353	1293391	1	57	49	26302	0	29454	29429	9004	3	9355	160010	80020	80000	80020	80000	29415	35	1	1	80021	10	9	24	10	80000	10	80000	1	10	80921	52	370	5422	85709	661	13	875	48	5783	86226	735	125	5009	5407	53	0	3	5020	0	0	1	16	0	0	0	1	1	29502	34	80056	557	520	143	80000	80010	29382	29519	29505	29443	29631
160024	29236	220	4	0	0	1	0	0	0	6929	785	1	728	117	140	29485	801	401	2035	1693	2119	25	160061	80068	80000	80010	80000	400302	1294995	0	79	49	26435	0	29490	29298	9256	3	9914	160010	80020	80000	80020	80000	29232	35	1	1	80021	10	9	31	10	80000	10	80000	1	10	81002	71	390	5315	85766	698	11	890	42	5237	86349	794	135	5500	5104	69	1	9	5020	0	0	1	16	0	0	0	1	1	29380	17	80062	564	533	113	80000	80010	29385	29607	29351	29393	29585
160024	29497	220	4	0	0	1	0	0	0	7258	778	1	656	125	140	29292	750	355	1969	1961	2040	25	160068	80069	80000	80010	80000	400390	1303333	1	65	49	26227	0	29382	29361	9503	3	9513	160010	80020	80000	80020	80000	29371	35	1	1	80021	10	9	23	10	80000	10	80000	1	10	80985	86	382	5860	85573	657	13	883	38	5403	85828	598	115	5201	5554	87	0	0	5020	0	0	1	16	0	0	0	1	1	29517	21	80057	547	513	109	80000	80010	29472	29415	29427	29368	29499
160024	29615	219	5	1	5	0	0	0	0	7335	750	1	688	103	132	29394	765	427	2029	1918	2134	25	160069	80076	80000	80010	80000	400337	1294820	0	59	49	26138	0	29230	29622	9354	3	9382	160010	80020	80000	80020	80000	29336	35	1	1	80021	10	9	36	10	80000	10	80000	1	10	80963	88	378	5604	85294	622	17	867	40	5810	86120	777	131	5343	5399	90	0	3	5020	0	0	1	16	0	0	0	1	1	29187	25	80067	526	476	108	80000	80010	29626	29666	29264	29367	29387
160024	29450	221	5	0	0	0	0	0	0	7373	798	1	712	109	108	29447	787	378	2151	1755	2089	25	160068	80072	80000	80010	80000	400263	1299957	1	51	49	26413	0	29580	29447	9435	3	9337	160010	80020	80000	80020	80000	29297	35	1	1	80021	10	9	23	10	80000	10	80000	0	10	80972	85	434	5609	85717	664	15	867	32	5507	86787	793	124	4589	5362	72	0	0	5020	0	0	1	16	0	0	0	1	1	29518	34	80056	608	525	103	80000	80010	29597	29545	29275	29445	29399
160024	29396	218	5	0	0	0	0	0	0	6919	786	1	600	110	100	29359	798	367	2044	1884	2169	25	160071	80079	80000	80010	80000	400388	1312005	0	68	49	26368	0	29573	29351	9329	3	9544	160010	80020	80000	80020	80000	29455	35	1	1	80021	10	9	27	10	80000	10	80000	0	10	80934	71	392	5123	85372	664	12	876	64	5470	85989	784	133	5587	4624	69	0	9	5020	0	0	1	16	0	0	0	1	1	29304	31	80070	506	603	106	80000	80010	29563	29418	29245	29543	29515
160024	29523	221	3	0	0	0	0	0	0	7227	764	1	752	88	120	29261	758	369	1767	1960	2154	25	160081	80085	80000	80010	80000	400348	1292918	1	54	49	26289	0	29453	29205	9356	3	9540	160010	80020	80000	80020	80000	29524	35	1	1	80021	10	9	22	10	80000	10	80000	1	10	80994	65	362	6210	85975	647	18	905	30	5343	86604	754	140	4701	5251	67	0	4	5020	0	0	1	16	0	0	0	1	1	29424	20	80068	542	518	97	80000	80010	29218	29582	29324	29200	29459

LDRSH (post-index, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations