Firestorm: LDRSW (unsigned offset) measurements

Code:

  ldrsw x0, [x6, #8]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	394	3	0	0	45	0	0	2	382	2	12	12	16	25	1000	1000	1000	14844	1	389	391	212	3	247	1000	1000	1000	389	71	1	1	1001	1000	1000	1000	0	39	1035	0	35	1035	6	1	35	39	73	1	16	1	1	386	10	6	4	1000	390	395	395	390	390
1004	389	2	0	0	45	0	0	2	379	2	12	12	16	25	1000	1000	1000	15018	0	394	394	216	3	252	1000	1000	1000	394	71	1	1	1001	1000	1000	1000	0	43	1039	0	39	1039	6	1	35	43	73	1	16	1	1	391	10	6	4	1000	395	395	395	390	395
1004	389	3	0	0	41	0	0	2	379	3	12	12	17	25	1000	1000	1000	14838	1	391	389	217	3	252	1000	1000	1000	394	72	1	1	1001	1000	1000	1000	0	43	1039	0	39	1039	6	1	35	43	73	1	16	1	1	391	10	10	4	1000	395	401	395	395	395
1004	389	2	0	0	45	0	0	2	379	2	12	12	16	25	1000	1000	1000	14838	1	394	394	217	3	252	1000	1000	1000	394	71	1	1	1001	1000	1000	1000	0	43	1039	0	39	1039	6	1	39	43	73	1	16	1	1	391	10	6	4	1000	395	399	395	395	395
1004	394	3	0	0	45	0	0	2	374	2	18	12	12	25	1000	1000	1000	14989	1	394	394	217	3	247	1000	1000	1000	394	71	1	1	1001	1000	1000	1000	0	43	1039	0	39	1035	6	1	39	39	73	1	16	1	1	386	10	10	2	1000	390	400	395	395	390
1004	389	3	0	0	45	0	0	2	379	2	12	12	16	25	1000	1000	1000	14838	1	394	394	217	3	251	1000	1000	1000	389	72	1	1	1001	1000	1000	1000	0	39	1039	0	35	1039	6	1	36	39	73	1	16	1	1	391	10	6	4	1000	395	395	395	390	395
1004	394	3	0	0	45	0	0	2	374	2	12	12	16	25	1000	1000	1000	14838	1	394	394	217	3	252	1000	1000	1000	394	72	1	1	1001	1000	1000	1000	0	39	1039	0	39	1039	6	1	35	39	73	1	16	1	1	386	10	10	4	1000	395	400	392	395	395
1004	394	3	0	0	45	0	0	0	379	2	12	18	16	25	1000	1000	1000	14989	0	394	394	217	3	252	1000	1000	1000	394	71	1	1	1001	1000	1000	1000	0	43	1039	0	39	1035	6	1	35	43	73	1	16	1	1	386	10	10	4	1000	395	395	395	395	390
1004	395	3	0	0	41	0	0	2	374	2	18	18	11	25	1000	1000	1000	14838	1	394	394	217	3	252	1000	1000	1000	394	71	1	1	1001	1000	1000	1000	0	39	1039	0	36	1039	6	1	39	43	73	1	16	1	1	391	10	6	4	1000	390	401	390	395	395
1004	389	3	0	0	41	1	0	1	379	2	12	12	16	25	1000	1000	1000	14989	1	394	394	217	3	252	1000	1000	1000	394	71	1	1	1001	1000	1000	1000	0	43	1039	0	39	1035	6	1	35	43	73	1	16	1	1	391	10	10	4	1000	395	396	395	400	395

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsw x0, [x6, #8]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5e	60	69	6a	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70051	525	1	1	0	0	0	0	1	0	1	0	0	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616014	3342254	1	1	49	66971	0	70051	70051	64647	0	3	64954	40100	30200	10000	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	5	2	0	10000	1	1	2610	3	71	2	2	69814	30003	10	10	10	10000	30100	70052	70052	70052	70036	70054
40204	70051	524	0	0	0	0	0	0	1	0	1	0	0	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616014	3342254	0	1	49	66971	0	70051	70051	64631	0	3	64954	40100	30200	10000	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	1	2610	2	71	2	2	69798	30003	10	0	10	10000	30100	70052	70052	70052	70052	70052
40204	70051	525	0	0	0	0	0	0	1	0	1	0	0	0	70344	69764	59710	25	40100	30114	10007	30100	10000	616014	3342254	0	1	49	66972	0	70051	70052	64651	0	3	64938	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	0	1	2610	2	71	2	2	69814	30003	10	0	10	10000	30100	70055	70057	70036	70052	70052
40204	70051	525	0	0	0	0	0	0	1	0	0	0	0	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616014	3341470	0	1	49	66971	0	70035	70051	64647	0	3	64954	40100	30200	10000	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	0	10000	1	1	2610	2	71	2	2	69798	30000	10	0	10	10000	30100	70052	70052	70052	70052	70052
40204	70035	524	0	0	0	0	0	0	1	0	0	0	0	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616014	3342254	0	1	49	66971	0	70035	70051	64647	0	3	64954	40100	30200	10000	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	1	0	0	10000	1	1	2610	2	71	2	2	69814	30003	10	10	10	10000	30100	70052	70052	70052	70036	70036
40204	70098	525	0	0	1	1	0	0	1	0	0	0	0	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616014	3342254	0	1	49	66971	0	70051	70051	64647	0	3	64954	40100	30200	10000	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	1	0	0	10000	0	1	2610	2	71	2	2	69814	30003	10	10	0	10000	30100	70052	70052	70052	70052	70052
40204	70035	525	0	0	0	0	0	0	1	0	1	0	0	0	70036	69782	59710	25	40104	30103	10000	30100	10000	616175	3342254	0	1	49	66971	0	70051	70051	64647	0	3	64954	40100	30200	10000	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	2	0	0	10000	1	0	2610	2	71	2	2	69814	30003	10	10	0	10000	30100	70052	70052	70052	70093	70055
40204	70051	524	0	0	0	0	0	0	4	0	1	0	0	0	70036	69782	59710	25	40104	30103	10000	30100	10000	616014	3342254	0	1	49	66955	0	70051	70051	64647	0	3	64954	40100	30200	10000	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	2	0	0	10000	1	1	2610	2	71	2	2	69814	30003	10	10	10	10000	30100	70052	70036	70052	70052	70054
40204	70051	524	0	0	0	0	0	0	1	0	0	0	0	0	70036	69764	59710	25	40104	30103	10001	30100	10000	616014	3342254	0	1	49	66971	0	70051	70051	64647	0	3	64954	40100	30200	10000	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	2	0	0	10000	1	1	2610	2	71	2	2	69814	30003	10	10	10	10000	30100	70052	70036	70052	70052	70056
40204	70051	524	0	0	0	0	0	0	1	0	0	0	0	0	70020	69782	59710	25	40104	30103	10001	30100	10000	616014	3342254	0	1	49	66971	0	70051	70051	64647	0	3	64954	40100	30200	10000	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	56	0	0	10000	1	1	2610	2	71	2	2	69814	30003	10	10	10	10000	30100	70052	70052	70052	70052	70052

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0056

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70053	525	1	0	0	0	1	1	0	2	0	0	0	1	70026	69702	59773	25	40018	30016	10002	30010	10000	617009	3342494	1	49	66973	70056	70053	64659	0	3	64966	40010	30020	10000	60020	10000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	1	10002	0	2	1	10000	1	1	0	1	1	0	2520	3	71	1	2	69819	30006	9	0	9	10000	30010	70042	70057	70057	70057	70057
40024	70056	525	1	1	1	0	1	1	0	2	0	0	0	0	70026	69702	59715	25	40018	30016	10002	30010	10000	617036	3342734	1	49	66961	70056	70041	64671	0	3	64981	40010	30020	10000	60020	10000	70053	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10002	2	1	10001	0	0	1	10000	1	1	1	1	0	0	2520	1	71	1	2	69804	30006	9	6	0	10000	30010	70057	70054	70057	70062	70057
40024	70056	524	1	0	1	1	0	1	0	2	0	0	0	0	70041	69777	59715	25	40018	30016	10002	30010	10000	617036	3342494	1	49	66976	70056	70041	64674	0	3	64966	40010	30020	10000	60020	10000	70056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	1	10001	0	1	1	10000	1	1	1	1	1	0	2520	2	71	1	2	69819	30006	9	6	9	10000	30010	70054	70057	70042	70057	70054
40024	70056	524	1	0	0	1	1	1	0	1	0	0	0	0	70026	69702	59701	25	40018	30016	10002	30010	10000	617036	3341769	1	49	66961	70056	70041	64659	0	3	64981	40010	30020	10000	60020	10000	70056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10001	0	0	1	10000	1	1	0	1	0	0	2520	2	71	1	1	69804	30003	9	6	0	10000	30010	70042	70057	70057	70057	70057
40024	70056	524	1	1	0	1	0	0	0	2	0	0	0	1	70038	69780	59715	25	40022	30013	10002	30010	10000	616995	3342494	1	49	66976	70056	70056	64659	0	3	64966	40010	30020	10000	60020	10000	70056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	0	10002	0	0	1	10000	0	1	1	1	0	0	2520	1	71	1	1	69825	30006	9	6	9	10000	30010	70057	70042	70057	70057	70054
40024	70056	524	1	1	0	0	0	0	0	2	0	0	0	0	70026	69780	59715	25	40014	30016	10002	30010	10000	617036	3342494	1	49	66976	70056	70056	64674	0	3	64966	40010	30020	10000	60020	10000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10003	0	1	1	10000	1	1	1	1	1	0	2520	2	71	2	1	69819	30003	9	6	9	10000	30010	70057	70057	70057	70057	70057
40024	70041	524	1	0	0	1	0	1	0	2	0	0	0	1	70026	69777	59718	25	40030	30016	10002	30010	10000	617036	3341769	1	49	66973	70056	70053	64674	0	3	64978	40010	30020	10000	60020	10000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	1	10001	0	1	1	10000	1	1	0	1	2	0	2520	1	71	1	1	69804	30006	9	6	9	10000	30010	70057	70042	70042	70054	70057
40024	70056	524	1	1	0	0	1	0	0	2	0	0	0	0	70041	69780	59718	25	40018	30016	10002	30010	10000	617009	3342494	1	49	66973	70041	70056	64666	0	3	64981	40010	30020	10000	60020	10000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	1	10002	0	1	1	10000	0	1	1	1	1	0	2520	1	71	1	1	69819	30006	6	6	0	10000	30010	70057	70042	70054	70042	70057
40024	70056	543	1	1	0	0	1	1	0	2	0	0	0	0	70041	69780	59701	25	40018	30016	10001	30010	10000	619270	3346958	1	49	66961	70056	70056	64674	0	3	64981	40010	30020	10000	60020	10000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10001	0	0	4	10000	1	1	1	1	1	0	2520	1	71	1	2	69804	30003	9	0	9	10000	30010	70057	70057	70057	70054	70057
40024	70056	524	1	0	1	1	0	0	0	2	0	1	0	0	70041	69780	59806	25	40014	30016	10002	30010	10000	617036	3341769	1	49	66976	70056	70041	64674	0	3	64966	40010	30020	10000	60020	10000	70056	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10002	2	1	10004	3	1	1	10000	1	1	0	1	2	0	2544	1	71	1	2	69804	30003	9	6	9	10000	30010	70057	70042	70057	70054	70042

Test 3: throughput

Count: 8

Code:

  ldrsw x0, [x6, #8]
  ldrsw x0, [x6, #8]
  ldrsw x0, [x6, #8]
  ldrsw x0, [x6, #8]
  ldrsw x0, [x6, #8]
  ldrsw x0, [x6, #8]
  ldrsw x0, [x6, #8]
  ldrsw x0, [x6, #8]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	18	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26723	200	0	0	0	41	1	0	1	26712	2	18	18	15	25	80100	100	80000	100	80015	500	1171929	1	49	23627	26722	26727	16635	6	16674	80115	200	80024	200	80024	26727	71	1	1	80201	100	99	100	80000	100	80000	100	80000	39	80000	33	0	0	80000	6	1	35	43	0	1	1	1	5118	0	16	0	0	26719	10	6	4	80000	100	26708	26728	26708	26728	26867
80204	26724	200	0	0	0	41	1	0	2	26712	2	12	12	16	25	80100	100	80000	100	80015	500	1166596	1	49	23647	26707	26727	16635	6	16679	80115	200	80024	200	80024	26727	56	1	1	80201	100	99	100	80000	100	80000	100	80000	0	80000	3	0	35	80000	6	1	35	39	0	1	1	1	5118	1	16	0	0	26704	6	6	2	80000	100	26708	26728	26708	26897	26811
80204	26727	200	0	0	0	45	1	0	1	26692	0	18	12	121	25	80100	100	80000	100	80000	500	1165789	1	49	23642	26727	26727	16630	3	16665	80100	200	80000	200	80000	26707	71	1	1	80201	100	99	100	80000	100	80000	100	80000	39	80039	1	0	39	80039	6	0	0	43	0	0	0	0	5110	1	16	1	1	26724	10	0	0	80000	100	26728	26728	26728	26728	26740
80204	26707	200	0	0	0	45	0	0	2	26712	0	12	0	124	25	80100	100	80000	100	80000	500	1166818	1	49	23627	26707	26727	16650	3	16680	80100	200	80000	200	80000	26727	71	1	1	80201	100	99	100	80000	100	80000	100	80000	0	80035	0	0	35	80035	6	0	35	0	0	0	0	0	5110	1	16	1	1	26704	10	0	4	80000	100	26728	26728	26708	26728	26730
80204	26716	200	0	0	0	45	0	0	2	26707	2	18	0	12	25	80100	100	80000	100	80000	500	1166525	1	49	23647	26727	26722	16650	3	16665	80100	200	80000	200	80000	26727	71	1	1	80201	100	99	100	80000	100	80000	100	80000	39	80039	29	0	3	80000	6	0	0	0	0	0	0	0	5110	1	16	1	1	26724	0	10	4	80000	100	26728	26728	26728	26723	26723
80204	26735	200	0	0	0	45	0	0	0	26712	2	0	18	11	25	80100	100	80000	100	80000	500	1166525	1	49	23635	26727	26727	16630	3	16685	80100	200	80000	200	80000	26727	71	1	1	80201	100	99	100	80000	100	80000	100	80000	39	80035	26	0	39	80000	0	1	0	43	0	0	0	0	5110	1	16	1	1	26724	0	6	0	80000	100	26723	26731	26729	26708	26717
80204	26728	200	1	0	0	45	0	0	2	26692	0	0	12	12	25	80100	100	80000	100	80000	500	1166525	1	49	23647	26707	26727	16630	3	16685	80100	200	80000	200	80000	26707	72	1	1	80201	100	99	100	80000	100	80000	100	80000	0	80039	3	2	39	80035	6	1	35	43	0	0	0	0	5110	1	16	1	1	26724	0	6	4	80000	100	26728	26728	26728	26708	26725
80204	26727	200	0	0	0	45	1	0	0	26712	0	12	12	115	25	80100	100	80000	100	80000	500	1165789	1	49	23647	26727	26727	16633	3	16685	80100	200	80000	200	80000	26727	71	1	1	80201	100	99	100	80000	100	80000	100	80000	0	80039	2	0	0	80000	6	1	0	43	0	0	0	0	5110	1	16	1	1	26724	10	0	0	80000	100	26708	26728	26708	26728	26739
80204	26722	200	0	0	0	45	0	0	0	26712	2	0	12	118	25	80100	100	80000	100	80000	500	1177038	1	49	23642	26727	26727	16650	3	16685	80100	200	80000	200	80000	26727	72	1	1	80201	100	99	100	80000	100	80000	100	80000	39	80000	1	0	39	80000	6	1	39	0	0	0	0	0	5110	1	16	1	1	26724	10	6	2	80000	100	26728	26708	26728	26708	26722
80204	26727	200	0	0	0	0	0	0	2	26712	2	12	0	16	25	80100	100	80000	100	80000	500	1165789	1	49	23647	26727	26727	16630	3	16685	80100	200	80000	200	80000	26727	71	1	1	80201	100	99	100	80000	100	80000	100	80000	39	80039	1	0	42	80039	6	1	39	43	0	0	0	0	5110	1	16	1	1	26724	10	6	4	80000	100	26728	26730	26708	26728	26708

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d5	map dispatch bubble (d6)	d9	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26737	200	1	1	0	0	0	0	0	0	67	1	0	0	3	26722	2	7	7	2	25	80010	10	80390	10	80000	50	1169933	0	0	49	23656	26737	26737	16681	3	16716	80010	20	80000	20	80000	26715	86	1	1	80021	10	9	1	10	80000	10	80000	1	10	80019	20	45	0	80019	0	1	0	67	80041	6	1	59	43	19	0	5020	0	2	16	0	0	3	3	26733	13	0	0	80000	10	26722	26731	26750	26721	26738
80024	26737	200	1	1	1	1	0	0	1	1	67	0	0	0	2	26721	3	7	0	20	25	80010	10	80000	10	80000	50	1173975	0	0	49	23656	26737	26736	16681	3	16716	80010	20	80000	20	80000	26740	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80021	19	0	0	80058	0	5	1	66	80000	6	1	59	0	19	2	5020	0	4	16	0	0	3	1	26711	0	13	5	80000	10	26737	26737	26737	26799	26893
80024	26737	200	1	0	1	0	0	0	0	0	66	1	0	0	2	26721	0	7	0	19	25	80010	10	80000	10	80000	50	1167298	0	1	49	23656	26753	26715	16660	3	16717	80010	20	80000	20	80000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80021	20	43	0	80058	0	38	0	30	80040	0	0	58	43	19	2	5020	0	4	16	0	0	4	1	26712	13	13	5	80000	10	26715	26716	26716	26716	26825
80024	26748	200	1	0	0	1	0	0	0	0	66	1	0	0	2	26721	2	0	7	19	25	80010	10	80000	10	80000	50	1173074	0	1	49	23656	26737	26737	16681	3	16716	80010	20	80000	20	80000	26737	86	1	1	80021	10	9	0	10	80000	10	80000	0	10	80158	20	43	0	80059	0	0	1	21	80039	6	1	58	43	19	0	5020	3	1	16	0	0	1	3	26733	13	13	5	80000	10	26737	26737	26737	26737	26829
80024	26740	200	1	0	0	1	0	0	0	0	21	1	0	0	3	26722	2	0	7	19	25	80010	10	80000	10	80000	50	1173975	0	1	49	23656	26737	26736	16681	3	16716	80010	20	80000	20	80000	26714	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	21	0	0	80057	0	29	2	70	80000	0	1	60	43	19	2	5020	0	1	16	0	0	1	3	26733	13	13	5	80000	10	26715	26715	26715	26716	26872
80024	26748	200	1	1	0	1	1	1	0	0	67	0	0	0	2	26700	2	0	0	19	25	80010	10	80000	10	80000	50	1169451	0	1	49	23635	26715	26736	16659	3	16716	80010	20	80000	20	80000	26737	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	19	0	0	80059	1	1	0	63	80039	6	1	58	43	19	1	5020	0	5	16	0	0	8	3	26734	13	13	5	80000	10	26719	26759	26737	27015	26810
80024	26736	200	1	1	0	1	0	0	0	0	66	1	0	0	2	26728	3	0	0	19	25	80010	10	80000	10	80000	50	1166960	0	0	49	23657	26736	26736	16663	3	16694	80010	20	80000	20	80000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80021	20	43	0	80059	0	2	0	64	80040	6	1	59	43	19	0	5020	0	4	16	0	0	4	2	26733	13	13	0	80000	10	26737	26737	26715	26737	26817
80024	26751	200	1	1	0	0	0	0	0	0	67	1	0	0	1	26700	2	0	0	1	25	80010	10	80000	10	80000	50	1169451	0	0	49	23656	26715	26737	16681	3	16694	80010	20	80000	20	80000	26737	64	1	1	80021	10	9	0	10	80000	10	80000	0	10	80021	20	0	0	80057	1	53	2	36	80039	6	0	59	43	19	1	5020	0	3	16	0	0	2	5	26712	13	13	5	80000	10	26715	26715	26715	26737	26873
80024	26748	200	1	0	1	1	0	0	0	0	66	0	0	0	1	26721	3	7	7	5	25	80010	10	80000	10	80000	50	1165304	0	0	49	23634	26737	26714	16681	3	16716	80010	20	80000	20	80000	26737	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80021	20	43	0	80019	1	30	0	73	80000	6	1	59	0	19	0	5020	0	4	16	0	0	4	2	26711	0	13	5	80000	10	26715	26737	26715	26737	26737
80024	26741	200	1	1	1	0	1	0	0	0	21	0	0	0	3	26722	2	0	0	19	25	80010	10	80000	10	80000	50	1167793	0	0	49	23635	26736	26736	16682	3	16717	80010	20	80000	20	80000	26737	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	20	45	0	80019	1	39	0	30	80040	6	1	61	43	19	0	5020	0	1	16	0	0	1	3	26734	0	13	0	80000	10	26716	26715	26738	26715	26857

LDRSW (unsigned offset)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations