Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
yield
(no loop instructions)
Retires: 1.000
Issues: 0.000
Integer unit issues: 0.000
Load/store unit issues: 0.000
SIMD/FP unit issues: 0.000
retire uop (01) | cycle (02) | 03 | 3f | 51 | 60 | 6d | 6e | map rewind (75) | map stall (76) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | f5 | f6 | f7 | f8 | fd |
1004 | 153 | 1 | 28 | 150 | 0 | 153 | 153 | 3 | 10 | 153 | 153 | 1 | 1 | 1001 | 0 | 74 | 1 | 16 | 1 | 1 | 150 | 154 | 154 | 154 | 154 | 154 |
1004 | 153 | 1 | 28 | 150 | 1 | 153 | 153 | 3 | 10 | 153 | 153 | 1 | 1 | 1001 | 0 | 74 | 1 | 16 | 1 | 1 | 150 | 154 | 154 | 154 | 154 | 154 |
1004 | 153 | 1 | 28 | 150 | 1 | 153 | 153 | 3 | 10 | 153 | 153 | 1 | 1 | 1001 | 0 | 74 | 1 | 16 | 1 | 1 | 150 | 154 | 154 | 154 | 154 | 154 |
1004 | 153 | 1 | 28 | 150 | 1 | 153 | 153 | 3 | 10 | 153 | 153 | 1 | 1 | 1001 | 0 | 74 | 1 | 16 | 1 | 1 | 150 | 154 | 154 | 154 | 154 | 154 |
1004 | 153 | 1 | 28 | 150 | 0 | 153 | 153 | 3 | 10 | 153 | 153 | 1 | 1 | 1001 | 0 | 74 | 1 | 16 | 1 | 1 | 150 | 154 | 154 | 154 | 154 | 154 |
1004 | 153 | 1 | 28 | 150 | 0 | 153 | 153 | 3 | 10 | 153 | 153 | 1 | 1 | 1001 | 0 | 74 | 1 | 16 | 1 | 1 | 150 | 154 | 154 | 154 | 154 | 154 |
1004 | 153 | 1 | 28 | 150 | 1 | 153 | 153 | 3 | 10 | 153 | 153 | 1 | 1 | 1001 | 0 | 74 | 1 | 16 | 1 | 1 | 150 | 154 | 154 | 154 | 154 | 154 |
1004 | 153 | 1 | 28 | 150 | 1 | 153 | 153 | 3 | 10 | 153 | 153 | 1 | 1 | 1001 | 0 | 74 | 1 | 16 | 1 | 1 | 150 | 154 | 154 | 154 | 154 | 154 |
1004 | 153 | 1 | 28 | 150 | 0 | 153 | 153 | 3 | 10 | 153 | 153 | 1 | 1 | 1001 | 0 | 74 | 1 | 16 | 1 | 1 | 150 | 154 | 154 | 154 | 154 | 154 |
1004 | 153 | 1 | 28 | 150 | 1 | 153 | 153 | 3 | 10 | 153 | 153 | 1 | 1 | 1001 | 0 | 74 | 1 | 16 | 1 | 1 | 150 | 154 | 154 | 154 | 154 | 154 |
Code:
yield
(fused SUBS/B.cc loop)
Result (median cycles for code): 0.1310
retire uop (01) | cycle (02) | 03 | 1e | 3f | 51 | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | 60 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | 9f | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
10204 | 1314 | 10 | 3 | 35 | 804 | 100 | 100 | 100 | 500 | 0 | 1310 | 1310 | 3 | 18 | 100 | 200 | 200 | 1310 | 1035 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 100 | 711 | 1 | 16 | 1 | 1 | 1307 | 100 | 1311 | 1311 | 1311 | 1311 | 1311 |
10204 | 1310 | 9 | 0 | 35 | 804 | 100 | 100 | 100 | 500 | 0 | 1310 | 1310 | 3 | 18 | 100 | 200 | 200 | 1310 | 1035 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 100 | 711 | 1 | 16 | 1 | 1 | 1307 | 100 | 1311 | 1311 | 1311 | 1311 | 1311 |
10204 | 1310 | 9 | 0 | 35 | 804 | 100 | 100 | 100 | 500 | 0 | 1310 | 1310 | 3 | 18 | 100 | 200 | 200 | 1310 | 1035 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 100 | 711 | 1 | 16 | 1 | 1 | 1307 | 100 | 1311 | 1311 | 1311 | 1311 | 1311 |
10204 | 1310 | 9 | 0 | 35 | 804 | 100 | 100 | 100 | 500 | 0 | 1310 | 1310 | 3 | 18 | 100 | 200 | 200 | 1310 | 1035 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 100 | 711 | 1 | 16 | 1 | 1 | 1307 | 100 | 1311 | 1311 | 1311 | 1311 | 1311 |
10204 | 1310 | 10 | 0 | 35 | 804 | 100 | 100 | 100 | 500 | 1 | 1310 | 1310 | 3 | 18 | 100 | 200 | 200 | 1310 | 1035 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 100 | 711 | 1 | 16 | 1 | 1 | 1307 | 100 | 1311 | 1311 | 1311 | 1311 | 1311 |
10204 | 1310 | 9 | 0 | 35 | 804 | 100 | 100 | 100 | 500 | 0 | 1310 | 1310 | 3 | 18 | 100 | 200 | 200 | 1310 | 1035 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 100 | 711 | 1 | 16 | 1 | 1 | 1307 | 100 | 1311 | 1311 | 1311 | 1311 | 1311 |
10204 | 1310 | 10 | 0 | 35 | 804 | 100 | 100 | 100 | 500 | 0 | 1310 | 1310 | 3 | 18 | 100 | 200 | 200 | 1310 | 1035 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 100 | 711 | 1 | 16 | 1 | 1 | 1307 | 100 | 1311 | 1311 | 1311 | 1311 | 1311 |
10204 | 1310 | 9 | 0 | 35 | 804 | 100 | 100 | 100 | 500 | 0 | 1310 | 1310 | 3 | 18 | 100 | 200 | 200 | 1310 | 1035 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 100 | 711 | 1 | 16 | 1 | 1 | 1307 | 100 | 1311 | 1311 | 1311 | 1311 | 1311 |
10204 | 1310 | 10 | 0 | 35 | 804 | 100 | 100 | 100 | 500 | 0 | 1310 | 1310 | 3 | 18 | 100 | 200 | 200 | 1310 | 1035 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 100 | 711 | 1 | 16 | 1 | 1 | 1307 | 100 | 1311 | 1311 | 1311 | 1311 | 1311 |
10204 | 1310 | 10 | 3 | 35 | 804 | 100 | 100 | 100 | 500 | 0 | 1310 | 1310 | 3 | 18 | 100 | 200 | 200 | 1310 | 1035 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 100 | 711 | 1 | 16 | 1 | 1 | 1307 | 100 | 1311 | 1311 | 1311 | 1311 | 1311 |
Result (median cycles for code): 0.1288
retire uop (01) | cycle (02) | 03 | 1e | 3f | 51 | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | 9f | l1d cache writeback (a8) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
10024 | 1292 | 9 | 0 | 35 | 1232 | 10 | 10 | 10 | 50 | 1288 | 1288 | 3 | 18 | 10 | 20 | 20 | 1288 | 1288 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10 | 0 | 0 | 643 | 2 | 16 | 2 | 2 | 1285 | 10 | 1289 | 1289 | 1289 | 1289 | 1289 |
10024 | 1288 | 9 | 0 | 35 | 1232 | 10 | 10 | 10 | 50 | 1288 | 1288 | 3 | 18 | 10 | 20 | 20 | 1288 | 1288 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10 | 0 | 0 | 643 | 3 | 16 | 2 | 3 | 1285 | 10 | 1289 | 1289 | 1337 | 1289 | 1289 |
10024 | 1288 | 10 | 0 | 35 | 1232 | 10 | 10 | 10 | 50 | 1288 | 1288 | 3 | 18 | 10 | 20 | 20 | 1288 | 1288 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10 | 0 | 0 | 643 | 2 | 16 | 3 | 3 | 1285 | 10 | 1289 | 1289 | 1289 | 1289 | 1289 |
10024 | 1288 | 9 | 0 | 35 | 1232 | 10 | 10 | 10 | 50 | 1288 | 1288 | 3 | 18 | 10 | 20 | 20 | 1288 | 1288 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10 | 0 | 0 | 643 | 3 | 16 | 2 | 2 | 1285 | 10 | 1289 | 1289 | 1289 | 1289 | 1289 |
10024 | 1288 | 9 | 0 | 35 | 1232 | 10 | 10 | 10 | 50 | 1288 | 1288 | 3 | 18 | 10 | 20 | 20 | 1288 | 1288 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10 | 0 | 0 | 642 | 3 | 16 | 2 | 2 | 1285 | 10 | 1289 | 1289 | 1289 | 1289 | 1289 |
10024 | 1288 | 9 | 0 | 35 | 1232 | 10 | 10 | 10 | 50 | 1288 | 1288 | 3 | 18 | 10 | 20 | 20 | 1288 | 1288 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10 | 0 | 0 | 642 | 3 | 16 | 3 | 3 | 1285 | 10 | 1289 | 1289 | 1289 | 1289 | 1289 |
10024 | 1288 | 10 | 3 | 35 | 1232 | 10 | 10 | 10 | 50 | 1288 | 1288 | 3 | 18 | 10 | 20 | 20 | 1288 | 1288 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10 | 0 | 0 | 643 | 2 | 16 | 3 | 3 | 1285 | 10 | 1289 | 1289 | 1289 | 1289 | 1289 |
10024 | 1288 | 9 | 0 | 35 | 1232 | 10 | 10 | 10 | 50 | 1288 | 1288 | 3 | 18 | 10 | 20 | 20 | 1288 | 1288 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10 | 0 | 0 | 642 | 3 | 16 | 3 | 2 | 1285 | 10 | 1289 | 1289 | 1289 | 1289 | 1289 |
10024 | 1288 | 9 | 0 | 35 | 1232 | 10 | 10 | 10 | 50 | 1288 | 1288 | 3 | 18 | 10 | 20 | 20 | 1288 | 1288 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10 | 0 | 0 | 643 | 3 | 16 | 3 | 2 | 1285 | 10 | 1289 | 1289 | 1289 | 1289 | 1289 |
10024 | 1288 | 10 | 0 | 58 | 1232 | 10 | 10 | 10 | 50 | 1288 | 1288 | 3 | 18 | 10 | 20 | 20 | 1288 | 1288 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10 | 0 | 0 | 643 | 3 | 16 | 3 | 3 | 1285 | 10 | 1289 | 1289 | 1289 | 1289 | 1289 |