Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

YIELD

Test 1: uops

Code:

  yield

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 0.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)033f51606d6emap rewind (75)map stall (76)8283flush restart other nonspec (84)85inst all (8c)accfd5map dispatch bubble (d6)ddfetch restart (de)e0f5f6f7f8fd
1004153128150015315331015315311100107411611150154154154154154
1004153128150115315331015315311100107411611150154154154154154
1004153128150115315331015315311100107411611150154154154154154
1004153128150115315331015315311100107411611150154154154154154
1004153128150015315331015315311100107411611150154154154154154
1004153128150015315331015315311100107411611150154154154154154
1004153128150115315331015315311100107411611150154154154154154
1004153128150115315331015315311100107411611150154154154154154
1004153128150015315331015315311100107411611150154154154154154
1004153128150115315331015315311100107411611150154154154154154

Test 2: throughput

Code:

  yield

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 0.1310

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int retires (ef)f5f6f7f8fd
102041314103358041001001005000131013103181002002001310103511102011009910010010071111611130710013111311131113111311
10204131090358041001001005000131013103181002002001310103511102011009910010010071111611130710013111311131113111311
10204131090358041001001005000131013103181002002001310103511102011009910010010071111611130710013111311131113111311
10204131090358041001001005000131013103181002002001310103511102011009910010010071111611130710013111311131113111311
102041310100358041001001005001131013103181002002001310103511102011009910010010071111611130710013111311131113111311
10204131090358041001001005000131013103181002002001310103511102011009910010010071111611130710013111311131113111311
102041310100358041001001005000131013103181002002001310103511102011009910010010071111611130710013111311131113111311
10204131090358041001001005000131013103181002002001310103511102011009910010010071111611130710013111311131113111311
102041310100358041001001005000131013103181002002001310103511102011009910010010071111611130710013111311131113111311
102041310103358041001001005000131013103181002002001310103511102011009910010010071111611130710013111311131113111311

1000 unrolls and 10 iterations

Result (median cycles for code): 0.1288

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int retires (ef)f5f6f7f8fd
100241292903512321010105012881288318102020128812881110021109101010006432162212851012891289128912891289
100241288903512321010105012881288318102020128812881110021109101010006433162312851012891289133712891289
1002412881003512321010105012881288318102020128812881110021109101010006432163312851012891289128912891289
100241288903512321010105012881288318102020128812881110021109101010006433162212851012891289128912891289
100241288903512321010105012881288318102020128812881110021109101010006423162212851012891289128912891289
100241288903512321010105012881288318102020128812881110021109101010006423163312851012891289128912891289
1002412881033512321010105012881288318102020128812881110021109101010006432163312851012891289128912891289
100241288903512321010105012881288318102020128812881110021109101010006423163212851012891289128912891289
100241288903512321010105012881288318102020128812881110021109101010006433163212851012891289128912891289
1002412881005812321010105012881288318102020128812881110021109101010006433163312851012891289128912891289