Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ADDS (register, lsr, 64-bit)

Test 1: uops

Code:

  adds x0, x0, x1, lsr #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10042035150611000186225200020001000126235203520351729318661000100020002035411110011000000731431119202000100020362036203620362036
10042035150611000186225200020001000126235203520351729318661000100020002035411110011000000731431119202000100020362036203620362036
10042035160611000186225200020001000126235203520351729318661000100020002035411110011000000731431119202000100020362036203620362036
100420351531231000186225200020001000126235203520351729318661000100020002035411110011000000731431119202000100020362036203620362036
10042035163611000186225200020001000126235203520351729318661000100020002035411110011000012600731431119202000100020362036203620362036
10042035150611000186225200020001000126235203520351729318661000100020002035411110011000000891431119202000100020362036203620362036
10042035160611000186225200020001000126235203520351729318661000100020002035411110011000000731431119202000100020362036203620362036
10042035150611000186225200020001000126235203520351729318661000100020002035411110011000000731431119202000100020362036203620362036
10042035160611000186225200020001000126235203520351729318661000100020002035411110011000000731431119202000100020362036203620362036
10042035150611000186225200020001000127004203520351729318661000100020002035411110011000000731431119202000100020362036203620362036

Test 2: Latency 1->2

Code:

  adds x0, x0, x1, lsr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03181e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204200351500061100001986225201002010010100130512149169552003520035185810318720101001020020200200354111102011009910010100100703710139111992220000101002003620036200362003620036
102042003515000611000019862252010020100101001305121491695520035200351858103187201010010200202002003541111020110099100101001002703710139111992220000101002003620036200362003620036
10204200351500061100001986225201002010010100130512149169552003520035185810318720101001020020200200354111102011009910010100100000710139111992220000101002003620036200362003620036
102042003515000611000019862252010020100101001305121491695520035200351858103187201010010200202002003541111020110099100101001002606710139111992220000101002003620036200362003620036
10204200351500061100001986225201002010010100130512149169552003520035185810318720101001020020200200354111102011009910010100100000710139111992220000101002003620036200362003620036
102042003515000611000019862252010020100101001305121491695520035200351858103187201010010200202002003541111020110099100101001002703710139111992220000101002003620036200362003620036
10204200351500061100001986225201002010010100130512149169552003520035185810318720101001020020200200354111102011009910010100100000710139111992220000101002003620036200362003620036
10204200351500061100001986225201002010010100130812649169552003520035185810318720101001020020200200354111102011009910010100100000710139111992220000101002003620036200362003620036
102042003515000611000019862252010020100101001305121491695520035200351858103187201010010200202002003541111020110099100101001002103710139111992220000101002003620036200362003620036
10204200351500061100001986225201002010010100130512149169552003520035185810318720101001020020200200354111102011009910010100100000710139111992220000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)0309l2 tlb miss instruction (0a)l2 tlb miss data (0b)1e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100242008115000006110000198622520010200101001013052290491695520035200351860331874010010100202002020035411110021109101001010010640241221993020000100102003620036200362003620036
100242003515000006110000198622520010200101001013052290491695520035200351860331874010010100202002020035411110021109101001010000640241221993020000100102003620036200362003620036
100242003515010006110000198622520010200101001013052291491695520035200351860331874010010100202002020035411110021109101001010000640241221993020022100102003620036200362003620036
100242003515000006110000198622520010200101001013052290491695520035200351860331874010010100202002020035411110021109101001010010640241221993020000100102003620036200362003620036
100242003515000006110000198622520010200101001013052290491695520035200351860331874010010100202002020035411110021109101001010000640241221993020000100102003620036200362003620036
100242003515000006110000198622520010200101001013052291491695520035200351860331874010010100202002020035411110021109101001010000640241221993020000100102003620036200362003620036
100242003515000006110000198622520010200101001013052290491695520035200351860331874010010100202002020035411110021109101001010003640241221993020000100102003620036200362003620036
100242003515000006110000198622520010200101001013052290491695520035200351860331874010010100202002020035411110021109101001010000640241221993020000100102003620036200362003620036
100242003515000106110000198622520010200101001013052290491695520035200351860331874010010100202002020035411110021109101001010020640241221993020000100102003620036200362003620036
100242003515000006110000198622520010200101001013052290491695520035200351860331874010010100202002020035411110021109101001010000640241221993020000100102003620036200362003620036

Test 3: Latency 1->3

Code:

  adds x0, x1, x0, lsr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102042003515001561000019868252010020100101051305150491695520035200351860881873510105102162023220035411110201100991001010010000111720016001995420000101002003620036200362003620036
10204200351500611000019868252010020100101051305150491695520035200351861981873510105102162023220035411110201100991001010010000000710139111992220000101002003620036200362003620036
10204200351500611000019862252010020100101001305121491695520035200351858131872010100102002020020035411110201100991001010010000000710139111992220000101002003620036200362003620036
10204200351490611000019862252010020100101001305121491695520035200351858131872010100102002020020035411110201100991001010010000000710139111992220000101002003620036200362003620036
10204200351500611000019862252010020100101001305121491695520035200351858131872010100102002020020035411110201100991001010010000000710139111992220000101002003620036200362003620036
10204200351490611000019862252010020100101001305121491695520035200351858131872010100102002020020035411110201100991001010010013000710139111992220000101002003620036200362003620068
102042003515006110000198622520100201001010013051214916955200352003518581318720101001020020200200354111102011009910010100100213000710139111992220000101002003620036200362003620036
10204200351500611000019862252010020100101001305121491695520035200351858131872010100102002020020035411110201100991001010010000000710139111992220000101002003620036200362003620036
102042003515006110000198622520100201001010013051214916955200352003518581318720101001020020200200354111102011009910010100100383000710139111992220000101002003620036200362003620036
10204200351500611000019862252010020100101001305886491695520035200351858131872010100102002020020035411110201100991001010010000000710139111992220000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1002420035150000000061100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000002000640241521993020000100102003620036200362003620036
1002420035150000000061100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000001000640241221993020000100102003620036200362003620036
10024200351500000000233100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000001000640241221993020000100102003620036200362003620036
1002420035150000000061100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000000000640341221993020000100102003620036200362003620036
1002420035150000000061100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000000000640241221993020000100102003620036200362003620036
10024200351500000000611000019862112200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000004000640241221993020000100102003620036200362003620036
100242003514900000006110000198622520010200101001013052294916955200352003518603318740100101002020020200354111100211091010010100000601230640241221993020000100102003620036200362003620036
1002420035150000000061100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000000000640241221993020000100102003620036200362003620036
1002420035150000000061100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000000000640241221993020000100102003620036200362003620036
1002420035150000000061100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000000000640241221993020000100102003620036200362003620036

Test 4: Latency 4->2

Chain cycles: 1

Code:

  adds x0, x1, x2, lsr #17
  cset x1, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20204300352250611000029899253012230123201071956240492695530035300352739182748520107202243023630035851120201100991002010010100001001111320162998230000201003003630036300363003630036
20204300352250611000029899253010030100201071956240492695530035300352739182748620107202243023630035851120201100991002010010100000401111319162998330000201003003630036300363003630036
20204300352250611000629899683014630100201071956964492695530081300352739172748620107202243023630035851120201100991002010010100220031111319162998230000201003003630036300363003630036
202043003522512611000029899253010030100201071956240492695530035300352739172748620107202243023630035851120201100991002010010100001001111320162998330000201003003630036300363003630036
2020430035225121031000029899253010030100201071956240492695530035300352739172748620107202243023630035851120201100991002010010100000001111319162998230000201003003630036300363003630036
202043003522507261000029899253010030100201071956240492695530035300352739172748620107202243023630035851120201100991002010010100000001111319162998330000201003003630036300363003630036
20204300352240611000029899253010030100201071956240492695530035300352739172748620107202243023630035851120201100991002010010100000001111319162998230000201003003630036300363003630036
20204300352250611000029899253010030100201071956240492695530035300352739172748620107202243023630035851120201100991002010010100000001111320162998230000201003003630036300363003630036
202043003522507261000029899253010030100201071956240492695530035300352739182748520107202243023630035851120201100991002010010100000001111319162998330000201003003630036300363003630036
202043003522507261000029899253010030100201071956240492695530035300352739182748620107202243023630035851120201100991002010010100000001111320162998230000201003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)0309l2 tlb miss instruction (0a)l2 tlb miss data (0b)191e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2002430035225000006110000298912530010300102001019562891492695530035300352739132749820010200203002030035851120021109102001010010000001270133122995930000200103003630036300363003630036
20024300352250000025110000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010000001270133112995930000200103003630036300363003630036
20024300352250000034610000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010002011270133212995930000200103003630036300363003630036
2002430035225000006110000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010000001270133112995930000200103003630036300363003630036
2002430035225000096110000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010000001270133212995930000200103003630036300363003630036
20024300352250000072610000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010000001270133112995930000200103003630036300363003630036
2002430035225000006110000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010000001270133112995930000200103003630036300363003630036
20024300352250000015610000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010001001270133112995930000200103003630036300363003630036
20024300352250000072610000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010000001270133112995930000200103003630036300363003630036
2002430035225000012061100002989125300103001020010195628904926955300353003527391162749820010200203002030035851120021109102001010010000001270133112995930000200103003630036300363003630036

Test 5: Latency 4->3

Chain cycles: 1

Code:

  adds x0, x1, x2, lsr #17
  cset x2, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
202043003522511611000029899253010030100201071956240149250993003530035273918274862010720224302363003585112020110099100201001010000001111319116112998630000201003003630036300363003630036
202043003522511611000029899253010030100201071956240149269553003530035273918274852010720224302363003585112020110099100201001010000001111320116112998730000201003003630036300363003630036
202043003522511611000029899253010030100201071956240149269553007830035273917274862010720224302363003585112020110099100201001010000001111320116112998730000201003003630036300363003630036
202043003522511611001229899253010030100201071956240149269553003530035273917274862010720224302363003585112020110099100201001010000001111319116112998730000201003003630036300363003630036
202043003522511611000029899253010030100201071956240149269553003530035273917274862010720224302363003585112020110099100201001010000001111319116112998730000201003003630036300363003630036
202043003522511611000029899253010030100201071956240149269553003530035273917274862010720224302363003585112020110099100201001010000001111319116112998730000201003003630036300363003630036
202043003522511611000029899253010030100201071956240149269553003530035273918274862010720224302363003585112020110099100201001010000001111319116112998730000201003003630036300363003630036
202043003522511611000029899253010030100201071956240149269553003530035273918274862010720224302363003585112020110099100201001010000001111319116112998630000201003003630036300363003630036
202043003522511611000029899253010030100201071956240149269553003530035273917274862010720224302363003585112020110099100201001010001091111319116112998630000201003003630036300363003630036
202043003522511611000029899253010030100201071956240149269553003530035273918274862010720224302363003585112020110099100201001010000001111320116112998630000201003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)0318191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20024300352250000346100002989125300103001020010195628904926955300353003527391327498200102002030020300358511200211091020010100100000001270233112995930000200103003630036300363003630036
2002430035225000061100002989125300103001020010195628914926955300353003527391327498200102002030020300358511200211091020010100100000001270233212995930000200103003630036300363003630036
2002430035225000082100002989125300103001020010195628914926955300353003527391327498200102002030020300358511200211091020010100100003001270133112995930000200103003630036300823003630036
2002430035225000061100002989125300103001020010195628914926955300353003527391327498200102002030020300358511200211091020010100100000001270133112995930000200103003630036300363003630036
2002430035225000061100242989125300103001020010195628904926955300353003527391327498200102002030020300358511200211091020010100100100001270233112995930000200103003630036300363003630036
2002430035225000061100002989125300103001020010195628914926955300353003527427327498200102002030020300358511200211091020010100100000001270133112995930000200103003630036300363003630036
2002430035225000061100002989125300103001020010195628904926955300353003527391327498201642002030020300358511200211091020010100100000001270133112995930000200103003630036300363003630036
2002430035225000061100002989125300103001020010195628914926955300353003527391327498200102002030020300358511200211091020010100101000001270133112999330000200103003630036300363003630036
2002430035224000061100002989125300103001020010195628904926955300353003527391327498200102002030020300358511200211091020010100100000001270133112995930000200103003630036300363003630036
20024300352250000611000029891253001030010200101956289049270003003530035274273274982001020020300203003585112002110910200101001001000001270133112995930000200103003630036300363003630036

Test 6: throughput

Count: 8

Code:

  adds x0, x8, x9, lsr #17
  adds x1, x8, x9, lsr #17
  adds x2, x8, x9, lsr #17
  adds x3, x8, x9, lsr #17
  adds x4, x8, x9, lsr #17
  adds x5, x8, x9, lsr #17
  adds x6, x8, x9, lsr #17
  adds x7, x8, x9, lsr #17
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
802045341340100006180000487412516010016010080100344000504950330534105341043298290934336080100802001602005341039118020110099100801001001051101241153390160000801005341153411534115341153411
80204534104000001766180000485262516010016010080100344000504950330534105341043298299134339680202802001602005346739118020110099100801001001051101241153390160000801005341153411534115341153411
8020453410400000010380000487412516010016010080100344000504950330534105341043298302434336080100802001602005341039118020110099100801001001351101241153390160000801005341153411534115341153411
8020453410400113306180000487412516010016010080100344000504950330534105341043298290934336080100802001602005341039118020110099100801001000051101241153390160000801005341153411534115341153411
802045341040000006180000487412516010016010080100344000504950330534105341043298290934336080100802001602005341039118020110099100801001000051101241153390160000801005341153411534115341153411
8020453410400000072680000487412516010016010080100344000504950330534105341043298290934336080100802001602005341039118020110099100801001000051101241153390160000801005341153411534115341153411
802045341040000006180000487412516010016010080100344000504950330534105341043298302434336080100802001602005341039118020110099100801001000651101241153390160000801005341153411534115341153411
802045341040000006180000487412516010016010080100344000504950330534105341043298302434336080100802001602005341039118020110099100801001000051101241153390160000801005341153411534115341153411
802045341040000006180000487412516010016010080100344000504950330534105341043298290934336080100802001602005341039118020110099100801001000051101241153390160000801005341153411534115341153411
802045341040000006180000487412516010016010080100344000504950330534105341043298302434336080100802001602005341039118020110099100801001000051101241153390160000801005341153411534115341153411

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6673

retire uop (01)cycle (02)03mmu table walk data (08)1e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfl1i cache miss demand (d3)d5map dispatch bubble (d6)dbddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8002453401399000618000047946251600101600108001034381301495030005343753380432903251343423800108002016002053380391180021109108001010005020432413353360160000800105338153381533815338153381
80024533804000001458000047946251600101600108001034381301495030005338053380432902936343352800108002016002053380391180021109108001010005020132403253360160000800105338153381533815338153381
80024533804000120828000047946251600101600978011234381301495035805338053380432903251343352800108013316002053436391180021109108001010105020032403353360160000800105338153381533815338153381
8002453380400000618000047946251600101600108001034381301495030005338053380432903251343352800108002016002053380391180021109108001010105020032403353360160000800105338153381533815338153381
8002453380400190618000047946251600101600108001034381301495030005338053380432902749343352800108002016002053380391180021109108001010135020032403353360160000800105338153381533815338153381
8002453380399000618000047946251600101600108001034381301495030005338053380432903251343352800108002016002053380391180021109108001010005020032403353360160000800105338153381533815338153381
8002453380400000618000047946251600101600108001034381301495030005338053380432902936343352800108002016002053380391180021109108001010005020022403353360160000800105338153381533815338153381
80024533804000007708000047946251600101600108001034381301495030005338053380432903251343352800108002016002053380391180021109108001010005020132403353360160000800105338153381533815338153381
8002453380399000618000047946251600101600108001034381301495030005338053380432903251343352800108002016002053380391180021109108001010005020032403353360160000800105338153381533815343153381
8002453380400000618000047946251600101600108001034381301495030005338053380432902936343352800108002016002053380391180021109108001010005020132403353360160000800105338153381533815338153381