Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CINC (32-bit)

Test 1: uops

Code:

  cinc w0, w0, hi
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10041035806191725100010001000622501035103580538821000100030001035104111001100010000073127119901000100010361036103610361036
10041035708291725100010001000622501035103580538821000100030001035104111001100010000073127119901000100010361036103610361036
10041035806191725100010001000622501035103580538821000100030001035104111001100010000073127119901000100010361036103610361036
10041035706191725100010001000622501035103580538821000100030001035104111001100010000373127119901000100010361036103610361036
10041035806191725100010001000622501035103580538821000100030001035104111001100010000073127119901000100010361036103610361036
10041035806191725100010001000622501035103580538821000100030001035104111001100010000073127119901000100010361036103610361036
10041035706191725100010001000622501035103580538821000100030001035104111001100010000073127119901000100010361036103610361036
10041035806191725100010001000622501035103580538821000100030001035104111001100010003073127119901000100010361036103610361036
10041035706191725100010001000622501035103580538821000100030001035104111001100010000073127119901000100010361036103610361036
10041035806191725100010001000622501035103580538821000100030001035104111001100010001073127119901000100010361036103610361036

Test 2: Latency 1->2

Code:

  cinc w0, w0, hi
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102041003575216619920251010010100101006471521496955010035100358656387321010010200302001003510211102011009910010100101000071012711999210000101001003610036100361003610036
1020410035750619920251010010100101006471521496955310035100358656387321010010200302001003510211102011009910010100101000971012711999210000101001003610036100361003610036
1020410035750619920251010010100101006471521496955010035100358656387321010010200302001003510211102011009910010100101000071012711999210000101001003610036100361003610036
1020410035750619920251010010100101006471520496955010035100358656387321010010200302001003510211102011009910010100101000071012711999210000101001003610036100361003610036
10204100357605149920251010010100101006471520496955010035100358656387321010010200302001003510211102011009910010100101000071012711999210000101001003610036100361003610036
10204100357502959920251010010100101006471520496955010035100358656387321010010200302001003510211102011009910010100101000071012711999210000101001003610036100361003610036
102041003575312619920251010010100101006471520496955010035100358656387321010010200302001003510211102011009910010100101000071022711999210000101001003610036100361003610036
1020410035750619920251010010100101006471520496955010035100358656387321010010200302001003510211102011009910010100101000071012711999210000101001003610036100361003610036
10204100357518619920251010010100101006471521496955010035100358656387321010010200302001003510211102011009910010100101000071012711999210000101001003610036100361003610036
1020410035750619920251010010100101006471520496955010035100358656387321010010200302001003510211102011009910010100101000071012711999210000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1002410035750619918251001010010100106472461496955100351003586783875410010100203002010035104111002110910100101001000064022722999310000100101003610036100361003610036
10024100357512619918251001010010100106472460496955100351003586783875410010100203002010035104111002110910100101001000064022722999310000100101003610036100361003610036
1002410035750619918251001010010100106472460496955100351003586783875410010100203002010035104111002110910100101001000064022722999310000100101003610036100361003610036
1002410035750619918251001010010100106472461496955100351003586783875410010100203002010035104111002110910100101001000064022722999310000100101003610036100361003610036
1002410035750619918251001010010100106472461496955100351003586783875410010100203002010035104111002110910100101001000364022722999310000100101003610036100361003610036
1002410035750619918251001010010100106472461496955100351003586783875410010100203002010035104111002110910100101001000064022722999310000100101003610036100361003610036
1002410035750619918251001010010100106472460496955100351003586783875410010100203002010035104111002110910100101001000064022722999310000100101003610036100361003610036
1002410035750619918251001010010100106472460496955100351003586783875410010100203002010035104111002110910100101001000064022722999310000100101003610036100361003610036
1002410035750619918251001010010100106472460496955100351003586783875410010100203002010035104111002110910100101001000064022722999310000100101003610036100361003610036
10024100357503599918251001010010100106472461496955100351003586783875410010100203002010035104111002110910100101001002064022722999310000100101003610036100361003610036

Test 3: Latency 1->3

Chain cycles: 1

Code:

  cinc w0, w1, hi
  tst x0, 1
  mov x0, 1
  mov x1, 2
  mov x2, 3

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)18191e1f3a3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20204200351500000000061199302520200202002021212977331491695520035200351742571748520212202244024820035104112020110099201001000000000001111319116112001520100101002003620036200362003620036
20204200351501010000061199262520200202002020012976501491695520035200351740631748120200202004020020035104112020110099201001000000000000001310228221999220100101002003620036200362003620036
20204200351500000000061199262520200202002020012976501491695520035200351740631748120200202004020020035104112020110099201001000000000000001310228221999220100101002003620036200362003620036
20204200351500000000061199262520224202222020012976501491695520035200351740631748120200202004020020035104112020110099201001000000000000001310228221999220100101002003620036200362003620036
20204200351500000000061199262520200202002020012976501491695520035200351740631748120200202004020020035104112020110099201001000000000000001310228221999220100101002003620036200362003620036
20204200351500000000061199262520200202002020012976501491695520035200351740631748120200202004020020035104112020110099201001000000000000001310228221999220100101002003620036200362003620036
202042003515000000000536199262520200202002020012976501491695520035200351740631748120200202004020020035104112020110099201001000000000000001310228221999220100101002003620036200362003620036
20204200351500000000061199262520200202002020012976501491695520035200351740631748120200202004020020035104112020110099201001000000000000001310228221999220100101002003620036200362003620036
20204200351500000000061199262520200202002020012976501491695520035200351740631748120200202004020020035104112020110099201001000000000000001310228111999220100101002003620036200362003620036
20204200351500000000061199262520200202002020012976501491695520035200351740631748120200202004020020035104112020110099201001000000000000001310228221999220100101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3a3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst int alu (97)9fcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20024200351501177061199182520020200202002012972970491695520035200351742831750420020200204002020035104112002110920010100001270127111999520010100102003620036200362003620036
200242003515000061199182520020200202002012972971491695520035200351742831750420020200204002020035104112002110920010100001270127111999520010100102003620036200362003620036
200242003515009061199182520020200202002012972970491695520035200351742831750420020200204002020035104112002110920010100001270127111999520010100102003620036200362003620036
2002420035150024061199182520020200202002012972971491695520035200351742831750420020200204002020035104112002110920010100001270127111999520010100102003620036200362003620036
200242003515006061199182520020200202002012972970491695520081200351742831750420020200204002020035104112002110920010100001270127111999520010100102003620036200362003620036
200242003515000061199182520020200202002012972971491695520035200351742831750420020200204002020035104112002110920010100001270127111999520010100102003620036200362003620036
200242003515009061199182520020200202002012972971491695520035200351742831750420020200204002020035104112002110920010100001270127111999520010100102003620036200362003620036
20024200351500480061199182520020200202002012972971491695520035200351742831750420020200204002020035104112002110920010100001270127111999520010100102003620036200362003620036
200242003515000061199182520020200202002012972970491695520035200351742831750420020200204002020035104112002110920010100001270127111999520010100102003620036200362003620036
200242003515000061199182520020200202002012972971491695520035200351742831750420020200204002020035104112002110920010100001270127111999520010100102003620036200362003620036

Test 4: throughput

Count: 8

Code:

  cinc w0, w8, hi
  cinc w1, w8, hi
  cinc w2, w8, hi
  cinc w3, w8, hi
  cinc w4, w8, hi
  cinc w5, w8, hi
  cinc w6, w8, hi
  cinc w7, w8, hi
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e1f3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)fetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80204267522010000282780118801188012447991649236602674026740166796166898012480232240296267406611802011009910080100801000000111511811602673780018801002674126741267412674126741
802042674020000003132780118801188012447991649236602674026740166796166898012480232240296267406611802011009910080100801000000111511801602673780018801002674126741267412674126741
80204267402000000282780118801188012447991649236602674026740166796166898012480232240296267406611802011009910080100801000000111511801602673780018801002674126741267412674126741
80204267402000000282780118801188012447991649236602674026740166796166898012480232240296267406611802011009910080100801000000111511801602673780018801002674126741267412674126741
802042674020000002827801188011880124479916492366026740267401667961668980124802322402962674066118020110099100801008010001033111511801602673780018801002674126741267412674126741
80204267402000000282780118801188012447991649236602674026740166796166898012480232240296267406611802011009910080100801000000111511801602673780018801002674126741267412674126741
80204267402000000282780118801188012447991649236602674026740166796166898012480232240296267406611802011009910080100801000000111511801602673780018801002674126741267412674126741
80204267402000000282780118801188012447991649236602674026740166796166898012480232240296267406611802011009910080100801000000111511801602673780018801002674126741267412674126741
80204267402000000702780118801188012447991649236602674026740166796166898012480232240296267406611802011009910080100801000000111511801602673780018801002674126741267412674126741
80204267402000000282780118801188012447991649236602674026740166796166898012480232240296267406611802011009910080100801000000111511801602673780018801002674126741267412674126741

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

retire uop (01)cycle (02)031e3a3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
800242672220003592580010800108001047205914923626026706267061666531668480010800202400202670666118002110910800108001005020118112670280000800102670726707267072670726707
800242670620000362580010800108001047205904923626026706267061666531668480010800202400202670666118002110910800108001005020118112670280000800102670726707267072670726707
8002426706200001242580010800108001047205914923626026706267061666531668480010800202400202670666118002110910800108001005020118112670280000800102670726707267072670726707
8002426706200001012580010800108001047205904923626026706267061666531668480010800202400202670666118002110910800108001005020118112670280000800102670726707267072670726707
8002426706200001012580010800108001047205904923626026706267061666531668480010800202400202670666118002110910800108001005020118112670280000800102670726707267072670726707
800242670620000592580010800108001047205904923626026706267061666531668480010800202400202670666118002110910800108001005020118112670280000800102670726707267072670726707
800242670620000362580010800108001047205904923626026706267061666531668480010800202400202670666118002110910800108001005020118112670280000800102670726707267072670726707
8002426706200001662580010800108001047205914923626026706267061666531668480010800202400202670666118002110910800108001005020118112670280000800102670726707267072670726707
8002426706200001012580010800108001047205904923626026706267061666531668480010800202400202670666118002110910800108001005020118112670280000800102670726707267072670726707
8002426706200001242580010800108001047205914923626026706267061666531668480010800202400202670666118002110910800108001005020118112670280000800102670726707267072670726707