Firestorm: LDRH (register, lsl) measurements

Code:

  ldrh w0, [x6, x7, lsl #1]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	19	1e	1f	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	61	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	389	3	0	0	1	0	0	45	0	1	2	384	2	18	18	16	25	1000	1000	1000	15362	0	398	398	221	3	257	1000	1000	2000	399	81	1	1	1001	1000	1000	0	1020	19	42	0	1058	1	0	1	59	1038	6	1	55	42	19	0	73	0	2	16	2	2	395	9	9	2	1000	400	400	400	400	400
1004	399	3	1	1	0	1	0	65	0	0	3	384	2	18	18	16	25	1000	1000	1000	15447	0	399	399	222	3	256	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	0	39	0	1035	0	0	0	39	1035	6	1	35	43	0	0	73	0	2	16	2	2	391	10	6	4	1000	395	395	392	395	390
1004	394	2	0	0	0	0	0	45	0	1	2	379	2	12	12	16	25	1000	1000	1000	15018	0	394	394	217	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	0	39	0	1039	0	0	0	39	1039	6	1	39	43	0	0	73	0	2	16	2	2	391	10	6	4	1000	395	395	395	395	390
1004	394	2	0	0	0	0	0	45	0	0	2	379	2	12	12	12	25	1000	1000	1000	15018	0	394	394	217	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	0	39	0	1039	0	0	0	39	1039	6	1	39	43	0	0	73	0	2	16	2	2	391	10	10	4	1000	395	395	395	395	395
1004	394	3	0	0	0	0	0	48	0	0	2	379	2	12	12	16	25	1000	1000	1000	14989	0	394	394	216	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	0	39	0	1039	0	0	0	39	1039	6	1	35	43	0	0	73	0	2	16	2	2	391	10	10	4	1000	395	395	395	395	395
1004	394	3	0	0	0	0	0	45	0	0	2	379	2	12	12	16	25	1000	1000	1000	14774	0	394	394	217	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	0	39	0	1039	0	0	0	39	1039	6	1	35	43	0	0	73	0	2	16	2	2	391	10	6	4	1000	395	395	390	390	395
1004	389	3	0	0	0	0	0	45	0	0	2	379	2	12	12	16	25	1000	1000	1000	15067	0	394	394	217	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	0	43	0	1039	0	0	0	39	1039	6	1	39	43	0	0	73	0	2	16	2	2	391	10	6	4	1000	395	395	395	395	395
1004	394	3	0	0	0	0	0	45	0	1	2	374	2	18	18	12	25	1000	1000	1000	14989	0	394	394	217	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	0	43	0	1039	0	0	0	39	1039	6	1	39	43	0	0	73	0	2	16	2	2	391	10	10	4	1000	395	395	395	395	395
1004	394	3	0	0	0	0	0	45	0	0	2	379	2	12	12	16	25	1000	1000	1000	15018	0	389	389	217	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	0	39	0	1035	0	0	0	39	1039	6	1	39	43	0	0	73	5	2	16	2	2	391	10	6	4	1000	395	395	395	395	395
1004	394	3	0	0	0	0	0	45	0	0	2	379	2	12	12	16	25	1000	1000	1000	14989	0	396	394	217	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	0	43	0	1039	0	0	0	39	1035	6	1	39	43	0	0	73	5	2	16	2	2	391	10	6	4	1000	390	395	390	390	395

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrh w0, [x6, x7, lsl #1]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	0e	0f	1e	22	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70055	626	1	1	1	1	2	1	3	70026	69702	59712	25	40104	30103	10002	30100	10000	616078	3342350	1	49	66973	70053	70041	64637	3	64956	40100	30200	10000	60200	20000	70053	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10003	1	1	10002	0	1	1	10000	1	1	1	1	1	2616	9	71	4	9	69819	30003	6	0	6	10000	30100	70042	70054	70054	70054	70054
40204	70053	524	1	0	0	0	2	1	3	70020	69764	59706	25	40100	30103	10001	30100	10000	616015	3341470	1	49	66955	70047	70048	64643	3	64950	40100	30200	10000	60200	20000	70049	35	2	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	10000	1	0	0	0	0	2616	9	71	9	9	69810	30003	6	6	0	10000	30100	70048	70048	70048	70036	70048
40204	70035	524	0	0	0	0	1	1	3	70032	69764	59706	25	40104	30100	10001	30100	10000	616175	3342062	1	49	66967	70047	70035	64643	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	2616	7	71	9	4	69798	30000	0	0	9	10000	30100	70048	70048	70036	70036	70048
40204	70035	524	0	0	0	0	0	1	3	70020	69735	59695	25	40104	30100	10000	30100	10000	616015	3342062	1	49	66955	70047	70035	64643	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	2616	9	71	9	4	69810	30003	6	6	0	10000	30100	70036	70048	70048	70036	70048
40204	70051	543	0	0	0	0	1	1	3	70020	69735	59695	25	40104	30100	10000	30100	10000	616015	3342062	1	49	66955	70035	70047	64643	3	64938	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	0	0	0	0	0	2616	7	71	9	9	69810	30003	6	0	6	10000	30100	70036	70036	70048	70048	70036
40204	70048	525	0	0	0	0	0	1	3	70032	69735	59695	25	40104	30103	10000	30263	10000	616015	3341470	1	49	66955	70047	70035	64631	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	1	0	0	10000	0	0	1	0	0	2616	9	71	10	9	69810	30003	6	6	6	10000	30100	70036	70036	70048	70048	70048
40204	70047	525	0	0	0	0	1	1	3	70032	69735	59706	25	40100	30103	10001	30100	10000	616015	3342062	1	49	66955	70035	70035	64643	3	64938	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	0	0	0	0	0	2651	9	71	9	9	69816	30000	0	0	0	10000	30100	70036	70036	70048	70048	70048
40204	70047	524	0	0	1	0	0	1	3	70032	69735	59706	25	40104	30103	10001	30100	10000	616015	3342062	1	49	66955	70047	70047	64631	3	64950	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	0	0	0	0	0	2616	4	71	9	9	69798	30003	0	0	0	10000	30100	70036	70048	70048	70048	70048
40204	70047	525	0	0	0	0	1	1	3	70032	69735	59695	25	40100	30100	10001	30100	10000	616015	3341470	1	49	66955	70047	70047	64631	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	2616	10	71	9	4	69810	30003	0	6	0	10000	30100	70048	70091	70048	70048	70048
40204	70048	524	0	0	0	0	1	1	3	70020	69735	59706	25	40104	30103	10000	30100	10000	616015	3341470	1	49	66973	70047	70047	64643	3	64940	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	2616	10	71	10	9	69810	30003	6	0	6	10000	30100	70048	70036	70048	70048	70048

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	19	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70051	525	0	0	1	0	1	1	0	1	1	0	0	70036	69743	59695	25	40014	30013	10002	30010	10000	617018	3342254	0	1	49	66974	70035	70035	64669	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	0	0	10000	1	1	1	1	0	0	2520	15	71	14	5	69883	30006	13	10	10	10000	30010	70473	70058	70058	70058	70058
40024	70403	525	1	1	1	0	1	1	0	2	1	0	0	70045	69752	59718	25	40018	30013	10002	30010	10000	617045	3342542	0	1	49	66973	70051	70035	64669	3	64979	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	0	2520	14	71	11	5	69815	30012	10	10	10	10000	30010	70053	70036	70052	70055	70036
40024	70035	525	0	0	0	0	1	1	0	1	1	0	0	70039	69775	59710	42	40014	30013	10001	30010	10000	617027	3342254	0	0	49	66955	70054	70054	64669	3	64976	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	0	10000	1	0	1	0	0	0	2520	5	71	6	14	69814	30003	0	10	10	10000	30010	70055	70052	70055	70056	70036
40024	70051	524	0	0	0	0	0	0	0	0	0	0	0	70036	69743	59695	25	40014	30013	10000	30010	10000	617068	3342398	0	1	49	66974	70051	70035	64669	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	1	1	1	1	0	2520	14	71	14	14	69820	30006	0	10	0	10000	30010	70058	70058	70058	70058	70058
40024	70041	524	1	1	1	1	0	0	0	2	1	0	0	70026	69702	59716	25	40014	30016	10005	30010	10000	617045	3342542	0	1	49	66998	70051	70051	64669	3	64976	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	0	2520	6	71	5	14	69817	30003	10	10	0	10000	30010	70036	70052	70052	70055	70036
40024	70051	525	0	0	0	0	0	0	0	0	1	0	0	70039	69743	59695	25	40014	30013	10001	30010	10000	616991	3342398	0	0	49	66974	70051	70035	64669	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	2	0	12	10000	1	1	1	1	1	0	2520	14	71	14	5	69820	30006	10	10	0	10000	30010	70058	70042	70042	70058	70058
40024	70041	525	1	1	1	1	0	0	0	2	1	0	1	70026	69781	59716	25	40018	30016	10002	30010	10000	616995	3341769	0	0	49	66974	70054	70051	64672	3	64960	40010	30020	10000	60020	20000	70037	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	0	10000	0	0	0	0	0	0	2520	14	17	14	5	69814	30003	10	10	10	10000	30010	70052	70052	70052	70036	70052
40024	70051	524	0	0	0	0	0	0	0	2	1	0	0	70042	69784	59719	25	40018	30013	10002	30010	10000	617045	3341769	0	0	49	66955	70051	70051	64653	3	64979	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	0	2520	14	71	14	14	69803	30003	10	0	0	10000	30010	70055	70052	70052	70055	70052
40024	70051	524	0	0	0	0	0	0	0	1	1	0	1	70026	69781	59719	25	40014	30013	10002	30010	10000	617045	3342542	0	1	49	66977	70057	70057	64675	3	64982	40010	30020	10000	60020	20000	70057	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10002	2	1	10003	0	0	1	1	10000	1	0	1	0	0	0	2520	14	71	6	14	69814	30003	10	13	0	10000	30010	70052	70052	70052	70052	70052
40024	70051	524	0	0	0	0	0	0	0	1	1	0	0	70020	69743	59695	25	40014	30010	10001	30010	10000	616991	3342254	0	1	49	66974	70054	70051	64653	3	64979	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	0	10000	0	0	1	0	0	0	2520	14	71	14	14	69798	30003	10	10	10	10000	30010	70036	70055	70052	70055	70036

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrh w0, [x6, x7, lsl #1]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0057

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70057	525	1	1	1	0	0	0	0	2	0	1	0	1	70042	69788	59716	25	40104	30106	10002	30100	10000	616078	3342542	1	49	66977	70057	70057	64653	3	64944	40100	30200	10000	60200	20000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10003	1	1	10002	0	1	1	10000	1	1	1	1	0	2610	1	71	1	1	69804	30006	10	10	0	10000	30100	70042	70042	70058	70058	70058
40204	70057	525	1	0	1	0	0	0	0	2	0	1	0	1	70026	69702	59701	25	40104	30103	10002	30100	10000	616068	3341769	0	49	66961	70041	70041	64653	3	64944	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	1	10002	0	0	1	10000	1	1	1	1	1	2610	1	71	1	1	69804	30006	0	10	0	10000	30100	70058	70058	70042	70059	70042
40204	70041	525	1	1	0	0	0	0	0	2	0	1	0	1	70026	69788	59716	25	40108	30106	10002	30100	10000	616068	3342542	1	49	66962	70065	70058	64637	3	64960	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10001	0	1	1	10000	1	1	1	1	0	2610	1	71	1	1	69820	30006	10	0	10	10000	30100	70058	70042	70058	70058	70058
40204	70041	525	1	1	1	0	0	0	0	2	0	1	0	1	70042	69702	59701	25	40104	30103	10001	30100	10000	616068	3342542	1	49	66977	70083	70051	64637	3	64960	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10001	0	1	1	10000	0	1	1	1	1	2610	1	71	1	1	69820	30006	10	0	0	10000	30100	70058	70058	70058	70042	70042
40204	70041	524	1	1	1	0	0	0	0	2	0	1	0	0	70042	69788	59716	25	40108	30106	10001	30100	10000	616068	3341769	1	49	66977	70057	70057	64653	3	64944	40100	30200	10000	60200	20000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10002	0	1	1	10000	1	1	1	1	0	2610	1	71	1	1	69820	30006	10	10	10	10000	30100	70058	70058	70058	70058	70042
40204	70057	525	1	0	0	0	0	0	0	1	0	1	0	1	70042	69788	59716	25	40108	30106	10002	30100	10000	616068	3341769	1	49	66961	70041	70041	64637	3	64960	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10001	1	0	10001	0	1	1	10000	0	1	0	1	1	2610	1	71	1	1	69820	30006	10	10	10	10000	30100	70061	70042	70058	70058	70042
40204	70041	525	1	0	0	0	0	0	0	2	0	1	0	0	70042	69702	59701	25	40104	30103	10002	30100	10000	616068	3342542	0	49	66977	70041	70057	64653	3	64963	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	1	10001	0	2	1	10000	1	1	1	1	1	2610	1	71	1	1	69804	30006	10	10	10	10000	30100	70058	70042	70058	70058	70058
40204	70041	525	1	0	0	0	0	0	0	1	0	0	0	1	70042	69788	59701	25	40108	30106	10001	30100	10000	616068	3342542	0	49	66977	70057	70041	64637	3	64944	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10002	0	1	1	10000	0	1	1	1	0	2610	1	71	1	1	69820	30003	0	10	0	10000	30100	70058	70058	70042	70058	70058
40204	70041	524	1	1	0	0	0	0	0	1	0	0	0	1	70042	69788	59701	25	40108	30106	10001	30100	10000	616078	3342542	0	49	66980	70041	70057	64637	3	64960	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10002	2	1	10002	0	0	1	10000	0	1	0	1	1	2610	1	71	1	1	69804	30006	10	10	0	10000	30100	70058	70042	70058	70042	70058
40204	70057	524	1	1	0	0	0	0	0	2	0	0	1	1	70026	69788	59716	25	40104	30106	10001	30100	10000	616078	3342542	1	49	66977	70041	70060	64653	3	64960	40100	30200	10000	60200	20000	70041	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10002	2	0	10002	0	1	1	10000	1	1	1	1	2	2610	1	71	1	1	69820	30003	10	0	0	10000	30100	70042	70042	70058	70042	70058

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	0e	0f	19	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	cf	d0	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	525	1	0	0	0	0	1	1	0	70035	69728	59709	25	40010	30010	10001	30010	10000	616952	3342062	1	49	66967	70035	70047	64665	3	64972	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	1	2520	0	7	71	0	14	5	69813	30003	9	0	6	10000	30010	70036	70036	70051	70051	70048
40024	70035	525	0	0	0	0	0	1	1	0	70032	69760	59709	25	40014	30013	10000	30010	10000	617068	3342206	0	49	66970	70035	70035	64665	3	64960	40010	30020	10000	60020	20000	70116	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	3	10003	0	0	2520	0	14	71	0	10	6	69813	30000	6	6	0	10000	30010	70036	70036	70048	70051	70048
40024	70050	524	0	0	0	0	0	1	0	0	70020	69760	59709	25	40014	30013	10001	30010	10051	616982	3342206	1	49	66955	70050	70050	64653	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	1	2520	0	14	71	0	14	14	69813	30003	9	6	9	10000	30010	70036	70036	70051	70051	70036
40024	70035	524	0	0	0	1	0	1	0	0	70035	69760	59695	25	40014	30013	10001	30010	10000	617068	3342206	1	49	66970	70035	70050	64668	3	64972	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	1	2520	0	14	71	0	14	6	69813	30003	6	0	9	10000	30010	70085	70051	70036	70048	70051
40024	70050	524	0	0	1	1	0	1	1	0	70032	69760	59709	25	40014	30013	10001	30010	10000	616982	3342206	0	49	66955	70050	70050	64653	3	64975	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	0	2520	3	14	71	0	15	14	69813	30003	9	6	9	10000	30010	70048	70051	70048	70048	70048
40024	70035	524	0	0	1	0	0	0	0	0	70032	69760	59709	25	40010	30013	10000	30010	10000	616982	3342206	0	49	66970	70050	70050	64668	3	64960	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	6	0	10000	1	1	2520	0	14	71	0	14	5	69798	30000	0	0	0	10000	30010	70051	70048	70051	70051	70051
40024	70050	525	0	0	0	0	0	0	1	0	70020	69743	59695	25	40014	30010	10001	30010	10000	616952	3341470	1	49	66970	70035	70050	64668	3	64960	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	10000	1	1	2520	0	14	71	0	5	14	69798	30003	9	6	9	10000	30010	70051	70051	70051	70048	70051
40024	70050	524	1	0	0	0	0	0	0	0	70037	69760	59695	25	40014	30010	10001	30010	10000	616952	3342206	1	49	66970	70050	70035	64668	3	64972	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	0	1	2520	0	13	71	0	6	14	69798	30003	9	0	9	10000	30010	70051	70048	70051	70051	70036
40024	70035	524	0	0	0	0	0	1	0	0	70020	69760	59709	25	40014	30010	10000	30010	10000	616982	3342206	1	49	66955	70050	70050	64653	3	64975	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	10000	1	0	2520	0	4	71	0	14	14	69798	30003	9	0	0	10000	30010	70048	70051	70051	70051	70048
40024	70035	525	1	0	1	1	0	6	0	0	70020	69760	59709	25	40014	30010	10000	30010	10000	616982	3342206	1	49	66970	70050	70050	64665	3	64975	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	0	2520	0	5	71	0	6	13	69813	30003	9	6	9	10000	30010	70051	70051	70048	70056	70051

Test 4: throughput

Count: 8

Code:

  ldrh w0, [x6, x7, lsl #1]
  ldrh w0, [x6, x7, lsl #1]
  ldrh w0, [x6, x7, lsl #1]
  ldrh w0, [x6, x7, lsl #1]
  ldrh w0, [x6, x7, lsl #1]
  ldrh w0, [x6, x7, lsl #1]
  ldrh w0, [x6, x7, lsl #1]
  ldrh w0, [x6, x7, lsl #1]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26727	200	0	1	0	0	0	0	1	0	0	0	26722	2	12	1	16	25	80100	100	80000	100	80015	500	1168380	0	49	23627	26735	26731	16659	6	16922	80115	200	80024	200	160048	26731	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	0	0	41	80000	6	1	39	44	0	1	1	1	5118	1	16	0	0	26724	0	10	7	80000	100	26708	26733	26732	26732	26708
80204	26728	200	0	0	0	0	0	0	1	0	0	0	26702	0	1	1	19	25	80100	100	80000	100	80015	500	1167198	0	49	23651	26727	26731	16659	6	16683	80115	200	80024	200	160048	26727	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	0	0	0	80000	6	0	39	44	0	1	1	1	5118	0	16	0	1	26731	10	10	4	80000	100	26732	26732	26708	26732	26708
80204	26731	200	0	0	0	0	0	44	1	0	0	1	26722	0	1	0	18	25	80100	100	80000	100	80015	500	1166596	0	49	23651	26731	26731	16659	6	16659	80116	200	80024	200	160048	26731	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	80039	1	2	0	80000	0	1	39	44	0	1	1	1	5118	0	16	0	0	26704	10	10	4	80000	100	26728	26728	26736	26732	26739
80204	26731	200	0	0	0	0	0	44	1	0	0	1	26719	2	1	12	19	25	80100	100	80000	100	80015	500	1167198	1	49	23627	26731	26731	16659	6	16659	80115	200	80024	200	160048	26731	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80000	0	0	38	80038	6	0	0	43	0	1	1	1	5118	0	16	0	0	26751	0	14	7	80000	100	26732	26708	26728	26724	26732
80204	26707	200	0	0	0	0	0	86	1	0	0	1	26692	2	0	0	0	25	80100	100	80000	100	80015	500	1168380	0	49	23627	26707	26736	16635	6	16683	80113	200	80024	200	160048	26727	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	44	80038	0	0	38	80000	6	1	38	0	0	1	1	1	5118	0	16	0	0	26724	14	0	7	80000	100	26732	26728	26708	26732	26732
80204	26727	200	0	0	0	0	0	0	1	0	0	1	26714	2	0	0	16	25	80100	100	80000	100	80014	500	1168380	0	49	23651	26731	26731	16659	6	16683	80115	200	80024	200	160048	26731	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	0	0	38	80000	6	1	38	0	0	1	1	1	5118	0	16	0	0	26724	10	10	7	80000	100	26732	26708	26732	26732	26728
80204	26727	201	0	0	0	0	0	0	1	0	0	0	26716	0	1	1	19	25	80100	100	80000	100	80015	500	1166596	1	49	23651	26731	26707	16635	6	16683	80115	200	80024	200	160048	26731	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	0	0	38	80038	6	0	39	44	0	1	1	1	5118	0	16	0	0	26704	0	10	4	80000	100	26728	26708	26728	26708	26732
80204	26731	201	0	0	1	0	0	44	1	0	0	1	26772	2	1	12	0	25	80100	100	80000	100	80015	500	1166596	1	49	23651	26707	26731	16659	6	16679	80115	200	80024	200	160048	26731	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80038	1	0	0	80038	6	0	38	44	0	1	1	1	5118	0	16	0	0	26727	14	10	7	80000	100	26708	26728	26732	26732	26728
80204	26707	200	0	0	0	0	0	45	0	0	0	0	26714	2	1	12	0	25	80100	100	80000	100	80013	500	1167198	0	49	23627	26727	26707	16659	6	16679	80115	200	80024	200	160048	26707	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	80038	0	0	39	80038	6	1	38	43	0	1	1	1	5118	0	16	0	0	26704	0	14	7	80000	100	26732	26732	26732	26732	26732
80204	26731	200	0	0	0	0	0	12	0	0	0	1	26716	2	0	1	19	25	80100	100	80000	100	80015	500	1166596	0	49	23651	26731	26731	16659	6	16683	80115	200	80024	200	160048	26707	81	1	1	80201	100	99	100	80000	100	80000	1	100	80000	43	80038	0	0	0	80038	6	0	38	44	0	1	1	1	5118	0	16	0	0	26732	10	10	7	80000	100	26738	26732	26708	26708	26728

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26723	200	0	0	0	0	1	1	0	0	45	0	0	0	0	26693	2	18	12	11	25	80010	10	80000	10	80000	50	1167660	1	49	23652	0	26732	26715	16677	3	16713	80010	20	80000	20	160000	26732	64	1	1	80021	10	9	10	80000	10	80000	1	10	80020	20	42	0	80057	0	28	0	0	80039	6	1	35	0	0	0	0	5020	7	16	10	8	26724	6	0	2	80000	10	26709	26723	26723	26723	26811
80024	26722	200	0	0	0	0	0	0	0	0	45	0	0	0	1	26693	0	18	12	16	25	80010	10	80000	10	80000	50	1173354	1	49	23652	0	26714	26732	16678	3	16695	80010	20	80000	20	160000	26714	81	1	1	80021	10	9	10	80000	10	80000	0	10	80020	20	0	0	80054	0	0	0	156	80000	6	1	0	0	0	0	0	5020	7	16	8	9	26719	0	6	0	80000	10	26723	26709	26729	26728	26815
80024	26727	200	0	0	0	0	0	0	0	0	47	0	0	0	0	26707	2	12	12	16	25	80010	10	80000	10	80000	50	1173036	1	49	23635	0	26714	26732	16677	3	16712	80010	20	80000	20	160000	26732	65	1	1	80021	10	9	10	80000	10	80000	0	10	80020	19	42	0	80058	0	33	0	38	80000	6	1	0	43	0	0	0	5020	7	16	8	6	26869	6	0	4	80000	10	26723	26729	26729	26729	26840
80024	26734	200	1	1	0	0	0	0	0	0	21	0	1	0	3	26717	0	18	18	16	25	80010	10	80000	10	80000	50	1167605	0	49	23628	0	26727	26708	16667	3	16708	80010	20	80000	20	160000	26728	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	0	80056	0	0	0	177	80000	6	1	39	43	0	0	0	5020	6	16	8	8	26724	0	0	4	80000	10	26709	26728	26729	26709	26709
80024	26763	200	0	0	0	0	0	0	0	0	45	0	0	0	0	26712	0	12	12	4	25	80010	10	80000	10	80000	50	1167605	0	49	23642	0	26722	26722	16652	3	16702	80010	20	80000	20	160000	26728	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80057	1	31	0	62	80037	6	1	19	42	19	0	0	5020	10	16	6	10	26730	0	9	0	80000	10	26733	26734	26734	26716	26813
80024	26731	200	0	0	0	0	0	0	0	0	45	0	0	0	0	26712	2	12	12	16	25	80010	10	80000	10	80000	50	1166464	0	49	23652	0	26732	26732	16677	3	16712	80010	20	80000	20	160000	26732	82	1	1	80021	10	9	10	80000	10	80000	0	10	80019	19	0	0	80057	0	25	0	3	80000	6	0	35	39	0	0	0	5020	8	16	10	7	26724	0	6	2	80000	10	26728	26709	26723	26723	26847
80024	26740	200	1	1	1	0	0	0	0	0	65	0	1	0	0	26699	2	18	18	1	25	80010	10	80000	10	80000	50	1166776	1	49	23647	0	26731	26719	16652	3	16705	80188	20	80000	20	160000	26728	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	0	80057	0	0	0	186	80039	6	0	39	43	0	0	0	5020	6	16	6	8	26705	10	10	4	80000	10	26729	26709	26729	26723	26828
80024	26715	200	1	1	1	0	0	0	0	0	65	0	0	0	3	26717	3	0	18	16	25	80010	10	80000	10	80000	50	1166993	1	49	23648	0	26728	26722	16667	3	16707	80010	20	80000	20	160000	26728	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	0	80057	0	11	0	44	80039	6	1	0	43	0	0	0	5020	9	16	7	8	26705	6	6	0	80000	10	26728	26732	26732	26709	26733
80024	26908	201	1	0	1	0	0	0	0	0	30	0	0	0	2	26717	1	0	0	15	25	80270	10	80000	10	80178	50	1174474	0	49	23648	0	26708	26727	16672	3	16708	80010	20	80000	20	160000	26727	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	0	80057	0	1	0	144	80035	6	1	39	39	0	0	0	5020	9	16	9	9	26719	0	6	0	80000	10	26709	26876	26723	26727	26907
80024	26791	200	1	1	1	1	1	1	0	2	65	88	0	0	1	26717	2	18	18	16	25	80010	10	80000	10	80000	50	1167132	0	49	23642	0	26729	26710	16667	3	16688	80010	20	80000	20	160000	26722	71	1	1	80021	10	9	10	80000	10	80000	1	10	80000	0	0	0	80057	1	23	2	21	80038	6	1	19	42	19	1	0	5020	7	16	6	9	26729	9	0	2	80000	10	26733	26733	26733	26733	26891

LDRH (register, lsl)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations