Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMN (register, asr, 32-bit)

Test 1: uops

Code:

  cmn w0, w1, asr #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)f5f6f7f8fd
100470950611000304252000200010004087707097094982135611000100020007097811100110000073122116842000710710710710710
100470950611000304252000200010004087707097094982135611000100020007097811100110000073122116842000710710710710710
100470950611000304252000200010004087707097094982535611000100020007097811100110000073122116842000710710710710710
100470960821000304252000200010004087707097094982535611000100020007097811100110000073122116842000710710710710710
100470950611000304252000200010004087707097094982135611000100020007097811100110000073122116842000710710710710710
100470950611000304252000200010004087717097094982135611000100020007097811100110000073122116842000710710710710710
100470950611000304252000200010004087717097094982535611000100020007097811100110000073122116842000710710710710710
100470950611000304252000200010004087717097094982135611000100020007097811100110000073122116842000710710710710710
100470950611000304252000200010004087717097094982535611000100020007097811100110000073122116842000710710710710710
100470950611000304252000200010004087717097094982535611000100020007097811100110000073122116842000710710710710710

Test 2: Latency 3->1

Chain cycles: 1

Code:

  cmn w0, w1, asr #17
  cset x0, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2020430035225000061100002989325301003010020100195619814926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
2020430035225000061100002989325301003010020100195619804926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
2020430035225000061100002989325301003010020100195619804926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
2020430035225000061100002989325301003010020100195619814926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
20204300352250000191100002989325301003010020100195619804927001300353003527369327478201002020030467300811453120201100991002010010100420013441241342995430000101003003630036300363003630036
2020430035225000061100002989325301003010020100195619804926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
2020430035225000061100002989325301003010020100195619814926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
2020430035225000061100002989325301003010020100195619804926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
2020430035225000061100002989325301003010020100195619814926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
2020430035225000061100002989325301003010020100195619814926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
200243003522542611000029891253001030010200101956289149269553003530035273913274982001020020300203003514511200211091020010100101270233112995830000100103003630036300363003630036
200243003522424611000029891253001030010200101956289149269553003530035273913274982001020020300203003514511200211091020010100101270133112995830000100103003630036300363003630036
200243003522415611000029891253001030010200101956289149269553003530035273913274982001020020300203003514511200211091020010100101270133122995830000100103003630036300363003630036
200243003522515611000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100101270133112995830000100103003630036300363003630036
200243003522536611000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100101270133112995830000100103003630036300363003630036
200243003522548611000029891253001030010200101956289149269553003530035273913274982001020020300203003514511200211091020010100101270133112995830000100103003630036300363003630036
200243003522521611000029891253001030010200101956289149269553003530035273913274982001020020300203003514511200211091020010100101270133112995830000100103003630036300363003630036
200243003522401391000029891253001030010200101956289149269553003530035273913274982001020020300203003514511200211091020010100101270233112995830000100103003630036300363003630036
200243003522527611000029891253001030010200101956289149269553003530035273913274982001020020300203003514511200211091020010100101270133112995830000100103003630036300363003630036
20024300352253611000029891253001030010200101956289149269553003530035273913274982001020020300203003514511200211091020010100101270133112995830000100103003630036300363003630036

Test 3: Latency 3->2

Chain cycles: 1

Code:

  cmn w0, w1, asr #17
  cset x1, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2020430035225000001200107100002989925301003010020107195624004926999300353003527391627487201072022430236300351451120201100991002010010100000403011113180116212998130000101003003630036300363003630036
20204300352250000000010510000298992530100301002010719562401492695530035300352739162748720107202243023630035145112020110099100201001010000036100011113180116123001530000101003003630036300363008230036
202043003522500000000124100002990625301003010020107195624014927001300353003527391627487201072022430236300351451120201100991002010010100000000011113180116112998130000101003003630036300363003630036
202043003522500000000124100002989925301003010020107195624004926955300353003527391627487201072022430236300351451120201100991002010010100000000011113180116112998130000101003007130036300363003630036
202043003522500000000800100002989925301003010020107195624014926955300353003527391627487201072022430236300351451120201100991002010010100000000011113180116112998130108101003003630036300363003630036
2020430035225000000001002100062989925301003010020107195624014926955300353003527391627487201072022430236300351451120201100991002010010100000000011113180116112998130000101003003630036300363003630036
202043003522500000000170100002989925301003010020107195624004926955300353003527391627487201072022430236300351451120201100991002010010100000000011113180116112998130000101003003630036300363003630036
20204300352250000000061100002989925301003010020107195624019826955300353003527391627487201072022430236300351451120201100991002010010100000000011113180116112998130000101003003630036300363003630036
20204300352250000000061100002989925301003010020107195624014926955300353003527391627487201072022430236300351451120201100991002010010100000000011113180116112998130000101003003630036300363003630036
202043003522500000000105100002989925301003010020107195624014926955300353003527391627487201072022430236300351451120201100991002010010100000000011113180116212998130000101003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9facc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20024300352250611000029891253001030010200101956289149269553003530035273913274982001020020300203003514511200211091020010100100001270633552995830000100103003630036300363003630036
20024300352250611000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100001270533562995830000100103003630036300363003630036
20024300352250611000029891253001030010200101956289149269553003530035273913274982001020020300203003514511200211091020010100100001270633652995830000100103003630036300363003630036
20024300352250611000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100001270533562995830000100103003630036300363003630036
20024300352250611000029891253001030010200101956289149269553003530035273913274982001020020300203003514511200211091020010100100001270533762995830000100103003630036300363003630036
200243003522518611000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100001270633562995830000100103003630036300363003630036
20024300352250611000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100001270433772995830000100103003630036300363003630036
200243003522415611000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100001270533662995830000100103003630036300363003630036
20024300352240611000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100001270633562995830000100103003630036300363003630036
20024300352240611000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100001270533662995830000100103003630036300363003630036

Test 4: throughput

Count: 8

Code:

  cmn w0, w1, asr #17
  cmn w0, w1, asr #17
  cmn w0, w1, asr #17
  cmn w0, w1, asr #17
  cmn w0, w1, asr #17
  cmn w0, w1, asr #17
  cmn w0, w1, asr #17
  cmn w0, w1, asr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)branch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
802045345640000000618000048741251601001601008010034400050495033053410534104329820043433608010080200160200534107811802011009910080100100000511021711533921600001005341153411534115341153411
802045341040010000618000048741251601001601008010034400050495033053410534104329820603433608010080200160200534107811802011009910080100100000511012411533921600001005341153411534115341153411
802045341040000000618000048741251601001601008010034400050495033053410534104329820633433608010080200160200534107811802011009910080100100000511012411533921600001005341153411534115341153411
802045341040000000618000048741251601001601008010034400050495033053410534104329820503433608010080200160200534107811802011009910080100100000511012411533921600001005341153411534115341153411
802045341040000000618000048741251601001601008010034400050495033053410534104329820633433608010080200160200534107811802011009910080100100000511012411533921600001005341153411534115341153411
8020453410400000570618000048741251601001601008010034400050495033053410534104329820633433608010080200160200534107811802011009910080100100000511012411533921600001005341153411534115341153411
802045341039900000618000048741251601001601008010034400050495033053410534104329820503433608010080200160200534107811802011009910080100100000511012411533921600001005341153411534115341153411
802045341040000000618000048741251601001601008010034400050495033053410534104329820503433608010080200160200534107811802011009910080100100000511012411533921600001005341153411534115341153411
802045341040000000618000048741251601001601008010034400050495033053410534104329820503433608010080200160200534107811802011009910080100100000511012411533921600001005341153411534115341153411
8020453410400000004108000048741251601001601008010034400051495033053410534104329820633433608010080200160200534107811802011009910080100100000511012411533921600001005341153411534115341153411

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6673

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8002453401399000000061800004794625160010160010800103438130149503005338053380432902562343352800108002016002053380781180021109108001010000050207247753359160000105338153381533815338153381
80024533804000000000441800004794625160010160010800103438130149503005338053380432902562343352800108002016002053380781180021109108001010000050206246553359160000105338153381533815338153381
8002453380400000000061800004794625160010160010800103438130149503005338053380432902562343352800108002016002053380781180021109108001010000050206245753359160000105338153381533815338153381
8002453380400000000061800004794625160010160010800103438130149503005338053380432902562343352800108002016002053380781180021109108001010000050207245653359160000105338153381533815338153381
8002453380399000000061800004794625160010160010800103438130149503005338053380432902562343352800108002016002053380781180021109108001010000050207246553359160000105338153381533815338153381
80024533803990000000103800004794625160010160010800103438130149503005338053380432902562343352800108002016002053380781180021109108001010000050206245553359160000105338153381533815338153433
8002453380400000000061800004794625160010160010800103438130149503005338053380432902707343352800108002016002053380781180021109108001010000050206246753359160000105338153381533815338153381
8002453380400000000061800004794625160010160010800103438130149503005338053380432902707343352800108002016002053380781180021109108001010000050206245553359160000105338153381533815338153381
8002453380400000000061800004794625160010160010800103438130149503005338053380432902562343352800108002016002053380781180021109108001010000050207248853359160000105338153381533815338153381
8002453380400000000061800004794625160010160010800103438130149503005338053380432902707343352800108002016002053380781180021109108001010000050208247753359160000105338153381533815338153381