Firestorm: STRB measurements

Code:

  strb w0, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	22	3a	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	554	4	0	0	0	0	3	0	0	527	16	16	2	25	1000	1000	1000	22448	1	554	542	355	3	401	1000	1000	2000	543	543	1	1	1001	1000	1000	1000	0	42	1	0	1002	0	0	2	1002	2	42	0	0	73	1	16	1	1	539	1000	543	543	543	555	543
1004	542	4	0	0	0	0	3	1	0	527	16	16	1	25	1000	1000	1000	22448	1	542	542	355	3	401	1000	1000	2000	542	543	1	1	1001	1000	1000	1000	0	42	0	4	1016	1	0	18	1002	16	44	14	0	73	1	16	1	1	551	1000	555	555	555	555	543
1004	542	4	0	0	0	0	3	1	0	527	16	16	5	25	1000	1000	1000	22884	0	554	554	376	3	411	1000	1000	2000	563	554	1	1	1001	1000	1000	1015	15	44	0	0	1002	0	0	2	1002	2	42	0	0	73	1	16	1	1	540	1000	544	544	544	544	543
1004	542	4	0	0	0	9	7	0	0	527	16	16	3	25	1000	1000	1000	22448	0	542	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	42	0	0	1002	0	0	2	1002	2	42	0	0	73	1	16	1	1	539	1000	543	543	543	555	544
1004	542	4	0	0	0	0	3	1	0	527	16	16	2	25	1000	1000	1000	23028	0	554	554	376	3	411	1000	1000	2000	563	554	1	1	1001	1000	1000	1014	14	42	0	0	1002	0	0	2	1002	2	42	0	0	73	1	16	1	1	539	1000	543	565	564	555	555
1004	554	4	1	1	1	0	17	1	1	539	16	16	1	25	1000	1000	1000	22448	0	542	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	14	44	0	0	1016	0	1	16	1002	16	44	14	1	73	1	16	1	1	549	1000	555	552	543	543	543
1004	542	4	0	0	0	0	3	1	0	527	16	16	0	25	1000	1000	1000	22472	0	554	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	14	44	0	1	1016	0	0	18	1002	16	44	14	1	73	1	16	1	1	561	1000	554	554	555	553	553
1004	552	4	1	1	1	0	18	0	1	536	16	16	1	25	1000	1000	1000	22472	0	542	543	356	3	400	1000	1000	2000	554	542	1	1	1001	1000	1000	1014	0	42	0	0	1002	0	0	2	1002	2	42	0	0	73	1	16	1	1	539	1000	553	543	543	543	543
1004	542	4	0	0	0	3	3	0	0	527	16	16	1	25	1000	1000	1000	23004	0	554	563	367	3	421	1000	1000	2000	554	552	1	1	1001	1000	1000	1015	15	44	1	2	1016	0	0	19	1002	16	44	14	0	73	1	16	1	1	551	1000	555	544	544	544	544
1004	543	4	0	0	0	0	3	0	0	528	16	16	1	25	1000	1000	1000	22472	0	542	542	356	3	401	1000	1000	2000	542	542	1	1	1001	1000	1000	1014	0	42	1	0	1002	0	0	2	1002	2	42	0	0	73	1	16	1	1	540	1000	555	555	555	555	555

Count: 8

Code:

  strb w0, [x6]
  strb w0, [x6]
  strb w0, [x6]
  strb w0, [x6]
  strb w0, [x6]
  strb w0, [x6]
  strb w0, [x6]
  strb w0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	19	1e	1f	22	23	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40042	300	0	0	0	3	1	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839424	0	49	36962	40042	40051	29964	3	29998	80100	200	80000	200	160000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	8	80002	2	34	5110	2	16	2	2	40046	0	80000	100	40050	40043	40051	40043	40043
80204	40042	300	0	0	0	3	1	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839424	0	49	36970	40042	40042	29955	3	29998	80100	200	80000	200	160000	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	2	80002	2	34	5110	2	16	2	2	40048	0	80000	100	40043	40043	40052	40043	40043
80204	40042	300	0	0	0	3	1	0	40025	16	16	0	25	80100	100	80000	100	80000	500	1839424	0	49	36970	40040	40042	29955	3	30007	80100	200	80000	200	160000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	80002	0	8	80002	2	34	5110	2	16	2	2	40039	0	80000	100	40043	40043	40043	40052	40043
80204	40042	300	0	0	0	9	0	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839424	0	49	36960	40042	40040	29955	3	30007	80100	200	80000	200	160000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	2	80002	2	34	5110	2	16	2	3	40039	0	80000	100	40043	40052	40043	40052	40043
80204	40042	300	0	0	0	9	1	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839424	0	49	36962	40040	40042	29955	3	30008	80100	200	80000	200	160000	40040	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	5	80002	0	34	5110	2	16	2	2	40039	0	80000	100	40043	40043	40043	40043	40051
80204	40042	300	0	0	0	3	1	0	40034	16	16	0	25	80100	100	80000	100	80000	500	1839424	0	49	36962	40049	40049	29963	3	30000	80100	200	80000	200	160000	40040	32003	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	2	80000	2	34	5110	2	16	2	2	40047	0	80000	100	40043	40043	40043	40043	40043
80204	40042	299	0	0	0	3	1	0	40025	16	16	0	25	80100	100	80000	100	80000	500	1839424	0	49	36962	40042	40042	29955	3	30009	80100	200	80000	200	160000	40051	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	2	80002	2	34	5110	2	16	2	2	40039	0	80000	100	40043	40043	40043	40043	40051
80204	40042	300	0	0	0	9	1	0	40027	0	16	0	25	80100	100	80000	100	80000	500	1839808	0	49	36962	40042	40040	29955	3	30000	80100	200	80000	200	160000	40043	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	5	80002	2	34	5110	2	16	2	2	40039	0	80000	100	40043	40051	40043	40051	40043
80204	40049	300	0	0	0	6	1	0	40036	16	16	0	25	80100	100	80000	100	80000	500	1839424	0	49	36960	40042	40051	29955	3	30000	80100	200	80000	200	160000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	5	80002	2	34	5110	2	16	2	2	40037	0	80000	100	40043	40043	40043	40043	40051
80204	40042	300	0	0	0	9	1	0	40027	16	0	0	25	80100	100	80000	100	80000	500	1839424	0	49	36962	40042	40042	29955	3	29998	80100	200	80000	200	160000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	2	80002	2	34	5110	2	16	2	2	40048	0	80000	100	40043	40043	40043	40043	40043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40043	299	0	0	3	1	40027	16	16	1	25	80010	10	80000	10	80000	50	1839448	1	49	36962	40042	40042	29975	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	42	80002	0	2	80002	2	42	5020	18	16	4	17	7	40039	80000	10	40041	40043	40043	40043	40043
80024	40042	300	0	0	3	0	40027	16	16	1	25	80010	10	80000	10	80000	50	1839448	1	49	36962	40040	40042	29977	3	30022	80010	20	80000	20	160000	40202	40190	1	1	80021	10	9	10	80000	10	80000	10	80000	42	80000	1	0	80002	2	42	5020	15	16	8	8	17	40039	80000	10	40041	40043	40043	40043	40043
80024	40042	300	0	6	3	1	40028	16	16	1	25	80010	10	80000	10	80000	50	1839448	1	49	36962	40042	40042	29977	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	42	80000	1	2	80002	2	42	5020	6	16	6	8	17	40039	80000	10	40043	40041	40055	40043	40043
80024	40042	300	0	0	3	1	40027	0	0	0	25	80010	10	80000	10	80000	50	1839448	1	49	36962	40042	40042	29978	3	30022	80010	20	80000	20	160000	40040	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	42	80002	0	2	80002	2	42	5020	8	16	6	7	14	40041	80000	10	40044	40041	40041	40043	40043
80024	40042	299	0	138	3	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839448	1	49	36962	40042	40042	29975	3	30020	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	42	80000	0	2	80002	2	0	5020	6	16	0	8	17	40039	80000	10	40043	40044	40044	40043	40041
80024	40042	300	0	138	3	1	40025	16	16	6	25	80010	10	80000	10	80000	50	1839352	1	98	36963	40040	40040	29975	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	80002	0	2	80002	2	42	5020	6	16	0	17	8	40037	80000	10	40043	40041	40043	40043	40043
80024	40042	300	0	105	3	0	40027	16	16	1	25	80010	10	80000	10	80000	50	1839352	1	49	36962	40191	40042	29977	3	30023	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	42	80002	0	2	80002	2	42	5020	6	16	0	17	17	40040	80000	10	40041	40041	40043	40044	40041
80024	40042	300	0	135	3	1	40027	16	16	1	25	80010	10	80000	10	80000	50	1839448	1	49	36962	40054	40042	29977	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	42	80002	0	2	80002	0	42	5020	17	16	0	6	17	40039	80000	10	40043	40043	40041	40043	40044
80024	40042	300	0	264	3	1	40025	0	16	1	25	80010	10	80000	10	80000	50	1839448	1	49	36962	40040	40042	29977	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	42	80002	0	6	80002	2	42	5020	7	16	0	8	17	40037	80000	10	40043	40041	40044	40043	40041
80024	40043	299	0	195	3	1	40025	16	16	0	25	80010	10	80000	10	80000	50	1839448	1	49	36962	40054	40042	29977	3	30022	80010	20	80000	20	160000	40043	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	42	80000	0	0	80002	2	42	5020	16	16	0	17	17	40039	80000	10	40044	40043	40041	40044	40041

STRB

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations