Firestorm: SDIV (fast, 64-bit) measurements

Code:

  sdiv x0, x1, x2

Initialization

  mov x1, #0
  mov x2, #0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	2038	16	1	0	0	0	0	0	0	84	950	25	1000	1000	1000	53725	0	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	73	1	16	1	1	1981	1000	1000	2039	2039	2039	2039	2039
1004	2038	15	1	0	0	0	0	0	0	61	950	25	1000	1000	1000	53725	1	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	73	1	16	1	1	1981	1000	1000	2039	2039	2039	2039	2039
1004	2038	15	1	0	0	0	0	0	0	61	950	25	1000	1000	1000	53725	1	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	73	1	16	1	1	1981	1000	1000	2039	2039	2039	2039	2039
1004	2038	15	1	0	0	0	0	0	0	112	950	25	1000	1000	1000	53725	1	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	73	1	16	1	1	1981	1000	1000	2039	2039	2039	2039	2039
1004	2038	15	1	0	0	0	0	0	0	61	950	25	1000	1000	1000	53725	0	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	73	1	16	1	1	1981	1000	1000	2039	2039	2039	2039	2039
1004	2038	16	1	0	0	0	0	0	0	61	950	25	1000	1000	1000	53725	1	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	73	1	16	1	1	1981	1000	1000	2039	2039	2039	2039	2039
1004	2038	15	1	0	0	0	0	0	0	61	950	25	1000	1000	1000	53725	1	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	73	1	16	1	1	1981	1000	1000	2039	2039	2039	2039	2039
1004	2038	15	1	0	0	0	0	0	0	61	950	25	1000	1000	1000	53725	1	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	73	1	16	1	1	1981	1000	1000	2039	2039	2039	2039	2039
1004	2038	16	1	0	0	0	9	18	0	61	950	25	1000	1000	1000	53725	1	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	73	1	16	1	1	1981	1000	1000	2039	2039	2039	2039	2039
1004	2038	15	1	0	0	0	0	0	0	61	950	25	1000	1000	1000	53725	1	2038	2038	1801	3	1896	1000	1000	2000	2038	261	1	1	1001	1000	0	0	73	1	16	1	1	1981	1000	1000	2039	2039	2039	2039	2039

Test 2: Latency 1->2

Chain cycles: 2

Code:

  sdiv x0, x1, x2
  eor x1, x1, x0
  eor x1, x1, x0

Initialization

  mov x1, #0
  mov x2, #0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 7.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30204	90035	674	0	0	0	6	0	61	81120	25	30100	30100	30100	8522656	1	49	86955	0	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	3	16	2	2	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	0	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	0	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	30	0	0	1910	2	16	2	2	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	0	0	0	61	81120	25	30100	30109	30100	8522656	0	49	86955	0	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	1	0	1910	2	16	2	2	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	675	0	0	0	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	0	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	2	16	2	2	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	675	0	0	0	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	0	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	1	0	1910	4	16	2	2	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	0	0	0	726	81120	25	30100	30100	30100	8522656	0	98	86955	0	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	2	16	2	2	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	0	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	0	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	2	16	2	2	89751	30000	30100	90036	90036	90036	90036	90066
30204	90035	674	0	0	0	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	0	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	2	16	2	2	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	675	0	0	0	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	0	90035	90035	85900	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	2	16	2	2	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	675	0	0	0	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	0	90035	90035	85900	3	86243	30201	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	4	16	2	2	89751	30000	30100	90036	90036	90036	90036	90036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 7.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30024	90035	674	0	0	0	0	0	0	0	61	81210	25	30010	30010	30010	8522901	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	3	16	2	3	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	0	0	0	0	61	81210	25	30010	30010	30010	8522901	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	2	16	2	3	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	0	0	0	0	726	81210	25	30010	30010	30010	8522901	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	1	0	3	0	1890	4	16	2	2	89778	30000	30010	90036	90081	90036	90036	90079
30024	90035	675	0	0	1	0	0	0	0	61	81210	25	30010	30010	30010	8522901	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	3	16	3	2	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	0	2	0	352	61	81210	25	30010	30010	30010	8522901	49	86955	90035	90076	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	2	16	2	3	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	0	0	0	0	61	81210	25	30010	30010	30010	8522901	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	3	16	3	3	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	0	0	0	0	61	81643	25	30010	30010	30010	8522901	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	2	16	3	2	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	0	0	0	0	61	81210	25	30010	30010	30010	8522901	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	2	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	2	16	3	2	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	0	0	0	0	61	81210	25	30010	30010	30010	8522901	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	2	16	2	1	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	0	0	0	0	0	251	81210	25	30010	30010	30010	8522901	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	3	16	2	2	89751	30000	30010	90036	90036	90036	90036	90036

Test 3: Latency 1->3

Chain cycles: 2

Code:

  sdiv x0, x1, x2
  eor x2, x2, x0
  eor x2, x2, x0

Initialization

  mov x1, #0
  mov x2, #0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 7.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30204	90035	674	0	0	61	81120	25	30100	30100	30125	8522656	1	49	86955	90035	90035	85900	0	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	3	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	675	1	0	61	81252	25	30125	30125	30125	8522656	1	49	86955	90035	90035	85900	0	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	675	0	12	61	81120	42	30100	30100	30100	8522656	1	49	86955	90035	90035	85900	0	3	86240	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	675	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	90035	90035	85900	0	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	61	81120	25	30100	30100	30100	8522656	1	49	86955	90035	90035	85900	0	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	61	81120	25	30100	30100	30100	8522656	1	49	86955	90035	90035	85900	0	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	675	0	0	61	81120	25	30100	30100	30100	8522656	1	49	86955	90035	90035	85900	0	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	61	81120	25	30100	30100	30100	8522656	0	49	86955	90035	90035	85900	0	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	1	16	1	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	674	0	0	61	81120	25	30100	30100	30100	8522656	1	49	86955	90035	90035	85900	0	3	86243	30100	30200	60200	90035	176	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	1	16	0	1	89751	30000	30100	90036	90036	90036	90036	90036
30204	90035	675	0	0	61	81120	25	30100	30100	30100	8522656	1	49	86955	90035	90035	85900	0	3	86243	30100	30200	60200	90035	194	1	1	30201	100	99	100	30100	100	0	0	0	0	1910	1	16	1	1	89808	30000	30100	90036	90036	90036	90036	90036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 7.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30024	90035	674	0	0	61	81210	25	30010	30010	30010	8522901	1	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	1890	3	16	2	2	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	61	81210	25	30010	30010	30010	8522901	1	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	1890	2	16	2	3	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	675	0	0	61	81210	25	30010	30010	30010	8522901	1	49	86955	90035	90035	85922	3	86275	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	1890	3	16	2	2	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	726	81210	25	30010	30010	30010	8522901	0	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90076	176	1	1	30021	10	9	10	30010	10	0	0	0	1890	2	16	2	2	89785	30000	30010	90036	90077	90036	90036	90036
30024	90035	674	0	0	61	81210	25	30010	30010	30010	8522901	1	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	1890	2	16	2	2	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	675	0	0	61	81210	25	30010	30010	30010	8522901	1	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	1890	3	16	2	2	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	61	81210	31	30010	30010	30010	8522901	1	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	1890	2	16	2	2	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	61	81210	25	30010	30010	30010	8522901	1	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	1	0	1890	2	16	2	2	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	674	0	0	61	81210	25	30010	30010	30010	8522901	1	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	3	1890	2	16	3	2	89751	30000	30010	90036	90036	90036	90036	90036
30024	90035	675	0	0	61	81210	25	30010	30010	30010	8522901	1	49	86955	90035	90035	85922	3	86265	30010	30020	60020	90035	176	1	1	30021	10	9	10	30010	10	0	0	0	1890	2	16	2	2	89751	30000	30010	90036	90036	90036	90036	90036

Test 4: throughput

Count: 8

Code:

  sdiv x0, x8, x9
  sdiv x1, x8, x9
  sdiv x2, x8, x9
  sdiv x3, x8, x9
  sdiv x4, x8, x9
  sdiv x5, x8, x9
  sdiv x6, x8, x9
  sdiv x7, x8, x9

Initialization

  mov x8, #0
  mov x9, #0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	160038	1198	0	0	0	0	0	61	79950	25	80100	80136	80100	4399225	1	49	156958	0	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	3	16	1	1	159980	80000	80100	160039	160039	160039	160039	160039
80204	160038	1199	0	0	0	0	0	61	79950	25	80100	80100	80100	4399225	1	49	156958	0	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160039	160039	160039	160039	160039
80204	160038	1199	0	0	0	0	0	61	79950	25	80100	80100	80100	4399225	1	49	156958	0	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160039	160039	160039	160039	160039
80204	160038	1199	0	0	0	0	0	61	79950	25	80100	80100	80100	4399225	0	49	156958	0	160038	160038	149940	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160039	160039	160039	160039	160039
80204	160038	1198	0	0	0	0	0	1568	79950	25	80100	80100	80100	4399225	1	49	156958	0	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160039	160039	160039	160039	160039
80204	160038	1199	0	0	0	0	0	6322	79950	25	80100	80100	80100	4399225	1	49	156958	0	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	2	0	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160039	160039	160039	160039	160039
80204	160038	1198	0	0	0	0	0	61	79950	25	80100	80100	80100	4399225	0	49	156958	0	160038	160076	149901	3	149996	80138	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	0	3	0	0	5110	1	16	1	1	159980	80000	80100	160039	160039	160039	160039	160039
80204	160078	1198	0	0	0	0	0	61	79950	25	80100	80100	80100	4399225	0	49	156958	0	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160039	160039	160039	160039	160039
80204	160038	1199	0	0	0	21	0	61	79950	25	80100	80100	80100	4399225	0	49	156958	0	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160077	160039	160039	160039	160039
80204	160038	1199	0	0	0	0	0	61	79950	25	80100	80100	80100	4399225	1	49	156958	3	160038	160038	149901	3	149996	80100	80200	160200	160038	261	1	1	80201	100	99	100	80100	100	0	0	1	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160039	160039	160039	160039	160039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? int retires (ef)	f5	f6	f7	f8	fd
80024	160038	1198	0	0	0	0	0	0	99	0	4828	79950	25	80010	80010	80010	4398775	1	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	15	16	15	18	159980	80000	0	0	80010	160039	160039	160039	160039	160039
80024	160038	1198	0	0	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	0	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	15	16	18	15	159980	80000	0	0	80010	160039	160039	160039	160039	160039
80024	160038	1198	0	0	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	0	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	18	16	15	18	159980	80000	0	0	80010	160039	160039	160039	160039	160039
80024	160038	1199	0	0	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	0	49	153927	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80022	10	9	10	80010	10	0	0	0	0	0	0	5020	15	16	17	15	159980	80000	0	0	80010	160039	160039	160039	160039	160039
80024	160038	1198	0	0	0	0	0	0	0	0	726	79950	25	80010	80010	80010	4398775	0	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	3	0	0	0	5020	18	16	16	20	159980	80000	0	0	80010	160039	160039	160039	160039	160039
80024	160038	1199	0	0	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	0	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	24	16	17	19	159980	80000	0	0	80010	160039	160039	160039	160039	160039
80024	160038	1198	0	0	0	0	0	0	0	0	726	79950	25	80010	80010	80010	4398775	0	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	14	16	15	19	159980	80000	0	0	80010	160039	160039	160039	160039	160039
80024	160079	1199	0	0	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	0	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	17	16	18	18	159980	80000	0	0	80010	160039	160039	160039	160039	160039
80024	160038	1199	0	0	0	0	0	0	9	0	61	79950	25	80010	80010	80010	4398775	0	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	1	5020	15	16	18	15	159980	80000	0	0	80010	160039	160039	160039	160039	160039
80024	160038	1198	0	0	0	0	0	0	0	0	61	79950	25	80010	80010	80010	4398775	0	49	156958	0	160038	160038	149923	3	150018	80010	80020	160020	160038	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	17	16	17	17	159980	80000	0	0	80010	160039	160039	160039	160039	160039

SDIV (fast, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations