Firestorm: UMADDL measurements

Code:

  umaddl x0, w0, w1, x2

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	3033	22	0	0	61	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	73	2	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	0	105	1922	25	1000	1000	1000	81440	1	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	0	1164	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	22	0	0	84	1922	25	1000	1000	1000	81440	1	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	0	103	1922	25	1000	1000	1000	81440	1	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	22	0	0	61	1922	25	1000	1000	1000	81440	1	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	0	441	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	0	147	1922	25	1000	1000	1000	81440	1	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	147	61	1922	25	1000	1000	1000	81440	1	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	0	61	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034

Test 2: Latency 1->2

Code:

  umaddl x0, w0, w1, x2

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30033	225	0	0	0	0	0	61	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	224	0	0	0	0	0	61	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	2	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	0	0	61	19906	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	0	0	61	19922	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	0	0	61	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	224	0	0	0	0	0	61	19922	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	0	0	61	19922	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	0	0	61	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	224	0	0	0	0	0	61	19922	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	0	0	61	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30033	225	0	0	0	0	0	0	0	61	19922	25	10010	10010	10010	828490	1	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	78	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	0	0	0	61	19922	25	10010	10010	10010	828490	1	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	84	0	0	640	2	16	2	3	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	0	0	0	61	19922	25	10010	10010	10010	828490	1	49	26953	30033	30033	28632	3	28763	10012	10020	30020	30033	401	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	102	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	224	0	0	0	0	0	0	0	61	19922	25	10010	10010	10010	828490	1	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	90	0	0	640	2	16	4	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	0	0	0	61	19922	25	10010	10012	10010	828490	1	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	96	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	0	0	0	61	19922	25	10010	10010	10010	828490	1	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	0	0	0	61	19922	25	10010	10010	10010	828490	1	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	87	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	0	0	0	103	19922	25	10010	10010	10010	828490	1	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	87	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	1	0	0	0	0	0	61	19922	25	10010	10010	10010	828490	1	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	90	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	0	0	0	61	19922	25	10010	10010	10010	828490	1	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	81	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034

Test 3: Latency 1->3

Code:

  umaddl x0, w1, w0, x2

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30068	225	0	0	24	145	19922	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	710	2	16	2	2	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	61	19922	25	10100	10100	10135	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	710	2	16	2	2	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	61	19922	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	710	2	16	2	2	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	132	19922	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	710	2	16	2	2	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	1114	19922	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	748	1	1	10201	100	99	100	10100	100	0	0	0	0	710	2	16	2	2	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	61	19922	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	2	0	0	710	2	16	2	2	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	61	19922	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	710	2	16	2	2	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	61	19922	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10207	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	710	2	16	2	2	29939	10000	10100	30034	30034	30034	30034	30034
10205	30033	225	0	0	0	61	19922	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	710	2	16	2	2	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	83	19922	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	710	2	16	2	2	29939	10000	10100	30034	30034	30034	30034	30034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	09	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30033	224	0	0	0	0	61	19922	25	10010	10010	10010	828490	0	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	3	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	89	19922	25	10010	10010	10010	828490	0	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	6	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	61	19922	25	10010	10010	10010	828490	0	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	9	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	61	19922	25	10010	10010	10010	828490	0	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	72	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	61	19922	25	10010	10010	10010	828490	0	49	26996	30077	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	9	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	61	19922	25	10010	10010	10010	828490	0	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	93	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	61	19922	25	10010	10010	10010	828490	0	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	99	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	61	19922	25	10010	10010	10010	828490	0	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	78	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	61	19922	25	10010	10010	10010	828490	0	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	96	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	61	19922	25	10010	10010	10010	828490	0	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	90	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034

Test 4: Latency 1->4

Code:

  umaddl x0, w1, w2, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10037	75	0	48	25	10100	10100	10100	70498	1	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	76	0	48	25	10100	10100	10100	70498	1	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	0	48	25	10100	10100	10100	70498	1	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	0	48	25	10100	10100	10100	70498	0	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	0	48	25	10100	10100	10100	70498	0	49	6957	10085	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	76	0	48	25	10100	10100	10100	70498	0	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	0	48	25	10100	10100	10100	70498	1	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	426	48	25	10100	10100	10100	70498	1	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	6	48	25	10100	10100	10100	70498	0	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	0	48	25	10100	10100	10100	70498	0	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10037	76	0	0	0	48	25	10010	10010	10010	70048	0	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	3	1	10021	10	9	10	10010	10	0	0	640	5	16	3	3	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	9	48	25	10010	10010	10010	70048	1	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	640	3	16	3	3	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	76	0	0	12	219	46	10033	10010	10010	70048	0	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	640	3	16	3	3	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	0	48	25	10010	10010	10010	70048	1	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	640	3	16	3	3	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	0	48	25	10010	10010	10010	70048	1	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	640	3	16	3	3	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	0	48	25	10010	10010	10010	70048	0	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	640	3	16	3	3	10033	10000	10010	10038	10085	10038	10038	10038
10024	10037	75	0	0	0	48	25	10010	10010	10010	70048	0	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	640	3	16	3	3	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	12	48	25	10010	10010	10010	70048	1	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	1	0	640	3	16	3	3	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	0	48	25	10010	10010	10010	70048	1	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	640	3	16	3	3	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	0	48	25	10010	10010	10010	70048	1	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	640	3	16	3	3	10033	10000	10010	10038	10038	10038	10038	10038

Test 5: throughput

Count: 8

Code:

  umaddl x0, w8, w9, x9
  umaddl x1, w8, w9, x9
  umaddl x2, w8, w9, x9
  umaddl x3, w8, w9, x9
  umaddl x4, w8, w9, x9
  umaddl x5, w8, w9, x9
  umaddl x6, w8, w9, x9
  umaddl x7, w8, w9, x9

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80035	600	0	0	0	0	0	0	46	25	80100	80100	80100	400500	1	49	76955	0	80035	80035	69964	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	25	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	0	0	0	0	46	25	80100	80100	80124	400500	1	49	76955	0	80035	80035	69964	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	0	0	0	0	1652	25	80100	80100	80100	400500	1	49	76955	0	80035	80035	69964	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80066	600	0	0	0	0	0	0	711	25	80100	80100	80100	400500	1	49	76955	0	80035	80035	69964	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	16	1	1	80070	80000	80100	80036	80036	80036	80036	80036
80204	80035	600	0	0	0	0	0	0	1829	25	80100	80100	80100	400500	1	49	76955	0	80035	80035	69964	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	0	0	0	0	711	25	80100	80100	80100	400500	1	49	76955	0	80035	80035	69964	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	3595	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	16	15	2112	1408	0	46	25	80100	80100	80100	400500	1	49	77633	0	80035	80035	69964	14	70158	80276	80434	240601	80397	164	6	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5122	1	25	1	1	80031	80000	80100	81030	80990	81173	81032	81158
80204	81118	607	0	24	2	0	0	1	46	25	80100	80100	80100	400500	1	49	76955	0	80035	80035	69964	3	69993	80100	80337	240991	80397	164	8	1	80201	100	99	100	80100	100	0	0	0	1	0	3	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	0	0	0	0	46	25	80100	80100	80100	400500	1	49	76955	0	80035	80035	69964	3	70021	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	1	0	0	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	0	0	0	0	46	25	80100	80100	80100	400500	1	49	76955	0	80035	80035	69964	8	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	2	2	1	0	0	0	0	5110	1	16	1	1	80031	80253	80100	80623	80308	80535	80583	80622

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? int retires (ef)	f5	f6	f7	f8	fd
80024	80035	600	0	0	0	0	46	25	80010	80010	80010	400050	0	0	49	76955	0	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	16	16	15	15	80032	80000	0	80010	80036	80036	80036	80036	80036
80024	80035	600	0	0	0	15	46	25	80010	80010	80010	400050	0	0	49	76955	0	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	18	16	14	13	80032	80000	0	80010	80036	80036	80036	80036	80036
80024	80035	599	0	0	0	0	46	25	80010	80010	80010	400050	0	0	49	76955	0	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	14	16	17	11	80032	80000	0	80010	80036	80036	80036	80036	80036
80024	80035	600	0	0	0	0	46	25	80010	80010	80010	400050	0	0	49	76955	0	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	3	0	0	0	5020	14	16	19	15	80032	80000	0	80010	80036	80036	80036	80036	80036
80024	80035	599	0	0	0	0	46	25	80010	80010	80010	400050	0	0	49	76955	0	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	15	16	13	10	80032	80000	0	80010	80036	80036	80036	80036	80036
80024	80035	599	0	0	0	0	46	25	80010	80010	80010	400050	0	0	49	76955	0	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	13	16	16	17	80032	80000	0	80010	80036	80036	80036	80036	80036
80024	80035	599	0	0	0	0	711	25	80010	80010	80010	400050	0	0	49	76955	0	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	12	16	15	16	80032	80000	0	80010	80036	80036	80036	80036	80036
80024	80073	600	0	0	0	0	711	25	80010	80010	80010	400050	0	0	49	76955	0	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	17	16	11	16	80032	80000	0	80010	80036	80036	80036	80036	80036
80024	80035	599	0	0	0	0	46	25	80010	80010	80010	400050	0	0	49	76955	0	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	54	0	0	0	5020	16	16	13	13	80032	80000	0	80010	80036	80036	80036	80036	80036
80024	80035	600	0	0	0	0	46	25	80010	80010	80010	400050	0	0	49	76955	0	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	14	16	16	17	80032	80000	0	80010	80036	80036	80036	80036	80036

UMADDL

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations