Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CAS (32-bit)

Test 1: uops

Code:

  cas w0, w1, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 70 nops): 4.001

Issues: 3.006

Integer unit issues: 0.000

Load/store unit issues: 3.006

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l1i tlb fill (04)l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)0f1e1f2223243a3f464951schedule uop (52)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)5f606163696a6b6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst int load (95)inst ldst (9b)9dl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafatomic or exclusive succ (b3)atomic or exclusive fail (b4)bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd0d1d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)dfe0eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
740093430125615030000110062000534733930012198930063009300922929500149309210337403400272630061002300910036012340505380217100110001000030134001004200602530079991221232152401070828000366608123720359744381660701033036190171640517536300010013403934067340763407934139
74005342072553101101110062000539233977002195930063006300622922400149310130337203413572530061002300610026012341312734217100110001000030093031005200601630079991221231151331076618002362516923794373744422669551033049191251640717618300010013414934134340863406734038
74005341232564101010010062000535233951002208430063006300622927600149278700339323405682630031002300610036012344265428217100110001000030095401005200601530079991221232151941077618029366326423998393144471570591033040189811644017512300010013406934006340883402234106
74005341592564101101010062000537533876002216930063006300622861200149276750337983411372530091002300610026018340562686217100110001000030166401006200601530079991221232151861086818012363726223816365644441766641133010190881633717633300010013410534148341203413434133
74005340702568110010010062000536633932002210630033009300322929600149310090338533403872530061002300310016012340782719217100110001000130123031003200402530109991220031148921061528016356916423746367544461465671032954189581644917582300010013415034095340543422434168
7400534024256210101101005200053383387110220253010300930032299060014927701033825341437253009100230061003600634083268621710011000100003011643100620060153007999122023315078107101806036451592378236134439186358933015188421642317297300010013408034058340393404934011
74005341872552100000010072000527433933102197930063006300622925510149277540337943403372530031002300910026012340012754217100110001000030104601004200400830109991221031150271072907982359406523773364944411470591033020191351637217470300010013395134000341223412834115
74005340612556101001010072000540234011002203230063006300922927700149310300338323410172530061003300610036012338952725217100110001000030104431006200800530109991221232149081064418001357015923726365544402168661133026190711646917473300010013400934114341063412434084
74005341332561101101010032000537933879002199930033006300622957000149309490337203413062530061002300610016012339862679217100110001000030094401005200602530079991221232151371069328000358005523854357144412165691132970189061652617418300010013397133976340453408934184
74005341352565101100010072000531934010002206130093006300622919000149311613338053420792630061003300910026012340472642217100110001000030115431005200401530079991221232151481079327991352806423786367044421661641033049191431628917409300010013402233994340553412434029

Test 2: throughput

Code:

  cas w0, w1, [x6]
  add x6, x6, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0067

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f1e1f202224293a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6b6d6emap stall dispatch (70)rob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9aaabacafatomic or exclusive succ (b3)atomic or exclusive fail (b4)b6bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2c3branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
50210300672251010038223227100101723006120048776796962540103101043000010103300015177714032891149269960300763007619897072005140102202073000920209600183006770112020110099100100001010010000100302903463750103052006926251020305304729998210207231330101011113170160030073100019930000201003007730077300773007730077
502043007622522200382011166101205108300521994169879766254010310102300001010330003518081402793004926987030067300671988907200424010320205300122020760024300767411202011009910010000101001000010030293174332001041620071192410382893039699982121881127333162011113170160030064100016630000201003006830068300683006830068
50204300672251000037513273101523963005218149737495822540103101033000010103300005177714027791249269873300673006719889072004240102202053001220205600243006770112020110099100100001010010000100302424423340103662007219002026230432999821523422102422111113170160030064100016630000201003006830068300683006830068
50204300672251100039343224100856300522224667969571254010210101300001010130001517811402773124926987030064300671989107200424010320200300002020060000300677011202021009910010000101001000010030232139302010375200701311828429830441999821722732243242310013101171130064100586630000201003006830068300683006830068
502043006722510000386152561096101123005216148628295952540100101013000010100300005179314027291249269870302223006719882032005340100202003000020200600003006872112020110099100100001010010000100302121312620103212008216284229182683042099982918222133010400013101171130073100019930000201003007730077300773007730077
502043007622520210380121841009212300612194672809620254010110101300001010030000518041403235104926996030073300761989303200584010020200300002020060000300677011202011009910010000101001000010030271435403010434200751720243123049699982422032382434300013101161130073100009930000201003007730077300773007730077
5020430076225200003749131891004108300521964661919557254010210102300001010030000518151402798104926987030067300671988203200504010020200300002020060000300677011202011009910010000101001000010030199235321010386200812419304231230396999821221832803020100013101171130073100009930000201003007730077300773007730077
50204300762252220038581020210064430052210346186986825401021010130000101003000051782140282411492698703006730067198840320050401002020030000202006000030076751120201100991001000010100100001003023116453260103502007520245018349304199998281891120127189400013101171130064100016630000201003006830069300683006830068
5020430067225100003886419410815192300612395785759641254010310101300001010030000517851403268124926996030073300761989103200584010020200300002020060000300677011202011009910010000101001000010030201250403010404200771524702430530366999821220331915020100013101161130073100009930000201003007830077300773007730078
50204300762252200038521018410408108300522054966699474254010210100300001010030000518161402657114926987030221300761989103200594010020200300002020060000300677311202011009910010000101001000010030151341285010362200711802448830030503999821023722183023400013101161130073100009930000201003007730077300773007730077

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0067

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f181e1f2022293a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6d6emap stall dispatch (70)rob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9aaabacafatomic or exclusive succ (b3)atomic or exclusive fail (b4)b6bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2c3cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
5003430067225000000373232061569108300521494966669908254001210010300001001030000513091403316124926987300673006719884032005040010200203000020020600003006770112002110910100001001010000010301640382961032720060232610243263041299982718922533000012703162230064100006630000200103006830068300683006830068
5002430067225110000372452261725923005219459825998862540011100103000010010300005134714027030049269873006730067198830320049400102002030000200206033030067711120021109101000010010100000103021103631410312200411000862843043599982919422012400112702172230064100006630000200103006830068300683006830068
50024300672251011003799416510760300521745860869898254001010010300001001030000513231402691104926987300673006719882032005040010200203000020020600003006770112002110910100001001010000010302196523841038420044154190463023033799982818232382421012702172230064100006630000200103006830068300683006830068
500243006722500000037663215115214172300521576043699491254001010010300001001030000513481402669104926987300673006719882032004940010200203000020020600003006770112002110910100001001010000010302410402661039820075123197182823038999982817922005700112702172230064100006630000200103006830068300683006830068
50024300672251010003725318711203812300521815170539568254001010064300001001030000513241402734104926987300643006719883032004940010200203000020020600003007072112002110910100001001010000010302424312731039520069202580282893035799982622321502451312702172230064100006630000200103006830068300683006830068
50024300672251000003870617910411443005214644596710009254017010010300001001030000513651402670124926987300673006719883032005040010200203000020020600003006770112002110910100001001010000010301716362801034020058150193303053029099982819122083024012702172230064100026630000200103006830068300683006830068
5002430067225000000372131951891403005218859926399062540010100103000010010300005134114027150149269873006730067198750320049400102002030000200206000030067701120021109101000010010100000103017505035310378200551916901002443028899982716631942400412702172230064100006630000200103006830068300683006830068
5002430067225100000374041931034830052178505762990325400101001030000100103000051331140278010492698730064300671988403200494001020020300002002060000300677311200211091010000100101000001030204343330103292006229199026321303809998213215327030401112702172330064100006630000200103006830069300683006830068
500243006722500000037204215101148300521624011073945825400101001130000100103000051340140279301492698730068300671988403200494001020020300002002060000300677011200211091010000100101000001030261162325103982007616409423330397999821115122133040412702163230064100006630000200103006830068300683006830068
5002430067226000000374941861062123005220354796195472540012100113000010010300005134714028170349269873006730067198820320049400102002030000200206000030067701120021109101000010010100000103023503130210406200671920103228230461999821220331775400112702172230064100006630000200103006830239300683006830068

Test 3: throughput

Code:

  cas w0, w1, [x6]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0110

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f18191e1f22243a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6367696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)797bmap int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acafatomic or exclusive succ (b3)atomic or exclusive fail (b4)bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2st memory order violation nonspec (c4)branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d1d5map dispatch bubble (d6)ddfetch restart (de)e0e2e7? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
40727301072254100000129062002300990781583329736578187366442055797210868352941049270300300963011730284700810557721304870442102361788209701235943010125621102011009910010000100100001100350550281461972121230010475416249999169892133013371226742012163352300951841009630000106133011130111301113010230114
407163010122542000001269520003008610015253284369271983655820957015102082930510492701803011030117298445408115582142999714720825611282109912349830101246211020110099100100001001000001003521200160204192126101122840758999916862212301362113664806207271519301071796006030000106163011330120301143010230127
40720301262251100000127392102300861661516340336764191359612075741797483290011492703003011030110287947288447577813107742820761605822092312313830113235211020110099100100001001000001003528500156205802120701038741736999917058002301320113667400146762119300941796009630000106133011430102301143011130102
407143011022561000001286920013009808614693276369732023683119357524938834492104927021030105300982742456682425804330787008207466095120680122268301101972110201100991001000010010000010035118034092032021339010129415549999170430123013942136606114286702115301121837009030000106083011130102301113011430114
40712301012264200000136122000300981801465338936470202364211945743597283363310492703003010130110289645768269580203137714820808614012088312296430110245211020110099100100001001000001003500302813320048213290101424123399991735021230137022466451151667634300981864209630000106123011430114301273011130111
407103012522552000001332521093010018101505321136598202365852075751110148336191049270323301073011031224617805257769327569172080660699209661226043010124221102011009910010000100100000100350880341310202512129301021241273999916840212301332113665200136441815300951812109630000106133011130114300993011130113
40716301102264200000134780107300991801466330536573199366412035713010728364611049270300301033011028824493814857452310671752101461647207631223403010129821102011009910010000100100000100351530014112029321223010207411289999170690023013571126620013764042300981837000630000106103011630111301113009930116
407153011322652000001303121093009805014133235366262023631920357344100683697510492701803011030110283544858215578453008692621043616112108612293430119248211020110099100100001001000001003496003416619925212560990641594999917219212301324112667910237071813300981813109930000106063011430111301023011430126
4071530113225020000013410200730095095137733563667720136257196573569808319951049270300301143011031134516817457230303369382086661302207551232343009825421102011009910010000100100000100352510341582074021358010471412139999171311412301349122678416236641814300961802009030000106103010230118301143011430124
407103009822625000001367021073009816014483416371252003641721257359100783516010492701803010730113331344128076577072988697120882616952061012194430114203211020110099100100001001000001003509202800198542118201050841050999916835212301360112672718266692425301041783000630000106063011430103301113011130102

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0113

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f2223243a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6367696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)797bmap int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafatomic or exclusive succ (b3)atomic or exclusive fail (b4)bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)c2st memory order violation nonspec (c4)cdcfd1d5map dispatch bubble (d6)ddfetch restart (de)e0e2e7? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
40540301172250001100216992100030095207988361539295213934822610691007977831049270333011430110178849646283611841655382165564752215921294743011724421100211091010000101000011037965001682798121907001912549751999911372421201083062720166151313301081911309630000105283011430114301143011430102
40541301132260000000213742100030098287946348839438213923621612241247940011049270333011030110178849466227611671915052165864680216161296423010123221100211091010000101000001037891034002789121848001926549766999911354221201064062940126151215301231883009030000105283011430114301143010230114
4054030101226000000021474010003009820010413559393602039466216096810579093910492702130113301131860483863706108420955921624646922166312919830110251211002110910100001010000010377550341502778221939001917049852999911360120001089062950146461313301091851406030000105263011430115301143011430102
40542301132250000000215052000030098290101736723941420394212060998100790989104927037301133011717364914638060936212622215886468321668129426301132462110021109101000010100000103782002815827813218860019175498559999113617012010920633212115861414300981919406630000105283011730102301143011430117
4054230113226000000021538210003008607099336013938622395112061139998002981049270303011330113176748286366609521985072157964947215911292883011330021100211091010000101000001037863000192780021969001933950032999911365100201071062849126421314300971881309630000105273011430103301143011430114
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