Firestorm: LDP (signed offset, 64-bit) measurements

Code:

  ldp x0, x1, [x6, #8]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	0e	0f	18	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
2005	394	3	0	0	0	0	45	1	0	1	379	3	12	12	16	25	1000	1000	1000	15065	1	394	394	92	3	127	1000	2000	1000	394	35	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	3	16	2	2	391	10	10	4	1000	1000	395	395	395	395	395
2004	394	2	0	0	0	0	45	0	0	1	379	2	12	12	16	25	1000	1000	1000	15065	1	394	394	92	3	128	1000	2000	1000	394	35	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	2	16	2	2	391	10	10	4	1000	1000	395	395	395	395	395
2004	394	3	0	0	0	0	45	1	0	1	379	2	12	12	16	25	1000	1000	1000	15014	0	394	394	92	3	127	1000	2000	1000	394	35	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	2	16	2	2	391	10	10	4	1000	1000	395	395	395	395	395
2004	394	3	0	0	0	0	45	1	0	1	379	2	12	12	16	25	1000	1000	1000	15226	1	394	394	92	3	127	1000	2000	1000	394	35	1	1	1001	1000	1000	0	1000	43	1039	1	39	1039	6	1	39	43	73	2	16	2	2	391	10	10	4	1000	1000	395	395	395	397	395
2004	394	3	0	0	0	0	45	1	0	1	379	2	12	12	16	25	1000	1000	1000	15014	1	394	394	92	3	127	1000	2000	1000	394	35	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	2	16	2	2	391	10	10	4	1000	1000	395	395	395	395	395
2004	394	3	0	0	0	0	45	1	0	1	379	2	12	12	16	25	1000	1000	1000	15014	1	394	394	92	3	127	1000	2000	1000	394	35	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	2	16	2	2	391	10	10	4	1000	1000	395	395	396	395	395
2004	394	2	0	0	0	0	45	1	0	1	379	2	12	12	16	25	1000	1000	1000	15014	0	394	394	92	3	127	1000	2000	1000	394	35	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	2	16	2	2	391	10	10	4	1000	1000	395	395	395	395	395
2004	394	2	0	0	0	0	45	1	0	1	379	2	12	12	16	25	1000	1000	1000	15065	0	394	394	92	3	127	1000	2000	1000	394	35	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	2	16	2	2	391	10	10	4	1000	1000	395	395	395	395	395
2004	394	3	0	1	0	0	45	1	0	1	379	2	12	12	16	25	1000	1000	1000	15053	0	394	394	92	3	127	1000	2000	1000	394	35	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	2	16	2	2	391	10	10	4	1000	1000	395	395	395	395	395
2004	394	3	0	0	0	0	45	1	0	1	379	2	12	12	16	25	1000	1000	1000	15065	0	394	394	92	3	127	1000	2000	1000	394	35	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	2	16	2	2	391	10	10	4	1000	1000	395	395	395	395	395

Test 2: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldp x0, x1, [x6, #8]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	70047	525	0	1	0	0	0	40	0	1	0	0	70020	69711	59694	25	40104	30103	10001	30100	10000	613756	3341304	0	49	66957	70036	70234	63405	0	3	63695	40100	30200	20000	60200	10000	70047	37	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	0	10000	1	0	0	2610	2	64	1	1	69798	30003	0	6	0	10000	40100	70036	70048	70048	70048	70048
50204	70052	525	0	1	1	0	4	1	0	0	0	0	70032	69698	59694	25	40100	30100	10001	30266	10000	613756	3341906	0	49	66955	70047	70035	63400	0	3	63695	40100	30200	20000	60200	10000	70047	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	0	2610	1	64	1	1	69810	30003	6	6	6	10000	40100	70048	70048	70048	70048	70048
50204	70047	524	0	0	1	0	0	0	0	0	0	0	70032	69711	59684	25	40100	30103	10001	30100	10000	613756	3341906	0	49	66967	70047	70047	63400	0	3	63707	40100	30200	20000	60200	10000	70047	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	2610	1	64	1	1	69810	30000	6	0	6	10000	40100	70059	70048	70040	70048	70048
50204	70047	525	0	0	0	0	0	0	0	0	0	0	70020	69698	59684	25	40104	30103	10000	30100	10000	613915	3341304	0	49	66955	70047	70047	63388	0	3	63695	40100	30200	20000	60200	10000	70047	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	0	2610	1	64	1	1	69810	30003	6	6	6	10000	40100	70048	70036	70036	70036	70048
50204	70047	525	0	0	1	0	0	0	0	1	0	0	70020	69698	59684	25	40104	30103	10000	30100	10000	613756	3341304	0	49	66967	70047	70047	63388	0	3	63707	40885	30200	20000	60200	10000	70047	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10008	0	0	10000	0	0	0	10000	1	0	0	2610	1	64	1	1	69802	30000	0	0	0	10000	40100	70036	70036	70036	70048	70036
50204	70047	525	0	0	0	0	0	1	0	1	0	0	70020	69711	59684	25	40104	30103	10001	30100	10000	613715	3351425	0	49	66967	70035	70047	63403	0	3	63695	40100	30200	20000	61500	10000	70035	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	10000	1	1	0	2610	1	64	1	1	69798	30000	6	6	0	10000	40100	70048	70036	70036	70048	70048
50204	70035	524	0	0	0	0	0	1	0	0	1	0	70032	69716	59823	25	40100	30100	10001	30100	10000	613756	3341906	0	49	66967	70035	70035	63400	0	3	63707	40100	30200	20000	60200	10000	70047	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	1	0	10000	1	0	0	2610	1	64	1	1	69798	30003	6	0	0	10000	40100	70036	70048	70048	70036	70036
50204	70323	524	0	0	0	0	0	1	0	0	1	0	70032	69711	59684	25	40100	30103	10001	30100	10000	613652	3341906	0	49	66969	70047	70035	63388	0	3	63707	40100	30200	20000	60200	10000	70042	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	1	3	0	10000	1	0	0	2610	1	64	1	1	69810	30003	6	0	0	10000	40100	70036	70048	70048	70048	70048
50204	70105	525	1	0	0	0	0	1	0	0	0	0	70020	69711	59694	25	40104	30103	10001	30100	10000	613652	3341906	0	49	66967	70035	70047	63388	0	3	63707	40100	30200	20000	60200	10000	70035	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	10000	1	1	0	2610	1	64	1	1	69810	30003	0	6	6	10000	40100	70036	70048	70036	70048	70051
50204	70050	525	0	1	1	0	0	1	0	0	0	0	70032	69711	59694	25	40104	30103	10000	30100	10000	613756	3341448	0	49	66967	70035	70035	63400	0	3	63707	40100	30200	20000	60200	10000	70035	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	10000	0	0	0	2610	1	64	1	1	69798	30000	6	6	6	10000	40100	70048	70036	70048	70036	70065

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0057

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	19	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	70060	525	1	0	1	1	0	1	0	0	0	2	0	0	2	70042	69722	59695	25	40018	30016	10002	30010	10000	615508	3342398	0	49	66977	70057	70057	63425	3	63739	40010	30020	20000	60020	10000	70057	37	1	1	40021	10	9	10	10000	30010	10000	10	10002	1	1	10001	0	2	1	10000	1	1	1	1	2	2521	7	64	13	9	69911	30006	0	10	10	10000	40010	70062	70058	70058	70042	70042
50024	70041	524	1	0	1	1	0	1	0	0	0	2	1	0	2	70042	69722	59710	25	40018	30016	10001	30010	10000	615508	3342398	0	49	66977	70041	70057	63409	3	63739	40010	30020	20000	60020	10000	70057	37	1	1	40021	10	9	10	10000	30010	10000	10	10001	1	1	10001	0	0	1	10000	1	1	1	1	0	2521	8	64	11	9	69820	30006	10	10	0	10000	40010	70058	70042	70058	70058	70058
50024	70057	525	1	0	0	1	0	0	1	0	0	2	1	0	1	70026	69697	59710	25	40018	30013	10001	30010	10000	615508	3342398	0	49	66977	70057	70057	63425	3	63739	40010	30020	20138	60020	10000	70041	37	1	1	40021	10	9	10	10000	30010	10000	10	10002	2	0	10002	0	0	1	10000	1	1	1	1	2	2521	10	64	8	8	69824	30006	10	10	10	10000	40010	70058	70058	70058	70058	70058
50024	70057	525	1	0	0	1	0	1	0	0	0	2	1	0	0	70042	69697	59710	25	40018	30016	10002	30010	10000	615508	3342398	0	49	66977	70057	70041	63425	3	63722	40010	30020	20000	60020	10000	70057	37	1	1	40021	10	9	10	10000	30010	10000	10	10001	2	1	10002	0	1	1	10000	1	1	1	1	0	2521	9	64	9	7	69820	30006	10	10	10	10000	40010	70058	70058	70042	70058	70058
50024	70057	524	1	0	1	0	0	0	0	0	0	2	1	0	0	70042	69722	59710	25	40018	30016	10002	30010	10000	615508	3342398	0	49	66961	70057	70057	63409	3	63722	40010	30020	20000	60020	10000	70057	37	1	1	40021	10	9	10	10000	30010	10000	10	10001	2	1	10002	0	1	1	10000	1	1	1	1	1	2521	9	64	11	8	69844	30006	10	10	0	10000	40010	70058	70042	70058	70058	70042
50024	70057	525	1	1	1	1	0	0	0	0	0	2	1	0	1	70042	69722	59710	25	40018	30016	10002	30010	10000	615508	3341614	0	49	66977	70057	70041	63425	3	63739	40010	30020	20000	60020	10000	70057	37	1	1	40021	10	9	10	10000	30010	10000	10	10002	2	1	10002	0	2	1	10000	1	1	1	1	0	2521	9	64	8	9	69832	30006	10	0	10	10000	40010	70058	70058	70058	70058	70042
50024	70057	524	1	0	1	1	0	0	0	0	0	7	1	0	1	70042	69722	59710	25	40018	30016	10002	30010	10000	615508	3342398	0	49	66977	70057	70057	63425	3	63739	40010	30020	20000	60020	10000	70057	37	1	1	40021	10	9	10	10000	30010	10000	10	10003	3	1	10002	0	2	1	10000	0	1	1	1	2	2521	9	65	7	7	69823	30006	10	10	0	10000	40010	70058	70058	70042	70058	70058
50024	70057	524	1	0	1	1	0	0	0	0	0	2	1	0	1	70042	69697	59710	25	40031	30016	10002	30010	10000	615508	3342398	0	49	66977	70042	70063	63425	3	63725	40010	30020	20000	60020	10000	70057	37	1	1	40021	10	9	10	10000	30010	10000	10	10002	2	1	10001	0	1	1	10000	1	1	1	1	2	2521	7	65	8	7	69820	30006	10	10	0	10000	40010	70058	70058	70058	70058	70058
50024	70057	525	1	0	0	1	0	1	0	0	0	1	1	0	1	70042	69722	59710	25	40018	30016	10002	30010	10000	615508	3342398	0	49	66977	70057	70057	63425	3	63739	40010	30020	20000	60020	10000	70057	37	1	1	40021	10	9	10	10000	30010	10000	10	10002	1	1	10002	0	1	1	10000	1	1	1	1	2	2521	8	65	11	7	69824	30006	10	10	10	10000	40010	70058	70058	70058	70058	70058
50025	70146	525	1	0	0	1	0	1	0	0	0	2	0	0	1	70042	69697	59710	25	40018	30016	10001	30010	10000	615163	3342398	0	49	66977	70057	70057	63425	3	63739	40010	30020	20000	60020	10000	70057	37	1	1	40021	10	9	10	10000	30010	10000	10	10003	2	1	10001	0	1	1	10000	1	1	1	1	1	2521	7	64	12	10	69810	30006	10	10	10	10000	40010	70042	70058	70058	70058	70058

Test 3: Latency 2->3 (with chain penalty)

Chain cycles: 3

Code:

  ldp x0, x1, [x6, #8]
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	70047	524	0	0	0	0	0	0	0	1	0	0	0	70020	69711	59723	25	40104	30103	10001	30111	10007	613306	3341473	49	66967	70047	70047	63444	0	7	63742	40118	30233	20023	60266	10012	70035	37	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	10000	1	1	1	1	1	2620	0	16	0	0	69857	30000	0	6	6	10000	40100	70048	70036	70048	70048	70048
50204	70035	524	0	0	0	0	0	0	0	1	0	0	0	70032	69711	59733	25	40100	30103	10001	30111	10007	613306	3342075	49	66967	70035	70035	63444	0	3	63707	40100	30200	20000	60200	10000	70047	37	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	10000	1	1	0	0	0	2610	1	64	1	1	69798	30000	6	6	6	10000	40100	70048	70048	70048	70036	70048
50204	70047	525	0	0	0	0	0	0	0	1	132	1	0	70032	69711	59694	25	40104	30100	10001	30100	10000	613756	3341906	49	66967	70047	70047	63388	0	3	63748	40100	30200	20000	60200	10000	70047	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10003	1	1	0	0	0	2610	1	64	1	1	69810	30003	6	6	6	10000	40100	70048	70048	70048	70048	70048
50204	70047	525	0	0	0	0	0	0	0	10	0	0	0	70032	69711	59684	25	40104	30103	10001	30100	10000	613756	3341906	49	66967	70047	70047	63400	0	3	63707	40100	30200	20000	60200	10000	70047	37	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	10000	1	0	0	0	0	2610	1	64	1	1	69810	30003	6	6	6	10000	40100	70048	70036	70048	70048	70048
50204	70047	525	0	0	0	0	0	0	0	1	0	1	0	70032	69711	59694	25	40104	30103	10001	30100	10000	614591	3341906	49	66967	70047	70047	63400	0	3	63707	40100	30200	20000	60200	10000	70047	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	0	0	2610	1	64	1	1	69810	30003	0	6	6	10000	40100	70048	70048	70048	70048	70048
50204	70047	525	0	0	0	0	0	0	0	0	0	1	0	70032	69714	59694	25	40104	30103	10003	30100	10000	613652	3341906	49	66967	70047	70035	63400	0	3	63707	40100	30200	20000	60200	10000	70047	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	0	1	0	0	0	2610	1	64	1	1	69810	30003	6	6	6	10000	40100	70048	70048	70048	70048	70048
50204	70047	525	0	0	0	0	0	0	0	1	0	0	0	70032	69711	59684	25	40104	30103	10001	30100	10000	613756	3341304	49	66967	70047	70047	63400	0	3	63695	40100	30200	20000	60200	10000	70047	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	1	0	10000	1	1	0	0	0	2610	1	64	1	1	69810	30003	0	6	6	10000	40100	70048	70048	70048	70048	70048
50204	70047	525	0	0	0	0	1	0	0	0	0	0	0	70032	69711	59694	25	40104	30103	10001	30100	10000	613756	3341906	49	66967	70047	70035	63400	0	3	63707	40100	30200	20000	60200	10000	70035	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	1	0	0	0	2610	1	17	1	1	69810	30003	6	6	6	10000	40100	70048	70048	70048	70048	70048
50204	70047	524	0	0	0	0	0	0	0	1	0	0	1	70032	69711	59694	25	40104	30103	10001	30100	10000	613756	3341906	49	64010	70047	70051	63400	0	3	63707	40100	30200	20000	60200	10000	70035	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	0	0	2610	1	64	1	1	69810	30003	6	6	6	10000	40100	70048	70048	70048	70036	70048
50204	70047	525	0	0	0	0	0	0	0	1	0	0	0	70020	69711	59694	25	40104	30103	10001	30100	10000	613756	3341906	49	66967	70047	70047	63400	0	3	63707	40100	30200	20000	60200	10000	70047	37	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	10000	1	0	0	0	0	2610	1	64	1	1	69798	30003	6	6	6	10000	40100	70048	70048	70048	70048	70048

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0057

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	70057	524	1	1	1	0	0	0	2	1	0	1	70042	69722	59710	25	40018	30016	10002	30010	10000	615508	3342542	1	49	66977	0	70060	70060	63425	0	3	63786	40010	30020	20000	60020	10000	70057	37	1	1	40021	10	9	10	10000	30010	10000	1	10	10002	2	1	10002	0	2	1	10000	1	1	1	1	2	0	2520	0	13	64	12	16	69820	30006	13	10	10	10000	40010	70058	70061	70058	70061	70058
50024	70057	524	1	0	0	0	0	0	2	1	0	0	70042	69722	59710	25	40018	30016	10002	30010	10000	615508	3341614	1	49	66961	0	70041	70057	63428	0	3	63743	40010	30020	20000	60020	10000	70057	37	1	1	40021	10	9	10	10000	30010	10000	1	10	10002	2	1	10002	0	2	1	10000	1	1	1	1	0	0	2520	0	6	64	14	12	69820	30003	10	10	10	10000	40010	70058	70061	70058	70061	70058
50025	70126	525	1	0	0	0	0	1	2	1	0	0	70026	69722	59713	25	40014	30016	10002	30010	10000	615163	3342542	1	49	66977	0	70057	70060	63428	0	3	63790	40010	30020	20000	60020	10000	70057	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	1	10001	0	0	4	10000	0	1	1	1	0	0	2520	0	12	64	14	11	69823	30006	10	10	10	10000	40010	70058	70058	70058	70042	70058
50024	70057	525	1	0	1	1	0	0	1	1	0	1	70042	69725	59713	25	40018	30016	10002	30010	10000	615535	3342542	0	49	66977	0	70060	70057	63428	0	3	63785	40010	30020	20000	60020	10000	70041	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	1	10001	1	1	1	10000	1	1	1	1	2	0	2520	0	11	64	8	14	69823	30006	0	13	10	10000	40010	70058	70061	70061	70061	70042
50024	70063	525	1	1	0	0	0	0	1	1	0	1	70042	69722	59710	25	40018	30016	10002	30010	10000	615163	3342398	0	49	66977	0	70057	70060	63425	0	3	63741	40010	30020	20000	60020	10000	70041	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10003	1	1	10002	0	1	1	10000	1	1	1	1	1	0	2520	0	11	65	13	8	69823	30006	10	10	10	10000	40010	70042	70061	70058	70072	70058
50024	70041	525	1	1	1	1	0	0	2	1	0	1	70042	69697	59710	25	40014	30016	10002	30010	10000	615163	3342398	1	49	66961	0	70060	70041	63428	0	3	63760	40010	30020	20000	60020	10065	70057	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10001	0	1	1	10000	1	1	1	1	2	0	2520	0	13	64	7	14	69820	30006	13	13	13	10000	40010	70058	70042	70058	70058	70058
50024	70058	525	1	0	0	1	0	0	2	1	0	1	70026	69725	59710	25	40018	30016	10002	30010	10000	615508	3342398	0	49	66977	0	70060	70057	63425	0	3	63751	40010	30020	20000	60020	10000	70060	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	1	10002	0	1	1	10000	1	1	1	1	0	0	2520	0	14	64	9	14	69820	30003	13	10	10	10000	40010	70058	70061	70058	70061	70058
50025	70057	525	1	1	1	1	0	0	1	1	0	1	70042	69725	59712	25	40018	30016	10002	30010	10000	615163	3342542	0	49	66961	0	70057	70057	63428	0	3	63788	40010	30020	20000	60020	10000	70060	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	1	10001	0	0	1	10000	1	1	1	1	0	0	2520	0	13	64	12	13	69805	30003	0	13	10	10000	40010	70042	70058	70042	70058	70042
50024	70041	525	1	1	1	1	0	0	2	1	0	0	70042	69722	59710	25	40018	30016	10002	30010	10000	615163	3342542	0	49	66977	0	70057	70057	63409	0	3	63777	40010	30020	20000	60020	10000	70041	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	0	10002	0	0	1	10000	1	1	1	1	0	0	2520	0	13	64	13	6	69820	30006	10	10	13	10000	40010	70058	70061	70058	70042	70058
50024	70057	525	1	1	1	0	0	0	556	1	0	0	70042	69722	59710	25	40018	30016	10002	30010	10000	615163	3342398	1	49	66977	0	70057	70057	63409	0	3	63742	40010	30020	20000	60020	10000	70057	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10002	0	1	1	10000	1	1	0	1	0	0	2520	0	7	64	14	7	69823	30006	13	13	0	10000	40010	70042	70042	70061	70061	70058

Test 4: throughput

Count: 8

Code:

  ldp x0, x1, [x6, #8]
  ldp x0, x1, [x6, #8]
  ldp x0, x1, [x6, #8]
  ldp x0, x1, [x6, #8]
  ldp x0, x1, [x6, #8]
  ldp x0, x1, [x6, #8]
  ldp x0, x1, [x6, #8]
  ldp x0, x1, [x6, #8]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160205	26732	200	1	0	1	0	89	1	0	3	26718	2	0	18	16	25	80100	100	80000	100	80000	500	1164410	0	49	23652	26814	26738	6685	0	3	6690	80100	200	160000	200	80000	26714	35	1	1	80201	100	99	100	80000	100	80000	0	100	80020	22	42	80058	1	0	1	59	80038	6	1	57	42	19	1	5110	1	16	1	1	26729	0	9	2	80000	80100	26733	26733	26733	26715	26733
160204	26714	200	1	1	1	0	122	1	0	3	26717	2	18	0	16	25	80100	100	80000	100	80000	500	1173093	0	49	23654	26805	26737	6657	0	3	6672	80100	200	160000	200	80000	26732	35	1	1	80201	100	99	100	80000	100	80000	0	100	80019	20	0	80057	1	0	1	59	80038	6	1	57	42	19	2	5110	1	16	2	1	26735	9	9	2	80000	80100	26733	26715	26733	26733	26733
160204	26732	200	1	0	1	0	65	1	0	1	26717	2	18	18	15	25	80100	100	80000	100	80000	500	1167530	1	49	23652	26846	26743	6725	0	3	6690	80100	200	160000	200	80000	26732	35	1	1	80201	100	99	100	80000	100	80000	0	100	80021	21	0	80056	1	0	2	21	80037	0	1	56	0	19	1	5110	1	16	1	1	26729	9	0	2	80000	80100	26733	26715	26733	26733	26733
160204	26732	200	1	0	1	0	92	1	0	2	26717	2	0	18	16	25	80100	100	80000	100	80000	500	1170529	1	49	23652	26835	26738	6667	0	3	6672	80100	200	160000	200	80000	26732	35	1	1	80201	100	99	100	80000	100	80000	0	100	80019	19	42	80057	0	0	2	59	80038	6	1	57	42	19	0	5110	1	16	1	1	26733	9	9	2	80000	80100	26733	26733	26733	26733	26733
160204	26732	200	1	1	1	0	78	1	0	3	26717	3	18	18	15	25	80100	100	80000	100	80000	500	1167530	1	49	23652	26828	26741	6667	0	3	6690	80100	200	160000	200	80000	26732	35	1	1	80201	100	99	100	80000	100	80000	0	100	80019	20	42	80057	0	0	0	59	80038	6	1	57	42	19	0	5110	1	16	1	1	26711	9	0	2	80000	80100	26733	26733	26733	26733	26733
160204	26732	200	1	1	1	0	95	0	0	3	26717	3	18	18	16	25	80100	100	80000	100	80000	500	1171570	1	49	23652	26732	26732	6797	0	3	6696	80100	200	160000	200	80000	26732	35	1	1	80201	100	99	100	80000	100	80000	0	100	80019	20	42	80057	0	0	0	59	80038	0	1	58	42	19	2	5110	1	16	1	1	26729	9	9	0	80000	80100	26733	26715	26715	26733	26715
160204	26732	200	1	1	0	0	98	0	0	3	26717	2	18	18	16	25	80100	100	80000	100	80000	500	1180419	1	49	23652	26738	26734	6789	0	3	6813	80100	200	160000	200	80000	26732	35	1	1	80201	100	99	100	80000	100	80000	0	100	80021	19	42	80056	1	0	2	59	80037	6	1	57	42	19	1	5110	1	16	1	1	26729	9	9	2	80000	80100	26715	26733	26900	26744	26733
160204	26732	201	1	1	1	0	77	0	0	3	26717	2	18	18	17	25	80100	100	80000	100	80000	500	1170682	1	49	23652	26831	26737	6663	0	3	6690	80100	200	160000	200	80000	26732	35	1	1	80201	100	99	100	80000	100	80000	0	100	80021	19	0	80019	1	0	0	59	80038	6	1	57	0	19	2	5110	1	16	1	1	26729	9	9	2	80000	80100	26733	26733	26733	26733	26733
160204	26732	200	1	0	1	0	80	1	0	2	26717	2	18	18	0	25	80100	100	80000	100	80000	500	1171570	1	49	23652	26841	26737	6662	0	3	6690	80100	200	160000	200	80000	26732	35	1	1	80201	100	99	100	80000	100	80000	0	100	80021	20	42	80057	1	0	1	59	80000	6	1	57	42	19	1	5110	1	16	1	1	26729	9	9	2	80000	80100	26733	26715	26733	26715	26733
160204	26732	200	1	1	1	0	71	1	0	3	26717	2	18	18	16	25	80100	100	80000	100	80000	500	1167999	1	49	23652	26833	26738	6663	0	3	6690	80100	200	160000	200	80000	26714	35	1	1	80201	100	99	100	80000	100	80000	0	100	80019	19	42	80057	1	0	4	21	80000	6	1	57	42	19	1	5110	1	16	1	1	26711	9	9	2	80000	80100	26733	26733	26733	26733	26733

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160025	26726	200	0	0	81	1	0	2	26712	0	18	18	0	25	80010	10	80000	10	80000	50	1174628	0	49	23647	26727	26707	6668	3	6702	80010	20	160000	20	80000	26707	35	1	1	80021	10	9	10	80000	10	80000	1	10	80000	39	80039	0	0	80000	6	0	35	0	5020	0	29	16	0	0	28	27	26951	4	6	2	80000	80010	26728	26728	26708	26708	26728
160024	26727	200	1	1	36	1	0	1	26712	2	12	18	0	25	80010	10	80000	10	80000	50	1170107	0	49	23647	26727	26722	6653	3	6715	80010	20	160000	20	80000	26727	35	1	1	80021	10	9	10	80000	10	80000	1	10	80000	0	80000	0	35	80039	6	1	35	0	5020	0	16	16	0	0	26	16	26724	10	6	4	80000	80010	26728	26708	26728	26728	26728
160024	26722	200	0	1	51	0	0	2	26712	2	12	12	16	25	80010	10	80000	10	80000	50	1174628	1	49	23642	26722	26727	6668	3	6695	80010	20	160000	20	80000	26722	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80039	0	39	80039	6	1	39	39	5020	0	27	16	0	0	25	27	26724	10	0	0	80000	80010	26728	26728	26728	26728	26728
160024	26707	200	0	0	24	1	0	2	26707	0	18	18	0	25	80010	10	80000	10	80000	50	1168754	1	49	23647	26722	26707	6668	3	6715	80010	20	160000	20	80000	26707	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80000	0	35	80035	0	1	35	43	5020	0	27	16	0	0	26	26	26724	0	6	0	80000	80010	26728	26708	26708	26708	26723
160024	26707	200	0	0	78	1	0	2	26712	2	12	0	16	25	80010	10	80000	10	80000	50	1174628	1	49	23647	26727	26727	6653	3	6702	80010	20	160000	20	80000	26722	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80000	0	39	80000	6	1	0	43	5020	0	28	16	0	0	17	31	26704	10	0	2	80000	80010	26708	26723	26723	26728	26723
160024	26722	200	0	0	198	1	0	2	26890	2	12	12	16	25	80010	10	80000	10	80000	50	1173183	1	49	23627	26727	26727	6817	3	6711	80010	20	160000	20	80000	26707	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80170	0	0	80000	6	1	39	43	5020	0	28	16	0	0	27	18	26724	4	6	0	80000	80010	26728	26723	26728	26708	26728
160024	26707	200	0	0	60	1	0	2	26707	2	18	12	11	25	80010	10	80000	10	80000	50	1170107	1	49	23627	26727	26729	6848	3	6707	80010	20	160000	20	80000	26707	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80035	0	0	80039	6	1	35	43	5020	0	26	16	0	0	25	26	26704	10	0	4	80000	80010	26708	26708	26728	26723	26728
160024	26707	200	0	0	64	1	0	2	26707	2	18	18	16	25	80010	10	80000	10	80000	50	1168880	1	49	23647	26727	26722	6668	3	6695	80010	20	160000	20	80000	26727	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80039	0	39	80039	0	1	0	0	5020	0	18	16	0	0	25	15	26704	0	6	2	80000	80010	26723	26708	26708	26708	26728
160024	26727	200	0	0	84	0	0	2	26692	2	0	12	16	25	80010	10	80000	10	80000	50	1173183	1	49	23647	26727	26727	6668	3	6871	80010	20	160000	20	80000	26727	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80039	0	39	80051	6	1	0	43	5020	0	27	16	0	0	17	26	26724	4	10	4	80000	80010	26728	26708	26708	26708	26723
160024	26710	200	0	0	0	0	0	1	26712	2	18	12	16	25	80010	10	80000	10	80000	50	1168754	1	49	23647	26727	26727	6668	3	6710	80010	20	160000	20	80000	26707	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80039	0	42	80039	6	1	0	43	5020	0	17	16	0	0	27	17	26724	10	6	4	80000	80010	26728	26708	26728	26728	26708

LDP (signed offset, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations