Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STADDLB

Test 1: uops

Code:

  staddlb w0, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 70 nops): 3.000

Issues: 3.005

Integer unit issues: 1.005

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l1i tlb fill (04)l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f1e22243a3f464951schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)5f696a6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst int load (95)inst ldst (9b)9dl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd0d1d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
73005332872483010020111002005772325850021082300310042000100020001102216850249299023291933021313300010002000200040003309626351171001100010001200330210081001026200571222116484114401823940340502299237744438164638323551006160531578115097200010003269933177330493276432993
73004327842460101101111045005951331130020788300410042000100020001108916991249298513264033106313300010002000200040003287925861171001100010000200002210031000003200330200016510120830828040680402290437844443154544323481005164311468915925200010003272232736326073277332623
73004328662461000000001005105755331511120652300410042000100020001100416964049298863271233253313300010002000200040003280025901171001100010000200002210031000003200320220015570111572842237590522290037434437204342325601005162951452314595200010003292132727326133276432991
73004327432463000000001054105577327981120703300510042000100020001099616996549299583290832816313300010002000200040003275026231171001100010001200002210031000003200350200015751121381844738350352279838644437123641323521004165031458415974200010003265232662327013262932897
73004332332450000000001002106098328251121047300410072000100020001110016887449298913307732850313300010002000200040003280525791171001100010000200002010031000004200430220415736120471844137370382281339574444184339323221004160941461015178200010003258032707330663270833087
7300432705245000000001100400592632574112076230071003200010002000110641699124929979327323296831030001000200020004000326992602117100110001000020000221003100000320053002001573811338184893968042229314138444693742324431004174451430615396200010003298232800326373264632652
73004326342450000000001004106037332111121066300610032000100020001106716971049298583283133055313300010002000200040003296325951171001100010000200002210051000005200530220015689118891828739540372321140124437143437323111003163241481116330200010003272333104331773257932646
73004326462440000000001003006099330191020555300710042000100020001097816824549298433277833257313300010002000200040003262025571171001100010000200002210031000006200220000016171119812855640990402287037464449114443323531004175311437915063200010003265532728327173276932713
73004325892450000000001002106079326330120995300710072000100020001100516880249298473304233126313300010002000200040003277426231171001100010000200002210031000005200330220015653119692845038170382288938064444204140323651007168071456715288200010003306833049327123273632600
73004327582480000000011004105838330141020674300510052000100020001097516883349300873291433090310300010002000200040003310625951171001100010000200000210051000005200650220216522123402846938830402279839744440173743323941004171351454715089200010003302632650331113308532770

Test 2: throughput

Code:

  staddlb w0, [x6]
  add x6, x6, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0069

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f2022293a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9e9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9aaabacafb6bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
4020670069525220200005053930101707005605201658010254035920535200002010020000204552333215220169496698907002970069644943650274010020200200003020040000700696511202011009910010000101001000000100200481913255198721008610009323442652006013595222219213101161169856204429920000201007007070070700707007070070
402047006952520220000507110241015070054305141258049254033420344200002010020000204571233211331964966989070033700696449436502740100202002000030200400007006967112020110099100100001010010000001002005617954219872100721000914286412004513795211614413101171169856204689920000201007007070070700707007070070
4020470069525220200005078920106070054354985808525403692039520000201002000020446383321772125949669900700297006964507365027401002020020000302004000070069651120201100991001000010100100000010020045141145419872100831001913445464200491369527815213101171169856204699920000201007007070070700707005770070
4020470069524202200005063102310100700542951010582912540347203952000020100200002045012332149911484966989070029700696450736502640100202002000030200400007006912711202011009910010000101001000000100200481713153198721006910008332518472004403194511414213101161169856202629920000201007007070070700707007070070
402047006952520020000512185030203670054165111058976254038320384200002010020000204515633221071884966990070029700696450725650274010020200210563020040000700566711202011009910010000101001000000100200421712749198721009210009223612702007223597133114413101161169856202529920000201007007070070700707007070070
40204700695242222000050988491090700542557858640254032820389200002010020000204482433212641146496698907003370069645073650274010020200200003020040000700696411202011009910010000101001000000100200431813357198701006710009013534552005313393413214213101161169856204189920000201007007070070700707007070070
402047006952522220000510510341014367005433510858663254051020480200002010020000204497933215611103496698907002970069645073650274010020200200003020040000700696411202011009910010000101001000001100200561718647198721008110010124112552003913693118615013101161169856202709920000201007007070070700707007070070
4020470069525242200005072938101407005427515235768225405992026520000201002000020451683321607114949669890700297006964507365027401002020020000302004000070069671120201100991001000010100100000010020077151135619872100631000904474250200561399349615413101161169856202599920000201007007070070700577007070070
40204700695242220000050629271090700542558105840125405842054020000201002000020443173321694116349669890700297006964507365027401002020020000302004000070072651120201100991001000010100100000010020041197851198721007510009234910512004513393416915013101161169843205429020000201007007070057700707007070057
4020470069525202200005060915103070054051112576442540313203352000020100200002044791332199211164966989070029700566450736502740100202002000030200400007006967112020110099100100001010010000001002004719964219872100741000944292260200571359499615013101161169856202539920000201007007070070700707007070070

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0069

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0f18191e1f2022233a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9aaabacafb6bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
40026700695250000010505916610141270054435131558676254052520250200002001020000204423533212230290496698970029700696497036683740010200202000030020400007006961512002110901010000100101000001020046017953198721005910002604630332006402114010600012702165471782202346020000200107006470070700707005170064
4002470069525000000050491000160700483541311585152540222205612000020010200002044140332088901554966970700107006964529365043400102002020000300204000070069611120021109351101000010010100000102003612126271986610051100091036384520091023840127131012702164269856202339920000200107007070070700707007070070
4002470069525110100050578211018070041194910579552540286203752000020010200002043956332118602114966989700167006964529365036400102002020000300204000070069671120021109010100001001010000010200501558231987210075100082040304920073223840145132012705164569856202479920000200107007070070700707007070070
4002470069524140100050458391092870054245965819738402232038020000200102000020442023320985112049669897002970069645293650364001020020200003002040000700566411200211090101000010010100000102005816114441987010080100172134386820129134815126140012704164469843202019920000200107007070070700707007070070
400247006952500000005069132101347005423510185837625402152018620000200102000020445423321225012749669897002970069645293650404001020020200003002040000700696111200211090101000010010100001102004301055119870100581006000423031200560192279000012704164469856203706620000200107007070070700707007070070
400247006952400000105049122101507054332413758767254053620502200002001020138204461633210371133496698970023705746452936504940010200202000030020400007006957112002110901010000100101000001020044011135198721005310061214240302007502903821300012702244269856202390620000200107007070070700707006470567
40024700505241011000506683210172870041245810577822540557204082000020010200002043482331987901134966989700337006964529365049400102002020000300204000070069651120021109010100001001010000010200502821954198721008210008117312542006402713212700012704164469856202456620000200107007070051700707006470070
400247006952500000005043191011070551243111459015254015920385200002001020000204418933217631142496697070033700506452936504940010200202000030020400007006961112002110901010000100101000001020044010535198701005710001613746232007713583177130012702165469856203559920000200107007070070700707056470070
4002470069524110100050567400016070054355146573922540503205672000020010200002044556334397111994966989700297006964529365049400102002020000300204000070069651120021109010100001001010000010200521311523198721006510008324836572011801873577130012902164469843201569920000200107007070070700707007070070
400247005652511110005070821101212700542451095811525402952048320000200102000020442173321555112249669767002970056645291265049400102002020000300204000070069671120021109010100001001010000010200541515045198721004910007723538362007013683794131212705165469856205589920000200107057770070700707007070070

Test 3: throughput

Code:

  staddlb w0, [x6]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 22.0127

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)0e0f18191e1f22243a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)797bmap int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acafbbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd1d5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
3020522022016490000000268941101220112307202164255072227939227701010020000859248610527286047049217051322015122014521539562163433010016512004102032000520206400092201198781110201100991001000010010000110020000302027685100000163803725617380002711171610233116112194151612754510002000010100220112220164220125220135220136
3020422011516491010000270221100220103312102021172550833274892359210100200008521914105273901574492170770220089220133215413621637330100168021211020320005202064000922015017441110201100991001000010010000010020000290271461000061773637200173820122911171610208116112194321602728610602000010100220111220121220120220125220163
3020422117216562010100274510001220103311020205125507522746222799101002000085592851065307505044921704302200942200892154627216331301002263216910203200052020640009220105944111020110099100100001001000001002000027162755010001017119372901700910301117161083311611219395177278356602000010100220158220134220128220112220112
302042201151649101000027615000122011220020196925505792779523054101002000086074801052935504994921701902201432201532154686216354301002038160510203200052029640009220133900111020110099100100001001000001002000030192714410000016801368071708011601117161040911611219397303267676602000010100220119220104220151220090220141
302042201141649101000027111100022013109112025282550850276892304310100200008456743105235350557492140280220129220123215483621631830100212221841020320005202064000922013784811102011009910010000100100000100200002718268181000001699637138173191001117161031311611219423123273450902000010100220160220140220182220110220132
3020422012316491010000277631000220122211020207825506722766423082101002000083753211052946404724921702302201192200932154226216354301001837171910203200982020640009220148944111020110099100100001001000001002000000266531000101689637295171270001117161055411611219415199274600602000010100220130220116220142220143220162
3020422009616491010000275180001220100311020236725506962740623497101002000084128561052753905554921704502201452201212154136216353302131983198910203200052020640009220123878111020210099100100001001000001002000027192656310001016771374681688312027111716982511611219486204272700602000010100220112220115220133220098220108
302042201271649101000027301110122012040112019531135087827686233261030320285857254310527667050449217068022013522014321537662163333010016691596102032000520206400092201378781110201100991001000010010000110020000290271931000031694137455177790163011171610418116112193831682725901002000010100220114220138220120220122220140
30204220093164810100002721111002200900802022342550490273032313810100200008567537105239890481492170440220136220149215385621634730100201318791020320005202064000922014492811102011009910010000100100000100200000182722610001016395369171674110311117161088911611219365130270579902000010100220116220127220134220132220122
302042201251649101110026957000022008200720198325507742731623138101002000082850061052421215534921706302201672201212154116216291301001698204210203200052020640009220116860111020110099100100001001000001002000030182747810000117239375481745411901117161051911611219451208272419602000010100220128220122220127220100220116

1000 unrolls and 10 iterations

Result (median cycles for code): 22.0257

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f1e1f22243a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)797bmap int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acafbbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)branch mispred nonspec (cb)cfd1d5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
3002522015216490000031679110022024201282016102552850327912007710010200001062706010524813013504921721002203062202862154053216498300101331301002020000200204000022026071311100211094585510100001010000110200262629533148710000421430415262148613431064015258216222193541328551302000010010220236220272220180220297220265
300242202521650111003160115003220223001820105725528123280220089100102000010667932105257050137749217199022025522025121534032165103001015215310020201102002040000220241720111002110954263101000010100000102000003535315481000102160541567215450340064015317216222194101329520102000010010220228220303220296220230220266
300242202211650000003152901012202501072013332552813327902008010010200001063597010525315113404921716302202632202932154113216459300101251271002020000200204000022028972811100211096134610100001010000010200000350315711000142159141508214771035064015237216222194333327201302000010010220329220270220265220281220278
300242202901649000003143411002202550101020142225531473275020071100102000010632425105246551131449217172022031022027621538132164753001011812610020200002002040000220219662111002110965650101000010100000102000000353160810001321612416722147513435064015210216222193335327360102000010010220268220192220348220248220310
30024220279165000000314621001220274070201115255293932834200651001020000106944301052454911372492171150220217220237215326321647130010117112100202000020020400002202876621110021109607111010000101000001020000035373149810001221506414982149413535064015336216212194381327770102000010010220238220186220238220294220256
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