Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ORR (register, ror, 32-bit)

Test 1: uops

Code:

  orr w0, w0, w1, ror #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03mmu table walk instruction (07)1e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100420351500061100017352520002000100032570020352035157531842100010002000203542111001100000732671117812000100020362036203620362036
100420351600061100017352520002000100032570020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
100420351500061100017352520002000100032570020352035157731842100010002000203542111001100003731671117812000100020362036203620362036
100420351506061100017352520002000100032570020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
100420351500061100017352520002000100032570020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
100420351501328861100017352520002000100032570020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
100420351500061100017352520002000100032570020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
100420351500061100017352520002000100032570020352035157531842100010002000203542111001100000751671117812000100020362036203620362036
100420351600061100017352520002000100032570020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
100420351500061100017352520002000100032570020352035157531842100010002000203542111001100000731671117812000100020362036203620362036

Test 2: Latency 1->2

Code:

  orr w0, w0, w1, ror #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102042003515027611000019803252010020100101001889711491695520035200351843031870010100102002020020035421110201100991001010010001300710159111979120000101002003620036200362008220036
1020420035150061100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000000710159111979120000101002003620036200362003620036
1020420035150061100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000000710159111979120000101002003620036200362003620036
1020420035150061100001980325201002010010100185342049169552003520035184293187001010010200202002003542111020110099100101001000000710159111979120000101002003620036200362003620036
1020420035150061100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000000710159111979120000101002003620036200362003620036
1020420035150061100001980325201002010010100185342049169552003520035184293187001010010200202002003542111020110099100101001000030710159111979120000101002003620036200362003620036
1020420035150061100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000000710159111979120000101002003620036200362003620036
1020420035150061100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000001710159111979120000101002003620036200362003620036
1020420035150061100001980325201002010010100185342049169552003520035184293187001010010200202002003542111020110099100101001000000710159111979120000101002003620036200362003620036
1020420035150061100001980325201002010010100185342049169552003520035184293187001010010200202002003542111020110099100101001000000710359111979120000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03181e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6061696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024200351500156110000197432520010200101001018531005491695520035200351845131871810010100202002020035421110021109101001010006400263221979220000100102003620036200362003620036
1002420035150006110000197432520010200101001018531010491695520035200351845131871810010100202002020035421110021109101001010106405263221979220000100102003620036200362003620036
1002420035150006110000197432520010200101001018531005491695520035200351845131871810156100202103620035421110021109101001010006400267221979220024100102003620036200362003620036
10024200351500014910000197432520010200101001018531005491695520035200351845131871810010100202002020035421110021109101001010006400263221979220000100102003620036200362003620036
1002420035150096110000197432520010200101001018531000491695520035200351845131871810010100202002020035421110021109101001010006400263221979220000100102003620036200362003620036
1002420035150006110000197432520010200101001018531000491695520035200351845131871810010100202002020035421110021109101001010006400263221979220045100102003620036200362003620036
1002420035150406110000197432520010200101001018531010491695520035200351845131871810010100202002020035421110021109101001010006720263221979220000100102003620036200362003620036
1002420035150006110000197432520010200101001018531005491695520035200351845131871810010100202002020035421110021109101001010006405263221979220000100102003620036200362003620036
1002420035150006110000197432520010200101001018531010491695520080200351845131871810010100202002020035421110021109101001010006400263221979220000100102003620036200362003620036
1002420035150006110000197432520010200101001018531005491695520035200351845131871810010100202002020035421110021109101001010006405263221979220000100102003620036200362003620036

Test 3: Latency 1->3

Code:

  orr w0, w1, w0, ror #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204200351500611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000710159121979120000101002003620036200362003620036
10204200351500611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000710159111979120000101002003620036200362003620036
1020420035150171611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000710159111979120000101002003620036200362003620036
10204200351500611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000710159111979120000101002003620036200362003620036
10204200351500611000019803252010020100101001853420491695520035200351842931870010100102002020020035421110201100991001010010000710159111979120000101002003620036200362003620036
1020420035150246611000019803252010020100101001853420491695520035200351842931870010100102002020020035421110201100991001010010000710159111979120000101002003620036200362003620036
1020420035150219611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000710159111979120000101002003620036200362003620036
10204200351500611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000710159111979120000101002003620036200362003620036
10204200351500611000019803252010020100101001853420491695520035200351842931870010100102002020020035421110201100991001010010000710159111979120000101002003620036200362003620036
10204200351500611000019803252010020100101001853420491695520035200351843531870010100102002020020035421110201100991001010010000710159111979120000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100242003515001121000019743252001020010100101853100491695520035200351845131871810010100202002020035421110021109101001010000640263221979220000100102003620036200362003620036
1002420035150156771000019743252001020010100101853100491695520035200351845131871810010100202002020035421110021109101001010000640263221979220000100102003620036200362003620036
10024200351500841000019743252001020010100101853100491695520035200351845131871810010100202002020035421110021109101001010000640263221979220000100102003620036200362003620036
10024200351500611000019743252001020010100101853100491695520035200351845131871810010100202002020035421110021109101001010000640263221979220000100102003620036200362003620036
10024200351506611000019743252001020010100101853100491695520035200351845131871810010100202002020035421110021109101001010000640263221979220000100102003620036200362003620036
10024200351500611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010000640263221979220000100102003620036200362003620036
100242003515005361000019743252001020010100101853100491695520035200351845131871810010100202002020035421110021109101001010000640263221979220000100102003620036200362003620036
10024200351500611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010000640263221979220000100102003620036200362003620036
10024200351500611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010000640263221979220000100102003620036200362003620036
10024200351500611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010000640263221979220000100102003620036200362003620036

Test 4: throughput

Count: 8

Code:

  orr w0, w8, w9, ror #17
  orr w1, w8, w9, ror #17
  orr w2, w8, w9, ror #17
  orr w3, w8, w9, ror #17
  orr w4, w8, w9, ror #17
  orr w5, w8, w9, ror #17
  orr w6, w8, w9, ror #17
  orr w7, w8, w9, ror #17
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

retire uop (01)cycle (02)03mmu table walk instruction (07)1e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8020426767201006180000260942516010016010080100164318049236452672526725166153166778010080200160200267253911802011009910080100100000051104222226717160000801002672626726267262672626726
8020426725200006180000260942516010016010080100164318049236452672526725166153166778010080200160200267253911802011009910080100100000051102222226717160000801002672626726267262672626726
8020426725200006180000260942516010016010080100164318049236452672526784166153166778010080200160200267253911802011009910080100100000051102222226717160000801002672626726267262672626726
8020426725200006180000260942516010016010080100164318049236452672526725166153166778010080200160200267253911802011009910080100100000051102222226717160000801002672626726267262672626726
8020426725200006180000260942516010016010080100164318049236452672526725166153166778010080200160200267253911802011009910080100100000051102222226717160000801002672626726267262672626726
8020426725200006180000260942516010016010080100164318049236452672526725166153166778010080200160200267253911802011009910080100100000051102222226717160000801002672626726267262672626726
8020426725200006180000260942516010016010080100164318049236452672526725166153166778010080200160200267253911802011009910080100100000051102222226717160000801002672626726267262672626726
8020426725201006180000260942516010016010080100164318049236452672526725166153166778010080200160200267253911802011009910080100100000051102222226717160000801002672626726267262672626726
8020426725200006180000260942516010016010080100164318049236452672526725166153166778010080200160200267253911802011009910080100100000051102222226717160000801002672626726267262672626726
8020426725201006180000260942516010016010080100164318049236452672526725166153166778010080200160200267253911802011009910080100100000051102222226717160000801002672626726267262672626726

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)5f60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9cfd2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80024267172000618000021280251600101600108001016314201492363126711267111662331668580010800201600202671139118002110910800101000502005013220151426704160000800102671226712267122671226712
80024267112000618000021280251600101600108001016314201492363126711267111662331668580010800201600202671139118002110910800101000502005012220151626704160000800102671226712267122671226712
800242671120012618000021280251600101600108001016314201492363126711267111662331668580010800201600202671139118002110910800101000502005015220151226704160000800102671226712267122671226712
8002426711200061800002128025160010160010800101631420149236312671126711166233166858001080020160020267113911800211091080010100050200501522091526704160000800102671226712267122671226712
800242671119901458000021280251600101600108001016314201492363126711267111662331668580010800201600202671139118002110910800101000502005014220131726704160000800102671226712267122671226712
80024267111996618000021280251600101600108001016314201492363126711267111662331668580010800201600202671139118002110910800101000502005015220111526704160000800102671226712267122671226712
80024267112000618000021280251600101600108001016314201492363126711267111662331668580010800201600202671139118002110910800101000502005015220111526704160000800102671226712267122671226712
80024267111990618000021280251600101600108001016314201492363126711267111662331668580010800201600202671139118002110910800101000502005011220101726704160000800102671226712267122671226712
80024267112000618000021280251600101600108001016314201492363126711267111662331668580010800201600202671139118002110910800101000502005014220161326704160000800102671226712267122671226712
80024267112000618000021280251600101600108001016314201492363126711267111662331668580010800201600202671139118002110910800101000502005011220141426704160000800102671226712267122671226712