Firestorm: DMB (ST) measurements

Code:

  dmb st

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst barrier (9c)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	3035	23	0	0	3011	2009	1000	1000	1000	6000	42	3027	3035	3	2884	1000	1000	3027	3035	1	1	1001	1000	1000	6	0	0	73	2	16	2	2	3024	1000	3036	3028	3036	3027	3036
1004	3035	22	0	0	3012	2009	1000	1000	1000	6000	42	3035	3026	3	2885	1000	1000	3026	3035	1	1	1001	1000	1000	0	0	0	73	2	16	2	2	3023	1000	3036	3028	3036	3028	3036
1004	3035	22	0	0	3020	2001	1000	1000	1000	6000	42	3035	3027	3	2884	1000	1000	3027	3035	1	1	1001	1000	1000	4	0	0	73	2	16	2	2	3022	1000	3028	3036	3028	3036	3027
1004	3026	22	0	0	3020	2009	1000	1000	1000	6000	33	3027	3035	3	2893	1000	1000	3035	3026	1	1	1001	1000	1000	5	0	0	73	2	16	2	2	3032	1000	3028	3036	3028	3036	3027
1004	3026	22	0	0	3020	2009	1000	1000	1000	6000	42	3035	3027	3	2885	1000	1000	3027	3035	1	1	1001	1000	1000	4	0	0	73	2	16	2	2	3032	1000	3027	3036	3027	3036	3027
1004	3026	22	0	0	3020	2009	1000	1000	1000	6000	34	3026	3035	3	2884	1000	1000	3027	3035	1	1	1001	1000	1000	0	0	0	73	2	16	2	2	3032	1000	3028	3036	3027	3036	3036
1004	3035	23	0	0	3020	2001	1000	1000	1000	6000	42	3035	3026	3	2885	1000	1000	3026	3035	1	1	1001	1000	1000	0	0	0	73	2	16	2	2	3032	1000	3028	3036	3028	3036	3027
1004	3026	23	0	15	3020	2009	1000	1000	1000	6000	34	3027	3035	3	2893	1000	1000	3035	3025	1	1	1001	1000	1000	0	0	0	73	2	16	2	2	3024	1000	3036	3028	3036	3028	3036
1004	3035	23	0	0	3011	2009	1000	1000	1000	6000	34	3027	3035	3	2893	1000	1000	3035	3026	1	1	1001	1000	1000	0	0	0	73	2	16	2	2	3024	1000	3036	3028	3036	3028	3026
1004	3025	23	0	0	3011	2001	1000	1000	1000	6000	34	3026	3035	3	2893	1000	1000	3035	3026	1	1	1001	1000	1000	0	0	0	73	2	16	2	2	3032	1000	3028	3036	3028	3036	3036

Code:

  dmb st

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.9044

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst barrier (9c)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10204	29028	218	0	0	0	0	29028	18906	10100	100	10000	100	10000	500	59800	1	49	26528	29025	29135	6	27732	10100	200	10000	200	29025	23295	1	1	10201	100	99	100	100	10000	100	0	0	10000	6	18	1	1	1	717	0	16	0	0	29132	10000	100	29045	29136	29044	29136	29136
10204	29135	218	0	0	0	0	29120	18916	10100	100	10014	125	10000	500	59800	0	49	25955	29135	29027	3	27742	10100	200	10000	200	29035	23295	1	1	10201	100	99	100	100	10000	100	0	0	10000	0	99	0	0	0	710	1	16	1	1	29132	10000	100	29136	29043	29136	29044	29136
10204	29135	218	0	0	0	0	29029	19008	10100	100	10000	100	10000	500	59800	0	49	26055	29042	29135	3	27843	10100	200	10000	200	29135	23216	1	1	10201	100	99	100	100	10000	100	0	0	10000	0	126	0	0	0	710	1	16	1	1	29132	10000	100	29136	29026	29136	29036	29044
10204	29043	219	0	0	0	0	29029	18900	10100	100	10000	100	10000	500	59800	0	49	26055	29035	29135	3	27843	10100	200	10000	200	29135	23222	1	1	10201	100	99	100	100	10000	100	0	0	10000	1	0	0	0	0	710	1	16	1	1	29040	10000	100	29136	29035	29136	29136	29036
10204	29035	219	0	0	0	0	29120	19008	10100	100	10000	100	10000	500	59800	0	49	25963	29135	29035	3	27843	10100	200	10000	200	29135	23216	1	1	10201	100	99	100	100	10000	100	0	0	10000	1	0	0	0	0	710	1	16	1	1	29132	10000	100	29045	29136	29136	29136	29036
10204	29035	218	0	0	0	0	29021	18899	10100	100	10000	100	10000	500	59800	0	49	26055	29025	29135	3	27843	10100	200	10000	200	29135	23223	1	1	10201	100	99	100	100	10000	100	0	0	10000	31	3	0	0	0	710	1	16	1	1	29132	10000	100	29044	29136	29136	29136	29028
10204	29027	218	0	0	0	0	29120	18908	10100	100	10000	100	10000	500	59800	0	49	25962	29135	29043	3	27742	10100	200	10000	200	29035	23295	1	1	10201	100	99	100	100	10000	100	0	0	10000	0	3	0	0	0	710	1	16	1	1	29132	10000	100	29136	29029	29026	29044	29136
10204	29135	217	0	0	0	0	29012	18975	10100	100	10000	100	10000	500	59800	0	49	25948	29135	29034	3	27752	10100	200	10000	200	29042	23295	1	1	10201	100	99	100	100	10000	100	0	0	10000	44	2158	0	0	0	710	1	16	1	1	29033	10000	100	29136	29044	29036	29044	29136
10204	29135	217	0	0	0	0	29120	18908	10100	100	10000	100	10000	500	59800	0	49	26055	29035	29135	3	27743	10100	200	10000	200	29036	23295	1	1	10201	100	99	100	100	10000	100	0	0	10000	40	6	0	0	0	710	1	16	1	1	29032	10000	100	29136	29035	29136	29136	29044
10204	29043	218	0	0	0	0	29120	19008	10100	100	10000	100	10000	500	59800	0	49	25954	29135	29043	3	27751	10100	200	10000	200	29261	29347	1	1	10201	100	99	100	100	10000	100	0	0	10000	39	3	0	0	0	710	1	16	1	1	29132	10000	100	29044	29136	29136	29136	29035

1000 unrolls and 10 iterations

Result (median cycles for code): 2.9951

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst barrier (9c)	9f	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10024	29867	224	0	29936	19831	10010	10	10000	10	10000	50	59982	0	49	26787	29897	29867	3	28681	10010	20	10000	20	29951	29867	1	1	10021	10	9	10	10	10000	10	0	10000	0	0	0	640	5	16	5	5	29948	10000	10	29952	29868	29952	29866	29952
10024	29951	224	0	29851	19915	10010	10	10000	10	10000	50	59982	0	49	26787	29951	29867	3	28597	10010	20	10000	20	29866	29951	1	1	10021	10	9	10	10	10000	10	0	10000	0	0	0	640	5	16	5	5	29948	10000	10	29952	29868	29952	29868	29952
10024	29951	224	0	29936	19829	10010	10	10000	10	10000	50	59982	0	49	26871	29865	29951	3	28681	10010	20	10000	20	29951	29866	1	1	10021	10	9	10	10	10000	10	0	10000	0	0	0	640	4	16	4	5	29948	10000	10	29952	29866	29952	29867	29952
10024	29951	223	0	29851	19915	10010	10	10000	10	10000	50	59982	1	49	26871	29867	29951	3	28681	10010	20	10000	20	29951	29867	1	1	10021	10	9	10	10	10000	10	0	10000	0	0	0	640	4	16	4	5	29862	10000	10	29952	29868	29952	29868	29952
10024	29951	223	0	29852	19915	10010	10	10000	10	10000	50	59982	1	49	26787	29951	29867	3	28596	10010	20	10000	20	29866	29951	1	1	10021	10	9	10	10	10000	10	0	10000	0	0	0	640	4	16	4	4	29948	10000	10	29868	29952	29868	29865	29952
10024	29951	223	0	29852	19915	10010	10	10000	10	10000	50	59982	1	49	26787	29951	29867	3	28681	10010	20	10000	20	29951	29867	1	1	10021	10	9	10	10	10000	10	0	10000	0	0	0	640	3	16	4	4	29948	10000	10	29952	29891	29868	29952	29867
10024	29866	224	0	29936	19829	10010	10	10000	10	10000	50	59982	1	49	26871	29867	29951	3	28681	10010	20	10000	20	29951	29865	1	1	10021	10	9	10	10	10000	10	0	10000	0	0	0	640	5	16	5	5	29864	10000	10	29865	29952	29867	29952	29868
10024	29867	224	0	29852	19829	10010	10	10000	10	10000	50	59982	1	49	26871	29867	29951	3	28681	10010	20	10000	20	29951	29865	1	1	10021	10	9	10	10	10000	10	0	10000	0	0	0	640	5	16	4	4	29862	10000	10	29952	29866	29952	29865	29952
10024	29951	224	0	29852	19915	10010	10	10000	10	10000	50	59982	1	49	26871	29865	29951	3	28681	10010	20	10000	20	29951	29866	1	1	10021	10	9	10	10	10000	10	0	10000	0	0	0	640	3	16	4	3	29948	10000	10	29952	29866	29952	29865	29952
10024	29951	223	0	29936	19915	10010	10	10000	10	10000	50	59982	1	49	26786	29951	29865	3	28597	10010	20	10000	20	29864	29951	1	1	10021	10	9	10	10	10000	10	0	10000	0	0	0	640	4	16	3	4	29862	10000	10	29867	29952	29868	29952	29867

DMB (ST)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations