Firestorm: LDRSH (register, sxtw, 64-bit) measurements

Code:

  ldrsh x0, [x6, w7, sxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	389	3	1	1	41	1	0	1	383	2	18	12	12	25	1000	1000	1000	14838	1	389	389	216	3	247	1000	1000	2000	389	71	1	1	1001	1000	1000	0	1000	39	1035	0	39	1039	6	1	35	39	73	2	16	1	1	386	10	6	4	1000	390	395	395	395	395
1004	394	3	0	0	46	1	0	2	379	2	18	18	12	25	1000	1000	1000	14838	0	394	394	217	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	39	1035	0	39	1035	6	1	35	39	73	1	16	1	1	386	6	6	2	1000	390	390	390	395	390
1004	389	3	0	0	41	0	0	2	379	2	18	18	16	25	1000	1000	1000	14838	1	389	389	216	3	247	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	39	1035	0	35	1035	6	1	35	39	73	1	16	1	1	386	10	10	2	1000	390	395	390	395	395
1004	389	3	0	0	45	0	0	1	379	2	18	18	12	25	1000	1000	1000	15018	1	394	389	216	3	247	1000	1000	2000	389	71	1	1	1001	1000	1000	0	1000	39	1039	0	39	1036	6	1	35	43	73	1	16	1	1	386	10	6	2	1000	390	390	395	390	395
1004	389	3	0	0	45	1	0	2	374	2	18	12	16	25	1000	1000	1000	14989	1	391	394	217	3	247	1000	1000	2000	389	71	1	1	1001	1000	1000	0	1000	39	1039	0	35	1039	6	1	35	43	73	1	16	1	1	388	6	6	2	1000	392	390	390	395	395
1004	394	2	0	0	45	0	0	1	374	2	12	12	16	25	1000	1000	1000	14838	1	389	394	217	3	247	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	39	1035	0	35	1039	6	1	35	43	73	1	16	1	1	391	10	6	2	1000	398	390	395	395	390
1004	389	3	0	0	41	0	0	1	379	2	18	12	13	25	1000	1000	1000	15018	0	394	391	216	3	252	1000	1000	2000	391	71	1	1	1001	1000	1000	0	1000	39	1035	0	39	1035	6	1	35	39	73	1	16	1	1	402	6	6	2	1000	395	395	390	390	390
1004	394	3	0	0	41	1	0	1	379	2	18	12	12	25	1000	1000	1000	15018	0	389	389	212	3	247	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	39	1035	0	39	1035	6	1	35	39	73	1	16	1	1	386	6	6	2	1000	395	392	395	395	398
1004	389	3	0	0	41	1	0	1	374	2	18	18	12	25	1000	1000	1000	14838	0	391	389	212	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	39	1039	0	39	1039	6	1	36	43	73	1	16	1	1	386	10	6	2	1000	390	395	395	390	390
1004	389	3	0	0	41	0	0	1	379	2	18	18	11	25	1000	1000	1000	14989	1	391	394	212	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	39	1039	0	35	1039	6	1	35	39	73	1	16	1	1	391	10	6	2	1000	390	390	392	390	391

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh x0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70041	525	0	0	0	0	0	2	2	1	0	0	70020	69764	59709	25	40100	30103	10001	30100	10000	616005	3342206	1	49	66970	70035	70050	64646	0	3	64953	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	0	10000	1	1	0	1	0	0	2610	1	71	1	1	69819	30006	0	6	9	10000	30100	70057	70062	70057	70042	70057
40204	70041	525	1	0	1	0	1	0	1	0	0	0	70035	69781	59695	25	40104	30100	10001	30100	10000	616175	3342206	1	49	66970	70050	70035	64631	0	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69804	30006	9	6	9	10000	30100	70057	70054	70042	70042	70057
40204	70053	525	1	0	1	1	0	0	1	0	0	0	70020	69781	59695	25	40100	30100	10001	30100	10000	616175	3342206	1	49	66970	70050	70050	64631	0	3	64953	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	1	0	0	10000	0	0	0	0	0	0	2610	1	71	1	1	69813	30003	6	6	6	10000	30100	70036	70048	70049	70048	70048
40204	70047	524	0	0	0	0	0	0	1	1	0	0	70021	69764	59709	25	40100	30103	10001	30100	10000	616005	3342206	1	49	66970	70035	70050	64631	0	3	64938	40100	30200	10000	60200	20000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	1	10002	0	0	1	1	10000	1	0	0	0	0	0	2610	1	71	1	1	69813	30003	0	6	9	10000	30100	70051	70051	70051	70051	70036
40204	70050	524	0	0	0	0	0	0	1	0	0	0	70020	69735	59709	25	40104	30103	10001	30100	10000	616005	3341470	1	49	66955	70112	70056	64643	0	3	64938	40313	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69798	30003	0	6	0	10000	30100	70051	70051	70051	70048	70051
40204	70035	525	0	1	0	0	0	0	1	0	0	0	70020	69787	59701	25	40108	30100	10001	30100	10000	616175	3342350	1	49	66970	70050	70050	64631	0	3	64938	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69820	30000	0	6	9	10000	30100	70050	70036	70051	70036	70051
40204	70035	524	0	0	0	0	0	0	1	0	0	0	70035	69702	59715	25	40104	30103	10001	30100	10000	616175	3342062	1	49	66970	70050	70050	64631	0	3	64953	40100	30200	10000	60200	20000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	1	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69813	30003	9	9	9	10000	30100	70051	70051	70036	70052	70051
40204	70035	525	0	0	0	0	0	0	672	0	0	0	70032	69781	59712	25	40104	30103	10001	30100	10000	616005	3342206	1	49	66970	70050	70047	64646	0	3	64938	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	0	0	0	0	2610	1	71	1	1	69810	30003	9	0	0	10000	30100	70051	70051	70051	70051	70051
40204	70047	525	0	0	0	0	0	0	6	0	1	0	70035	69764	59709	25	40104	30103	10000	30100	10000	616015	3342062	1	49	66970	70050	70050	64651	0	3	64938	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	0	10000	1	1	0	1	0	0	2610	1	71	1	1	69816	30003	9	9	9	10000	30100	70036	70051	70036	70048	70036
40204	70050	524	0	0	0	0	0	1	1	0	0	0	70032	69781	59706	38	40100	30100	10001	30100	10000	616005	3341470	1	49	66955	70035	70047	64646	0	3	64950	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	1	1	10000	1	0	1	0	0	0	2610	1	71	1	1	69798	30003	9	9	0	10000	30100	70051	70051	70051	70051	70051

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	525	0	0	1	0	0	70032	69728	59706	25	40014	30013	10002	30010	10000	616952	3342062	0	49	66967	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	2520	1	71	1	1	69812	30003	6	6	6	10000	30010	70048	70048	70048	70048	70048
40024	70047	524	0	0	1	1	0	70032	69728	59706	25	40014	30013	10001	30010	10000	616952	3342062	0	49	66967	70047	70047	64665	24	64972	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	10000	1	1	0	2520	1	71	1	1	69876	30003	6	6	6	10000	30010	70048	70048	70048	70048	70048
40024	70047	524	0	0	1	1	0	70032	69728	59706	25	40014	30013	10001	30010	10000	616952	3342062	0	49	66967	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	2520	1	71	1	1	69854	30003	6	6	6	10000	30010	70048	70048	70048	70048	70048
40024	70047	524	0	0	6	1	0	70032	69728	59706	25	40014	30013	10001	30010	10000	616952	3342062	0	49	66967	70050	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	10000	1	1	0	2520	1	71	1	2	69814	30003	6	6	6	10000	30010	70054	70048	70048	70048	70058
40024	70047	525	0	1	1	1	0	70032	69728	59706	25	40010	30013	10001	30010	10000	616952	3344938	0	49	66967	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	2520	1	71	1	2	69813	30003	6	6	6	10000	30010	70048	70048	70048	70048	70048
40024	70047	525	0	0	0	1	0	70032	69728	59706	25	40014	30013	10001	30010	10000	616952	3342062	0	49	66967	70047	70047	64653	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	1	0	10000	1	1	0	2520	1	71	1	2	69836	30000	6	6	6	10000	30010	70048	70048	70036	70048	70048
40024	70047	524	0	1	1	1	0	70032	69728	59706	25	40014	30013	10001	30010	10000	616952	3342062	0	49	66967	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10003	7	0	10000	1	1	0	2520	2	71	1	2	69867	30003	6	6	6	10000	30010	70048	70048	70048	70048	70048
40024	70035	524	0	0	1	1	0	70032	69728	59706	25	40014	30013	10001	30010	10000	616952	3342062	0	49	66967	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	1	2520	1	71	1	2	69836	30003	6	0	6	10000	30010	70048	70048	70048	70036	70048
40024	70047	525	0	0	1	1	0	70032	69728	59706	25	40014	30013	10001	30010	10000	616952	3342062	0	49	66967	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	2520	1	71	1	1	69861	30003	6	6	6	10000	30010	70108	70049	70057	70048	70036
40024	70049	525	0	0	1	1	0	70032	69728	59706	25	40014	30013	10001	30010	10000	616952	3342062	0	49	66967	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	10000	1	1	0	2520	1	71	1	2	69812	30003	6	6	6	10000	30010	70048	70048	70054	70048	70048

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh x0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0057

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	19	1e	22	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70057	525	1	1	1	1	1	0	0	2	1	1	70026	69792	59716	25	40108	30106	10002	30100	10000	616068	3342542	49	66977	0	70057	70057	64653	3	64960	40100	30200	10000	60200	20000	70058	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10003	1	1	10002	0	1	1	10000	1	1	1	1	2	0	2610	1	71	1	1	69820	30006	10	10	10	10000	30100	70058	70058	70058	70058	70058
40204	70057	525	1	0	0	1	0	1	0	2	1	1	70042	69788	59716	25	40108	30106	10002	30100	10000	616068	3342542	49	66977	0	70057	70057	64653	3	64961	40100	30200	10000	60200	20000	70118	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10003	0	1	1	10000	1	1	1	1	1	0	2610	1	71	1	1	69820	30006	10	10	10	10000	30100	70058	70042	70058	70058	70058
40204	70057	525	1	1	1	1	0	0	0	2	0	1	70042	69788	59716	25	40104	30106	10002	30100	10000	616068	3342542	49	66980	0	70057	70057	64659	3	64960	40100	30200	10000	60200	20000	70106	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10003	0	1	1	10000	1	1	1	1	0	0	2610	1	71	1	1	69820	30003	10	10	10	10000	30100	70058	70058	70058	70058	70058
40204	70057	525	1	0	0	1	0	0	0	29	1	1	70042	69788	59716	25	40108	30106	10002	30100	10000	616068	3342542	49	66977	0	70057	70041	64653	3	64960	40100	30200	10000	60200	20000	70105	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	0	10002	0	0	1	10000	1	1	1	1	0	0	2610	1	71	1	1	69820	30006	10	10	10	10000	30100	70058	70058	70058	70058	70058
40204	70057	525	1	1	1	0	0	0	0	2	1	1	70042	69788	59716	25	40108	30115	10002	30100	10000	616068	3342542	49	66977	0	70061	70057	64653	3	64964	40100	30200	10000	60200	20000	70105	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10002	0	1	1	10000	1	1	1	1	0	0	2610	1	71	1	1	69820	30006	10	10	10	10000	30100	70058	70058	70058	70058	70058
40204	70057	524	1	1	1	1	0	0	0	2	1	1	70042	69788	59716	25	40108	30106	10002	30100	10000	616068	3342542	49	66977	0	70495	70057	64653	3	65326	40100	30200	10000	60200	20000	70094	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10002	0	0	1	10000	0	1	1	1	1	0	2610	1	71	1	1	69820	30006	10	10	10	10000	30100	70058	70058	70058	70058	70058
40204	70057	525	1	0	0	1	0	0	0	2	1	0	70042	69788	59716	25	40108	30106	10002	30100	10000	616068	3342542	49	66977	0	70041	70057	64653	3	64960	40100	30200	10000	60200	20000	70087	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	1	10001	0	0	1	10000	1	1	1	1	2	0	2610	1	71	1	1	69820	30006	10	10	0	10000	30100	70058	70058	70058	70058	70058
40204	70057	524	1	1	1	2	0	0	0	5	1	1	70042	69788	59716	25	40108	30106	10002	30100	10000	616068	3342542	49	66977	0	70057	70057	64653	3	64960	40100	30200	10000	60200	20000	70060	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	1	10001	0	0	1	10000	1	1	1	1	1	0	2610	1	71	1	1	69820	30006	10	10	10	10000	30100	70058	70058	70042	70058	70058
40204	70057	524	1	0	1	1	0	0	0	2	1	1	70042	69788	59716	25	40108	30106	10002	30100	10000	616068	3342542	49	66977	0	70057	70057	64653	3	64960	40100	30200	10000	60200	20000	70059	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10002	0	0	1	10000	1	1	1	1	0	0	2610	1	71	1	1	69820	30006	10	10	10	10000	30100	70058	70058	70058	70058	70058
40204	70057	525	1	0	1	1	0	0	0	2	1	1	70042	69788	59716	25	40104	30106	10002	30100	10000	616068	3342542	49	66977	0	70057	70057	64653	3	64960	40100	30200	10000	60200	20000	70104	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10001	2	1	10001	0	2	160	10000	1	1	1	1	1	0	2610	1	71	1	1	69820	30006	10	10	10	10000	30100	70058	70058	70058	70058	70058

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	0f	1e	1f	22	23	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cd	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	525	0	0	1	0	0	0	0	70035	69728	59709	25	40014	30010	10001	30010	10000	616982	3342062	0	49	66967	70050	70035	64665	0	3	64972	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	0	10000	1	1	0	0	2520	0	1	71	2	1	1	69810	30003	9	6	0	10000	30010	70036	70051	70051	70051	70051
40024	70050	524	0	0	1	0	0	0	0	70020	69760	59695	25	40010	30010	10001	30010	10000	616952	3342206	1	49	66967	70035	70047	64668	0	3	64960	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	3	10000	1	0	0	0	2520	0	1	71	2	1	0	69801	30003	6	0	9	10000	30010	70051	70052	70051	70036	70048
40024	70050	525	0	0	1	0	0	0	0	70035	69760	59709	25	40010	30010	10001	30010	10000	617068	3341470	0	49	66955	70050	70035	64673	0	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	0	10000	1	0	0	0	2520	0	1	71	2	2	1	69798	30000	9	0	9	10000	30010	70051	70036	70048	70051	70051
40024	70035	524	0	0	6	0	1	0	0	70020	69760	59695	25	40014	30013	10001	30010	10000	617068	3342062	1	49	66955	70050	70050	64668	0	3	64960	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	0	10000	1	1	0	0	2520	0	1	71	2	1	1	69813	30003	9	6	0	10000	30010	70051	70036	70051	70051	70051
40024	70050	524	0	0	0	0	0	0	0	70020	69728	59709	25	40014	30013	10001	30010	10000	617068	3342206	1	49	66970	70050	70050	64668	0	3	64960	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	0	10000	0	1	0	0	2520	0	1	71	3	1	1	69798	30000	9	0	9	10000	30010	70079	70127	70051	70051	70036
40024	70050	524	0	0	1	0	0	0	0	70020	69760	59709	25	40014	30013	10001	30010	10000	616952	3342062	1	49	66955	70050	70035	64668	0	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	0	10000	1	1	0	0	2520	0	1	71	2	1	1	69813	30003	0	6	9	10000	30010	70051	70036	70036	70036	70036
40024	70050	525	0	0	1	0	0	0	0	70035	69760	59709	25	40014	30013	10004	30010	10000	616982	3342206	1	49	66955	70035	70050	64668	0	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	3	10000	1	1	0	0	2520	0	1	71	2	1	1	69798	30003	9	6	0	10000	30010	70048	70051	70036	70094	70040
40024	70051	524	0	0	6	0	0	0	0	70033	69728	59695	25	40014	30013	10001	30010	10000	616982	3342062	1	49	66970	70050	70050	64668	0	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	0	10000	1	1	0	0	2520	0	1	71	2	1	1	69813	30003	9	6	6	10000	30010	70036	70051	70051	70051	70051
40024	70050	524	0	0	0	0	0	0	0	70020	69760	59695	25	40014	30010	10001	30010	10000	616982	3341470	1	49	66970	70050	70050	64653	0	3	64960	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	0	10000	0	1	0	0	2520	0	1	71	2	1	1	69810	30003	6	9	6	10000	30010	70051	70036	70051	70051	70048
40024	70047	525	0	0	1	0	1	0	0	70035	69760	59709	25	40014	30013	10000	30010	10000	616982	3342206	1	49	66970	70050	70050	64653	0	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	0	10000	1	1	0	0	2520	0	1	71	2	1	1	69813	30000	9	6	0	10000	30010	70051	70051	70051	70051	70048

Test 4: throughput

Count: 8

Code:

  ldrsh x0, [x6, w7, sxtw]
  ldrsh x0, [x6, w7, sxtw]
  ldrsh x0, [x6, w7, sxtw]
  ldrsh x0, [x6, w7, sxtw]
  ldrsh x0, [x6, w7, sxtw]
  ldrsh x0, [x6, w7, sxtw]
  ldrsh x0, [x6, w7, sxtw]
  ldrsh x0, [x6, w7, sxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26732	201	1	1	0	0	0	65	1	0	0	26692	2	18	18	12	25	80100	100	80000	100	80014	500	1167875	1	49	23647	26722	26722	16655	6	16674	80114	200	80024	200	160048	26733	88	1	1	80201	100	99	100	80000	100	80000	1	100	80020	21	42	80058	0	0	0	59	80037	6	1	57	41	19	0	1	1	1	5118	0	16	0	0	26730	9	0	2	80000	100	26734	26715	26733	26733	26746
80204	26714	200	1	1	1	0	1	65	0	0	2	26718	2	18	18	17	25	80100	100	80000	100	80016	500	1167561	1	49	23653	26732	26714	16660	6	16685	80115	200	80024	200	160048	26725	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	80036	0	0	0	35	80035	0	1	35	39	0	0	1	1	1	5118	0	16	0	0	26719	6	6	2	80000	100	26723	26708	26708	26708	26723
80204	26707	200	0	0	0	0	1	0	1	0	2	26717	2	18	0	16	25	80100	100	80000	100	80016	500	1169563	1	49	23652	26732	26732	16659	6	16683	80115	200	80024	200	160048	26734	81	1	1	80201	100	99	100	80000	100	80000	0	100	80019	19	42	80057	0	0	2	59	80038	6	0	57	42	19	1	1	1	1	5118	0	16	0	0	26826	6	6	2	80000	100	26723	26723	26723	26723	26723
80204	26722	200	0	0	0	0	0	45	0	0	1	26707	2	12	18	12	25	80100	100	80000	100	80014	500	1177116	1	49	23642	26722	26722	16650	6	16659	80114	200	80024	200	160048	26728	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	80000	0	0	0	36	80038	6	1	57	42	19	1	1	1	1	5118	0	16	0	0	26724	0	6	2	80000	100	26723	26723	26723	26723	26723
80204	26722	200	0	0	0	0	0	74	1	0	3	26717	2	18	18	16	25	80100	100	80000	100	80015	500	1169757	1	49	23634	26732	26732	16660	6	16684	80116	200	80024	200	160048	26736	82	1	1	80201	100	99	100	80000	100	80000	1	100	80020	20	42	80057	0	0	1	59	80038	6	1	57	42	19	0	1	1	1	5118	0	16	0	0	26723	9	9	2	80000	100	26734	26733	26733	26733	26734
80204	26733	200	1	0	0	0	0	65	1	0	3	26717	2	18	18	15	25	80100	100	80000	100	80016	500	1169757	0	49	23652	26732	26732	16660	6	16685	80115	200	80024	200	160048	26742	81	1	1	80201	100	99	100	80000	100	80000	0	100	80019	20	42	80056	1	0	0	58	80038	6	1	57	42	19	1	1	1	1	5118	0	16	0	0	26730	9	9	2	80000	100	26733	26733	26733	26733	26733
80204	26732	200	1	0	0	0	0	65	0	0	3	26717	2	18	18	16	25	80100	100	80000	100	80015	500	1169757	0	49	23652	26732	26732	16660	6	16685	80115	200	80024	200	160048	26737	81	1	1	80201	100	99	100	80000	100	80000	0	100	80020	20	42	80058	0	0	0	59	80038	6	0	57	42	19	2	1	1	1	5118	0	16	0	0	26729	9	9	2	80000	100	26734	26734	26734	26733	26733
80204	26732	200	1	1	1	0	0	64	1	0	2	26718	2	0	18	16	25	80100	100	80000	100	80015	500	1177389	0	49	23652	26732	26733	16642	6	16684	80113	200	80024	200	160048	26735	81	1	1	80201	100	99	100	80000	100	80000	0	100	80021	19	41	80057	1	0	1	60	80000	6	1	57	42	19	1	1	1	1	5118	0	16	0	0	26734	9	9	2	80000	100	26733	26733	26733	26733	26734
80204	26733	200	1	1	1	0	0	65	1	0	0	26717	2	18	18	16	25	80100	100	80000	100	80016	500	1169563	0	49	23652	26732	26714	16660	6	16684	80114	200	80024	200	160048	26732	81	1	1	80201	100	99	100	80000	100	80000	0	100	80019	20	42	80057	0	0	1	62	80000	6	1	57	42	19	1	1	1	1	5118	0	16	0	0	26719	6	6	2	80000	100	26708	26723	26723	26723	26708
80204	26722	200	0	0	0	0	0	0	1	0	1	26707	0	18	18	12	25	80100	100	80000	100	80014	500	1167875	1	49	23642	26722	26722	16650	6	16674	80114	200	80024	200	160048	26740	81	1	1	80201	100	99	100	80000	100	80000	0	100	80019	20	42	80059	0	0	0	59	80038	6	1	57	42	19	2	1	1	1	5118	0	16	0	0	26729	9	9	0	80000	100	26733	26734	26734	26734	26733

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26736	200	0	0	0	0	0	1	0	0	57	0	1	1	26721	2	12	12	16	25	80010	10	80000	10	80000	50	1166750	1	49	23648	26730	26727	16682	3	16846	80010	20	80000	20	160000	26714	64	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	19	43	0	80059	1	0	1	21	80041	6	1	19	43	19	0	5020	7	16	2	4	26705	10	10	4	80000	10	26709	26728	26728	26728	26729
80024	26728	200	0	0	0	0	1	0	0	0	57	0	1	0	26712	2	12	12	16	25	80010	10	80000	10	80000	50	1168843	0	49	23647	26708	26727	16681	3	16724	80010	20	80000	20	160000	26736	64	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	20	0	0	80059	1	0	1	21	80000	0	0	59	0	19	2	5020	3	16	2	4	26724	0	0	0	80000	10	26729	26729	26729	26729	26728
80024	26727	200	0	0	0	0	0	0	0	0	63	0	1	0	26693	2	12	0	16	25	80010	10	80000	10	80000	50	1168843	1	49	23648	26727	26727	16682	3	16722	80010	20	80000	20	160000	26736	64	1	1	80021	10	9	0	10	80000	10	80000	0	10	80021	21	43	0	80059	1	0	1	63	80040	6	1	59	43	19	1	5020	2	16	3	5	26705	10	10	4	80000	10	26729	26728	26728	26728	26729
80024	26728	201	0	0	0	0	0	0	0	0	66	0	1	1	26713	2	12	12	8	25	80010	10	80000	10	80000	50	1166750	0	49	23648	26727	26708	16682	3	16707	80010	20	80000	20	160000	26728	77	1	1	80021	10	9	0	10	80000	10	80000	0	10	80000	0	43	0	80000	0	0	0	39	80039	6	1	39	43	0	0	5020	4	16	2	4	26724	10	10	4	80000	10	26728	26728	26728	26728	26709
80024	26727	201	0	0	0	0	0	0	0	0	45	0	0	1	26712	2	12	0	16	25	80010	10	80000	10	80000	50	1166750	0	49	23663	26737	26755	16701	3	16716	80010	20	80000	20	160000	26736	85	2	1	80021	10	9	0	10	80000	10	80000	0	10	80021	20	44	0	80059	1	0	1	93	80040	6	0	0	43	0	0	5020	2	16	4	2	26725	10	10	4	80000	10	26728	26728	26728	26728	26732
80024	26728	200	0	0	0	0	0	0	0	0	45	0	0	1	26713	2	12	12	16	25	80010	10	80000	10	80000	50	1166896	0	49	23649	26741	26745	16681	3	16716	80010	20	80000	20	160000	26736	64	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	20	0	0	80019	1	0	2	61	80040	6	1	0	43	0	0	5020	2	16	2	4	26724	10	10	0	80000	10	26729	26729	26709	26729	26728
80024	26727	200	0	0	0	0	1	1	0	0	67	0	1	2	26721	3	7	7	0	25	80010	10	80000	11	80000	50	1167298	0	49	23661	26728	26716	16672	3	16688	80010	20	80000	20	160000	26727	77	1	1	80021	10	9	0	10	80000	10	80000	0	10	80000	0	43	0	80039	0	0	0	39	80039	0	1	19	43	19	1	5020	4	16	4	2	26734	13	13	0	80000	10	26738	26737	26738	26715	26737
80024	26736	200	1	1	1	0	0	0	0	0	45	0	1	1	26713	2	12	12	16	25	80010	10	80000	10	80000	50	1168843	0	49	23648	26731	26728	16806	3	16707	80010	20	80000	20	160000	26708	77	1	1	80021	10	9	0	10	80000	10	80000	0	10	80000	0	0	0	80039	0	0	0	39	80039	6	1	39	43	0	0	5020	2	16	4	4	26724	10	10	4	80000	10	26728	26728	26729	26729	26728
80024	26708	200	0	0	0	0	0	0	0	0	45	0	0	0	26712	0	12	12	18	33	80010	10	80000	10	80000	50	1166896	0	49	23635	26931	26736	16681	3	16716	80010	20	80000	20	160000	26737	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	21	43	0	80019	1	0	2	21	80000	6	1	39	0	0	0	5020	2	16	2	4	26705	10	10	4	80000	10	26728	26728	26728	26728	26728
80024	26727	200	0	0	0	0	0	0	0	0	0	0	1	1	26693	2	12	12	16	25	80010	10	80000	10	80000	50	1169962	0	49	23657	26729	26732	16654	3	16707	80010	20	80000	20	160000	26708	77	1	1	80021	10	9	0	10	80000	10	80000	0	10	80000	0	0	0	80039	0	0	0	39	80000	6	1	59	43	19	2	5020	2	16	4	2	26737	13	13	5	80000	10	26716	26737	26737	26737	26737

LDRSH (register, sxtw, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations