Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UBFX (32-bit)

Test 1: uops

Code:

  ubfx w0, w0, #3, #7
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)033f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100410358618622510001000100016916110351035728386810001000100010354111100110000073141119371000100010361036103610361036
100410357618622510001000100016916110351035728386810001000100010354111100110000073141119371000100010361036103610361036
100410358618622510001000100016916110351035728386810001000100010354111100110000073141119371000100010361036103610361036
100410357618622510001000100016916010351035728386810001000100010354111100110000073141119371000100010361036103610361036
100410357828622510001000100016916010351035728386810001000100010354111100110000073141119371000100010361036103610361036
100410358618622510001000100016916110351035728386810001000100010354111100110000073141119371000100010361036103610361036
100410358618622510001000100016916010351035728386810001000100010354111100110000073141119371000100010361036103610361036
100410357618622510001000100016916110351035728386810001000100010354111100110000073141119371000100010361036103610361036
100410358618622510001000100016916010351035728386810001000100010354111100110000073141119371000100010361036103610361036
100410358858622510001000100016916110351035728386810001000100010354111100110000073141119371000100010361036103610361036

Test 2: Latency 1->2

Code:

  ubfx w0, w0, #3, #7
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204100357506198772510100101001010088664496955100351003585803872210100102001020010035411110201100991001010010000071023722994110000101001003610036100361003610036
1020410035751119598772510100101001010088664496955100351003585803872210100102001020010035411110201100991001010010000071023724994110000101001003610036100361003610036
102041003575186198772510100101001010088664496955100351003585803872210100102001020010035411110201100991001010010000071023722994110000101001003610036100361003610036
10204100357506198772510100101001010088664496955100351003585803872210100102001020010035411110201100991001010010000071023722994110000101001003610036100361003610036
102041003575156198772510100101001010088664496955100351003585803872210100102001020010035411110201100991001010010000071023722994110000101001003610036100361003610036
10204100357508298772510100101001010088664496955100351003585803872210100102001020010035411110201100991001010010000071023722994110000101001003610036100361003610036
10204100357506198772510100101001010088664496955100351003585803872210100102001020010035411110201100991001010010000071023722994110000101001003610036100361003610036
10204100357506198772510100101001010088664496955100351003585803872210100102001020010035411110201100991001010010000071023722994110000101001003610036100361003610036
10204100357506198772510100101001010088664496955100351003585803872210100102001020010035411110201100991001010010000071023722994110000101001003610036100361003610036
10204100357506198772510100101001010088664496955100351003585803872210100102001020010035411110201100991001010010000071023722994110000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03mmu table walk data (08)181e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1002410035750045619863251001010010100108878414969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036
100241003575000619863251001010010100108878414969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036
100241003575000619863251001010010100108878414969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036
10024100357500207619863251001010010100108878414969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036
100241003575000619863251001010010100108878414969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036
100241003575000619863251001010010100108878414969551003510035860238740100101002010020100354111100211091010010100064024123994010000100101003610082100361003610036
1002410035750033619863251001010010100108878414970011003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100811003610036
100241003575000619863251001010010100108878414969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036
100241003575000619863251001010010100108878404969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036
1002410035750012619863251001010010100108878414969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036

Test 3: throughput

Count: 8

Code:

  ubfx w0, w8, #3, #7
  ubfx w1, w8, #3, #7
  ubfx w2, w8, #3, #7
  ubfx w3, w8, #3, #7
  ubfx w4, w8, #3, #7
  ubfx w5, w8, #3, #7
  ubfx w6, w8, #3, #7
  ubfx w7, w8, #3, #7
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.1674

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)191e1f3a3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80204134131001001009002827801368013680148400710149103101339013390332663336801488026480264133903911802011009910080100100001115119216111338780036801001339113391133911339113391
802041339010010010000021827801368013680148400710149103101339013390332663336801488026480264133903911802011009910080100100001115119116111338780036801001339113391133911339113391
80204133901011001006002827801368013680148400710149103101339013390332663336801488026480264133903911802011009910080100100001115119116111338780036801001339113391133911339113391
80204133901001001000002827801368013680148400710149103101339013390332663336801488026480264133903911802011009910080100100001115119116111338780036801001339113391133911339113391
80204133901001001000002827801368013680148400710149103101339013390332663336801488026480264133903911802011009910080100100001115119416111338780036801001339113391133911339113391
802041339010010010012002827801368013680148400710149103101339013390332663336801488026480264133903911802011009910080100100001115119116111338780036801001339113391133911339113391
80204133901001001000002827801368013680148400710149103101339013390332663336801488026480264133903911802011009910080100100001115119116111338780036801001339113391133911339113391
80204133901001001006002827801368013680148400710149103101339013390332663336801488026480264133903911802011009910080100100001115119116111338780036801001339113391133911339113391
80204133901001001000002827801368013680148400710149103101339013390332663336801488026480264133903911802011009910080100100001115119116111338780036801001339113391133911339113391
80204133901001001000002827801368013680148400710149103101339013390332663336801488026480264142653911802011009910080100100001115119116111338780036801001339113391133911339113391

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.1671

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fcdcfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ea? int retires (ef)f5f6f7f8fd
8002413389101035258001080010800104000504910291133711337133303334880010800208002013371391180021109108001010050410006196213368800000800101337213372133721337213372
8002413371100035258001080010800104000504910291133711337133303334880010800208002013371391180021109108001010050200002192213368800000800101337213372133721337213372
8002413371100035258001080010800104000504910291133711337133303334880010800208002013371391180021109108001010050200002192613368800000800101337213372133721337213372
8002413371100035258001080010800104000504910291133711337133303334880010800208002013371391180021109108001010050200002192213368800000800101337213372133721337213372
80024133711000225258001080010800104000504910291133711337133303334880010800208002013371391180021109108001010050200002192213368800000800101337213372133721337213372
8002413371100035258001080010800104000504910291133711337133303334880010800208002013371391180021109108001010050200002192213368800000800101337213372133721337213372
8002413371100035258001080010800104000504910291133711337133303334880010800208002013371391180021109108001010050220006196213368800000800101337213372133721337213372
8002413371100035258001080010800104000504910291133711337133303334880010800208002013371391180021109108001010050220002196213368800000800101337213372133721337213372
8002413371101035258001080010800104000504910291133711337133303334880010800208002013371391180021109108001010050200002192613368800000800101337213372133721337213372
8002413371100035258001080010800104000504910291133711337133303334880010800208002013371391180021109108001010050200012193613368800000800101337213372133721337213372