Firestorm: UDIV (medium, 64-bit) measurements

Code:

  udiv x0, x1, x2

Initialization

  mov x1, #0xffffffff
  mov x2, #3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	2039	15	61	950	25	1000	1000	1000	53725	1	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	3	16	1	1	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	16	61	950	25	1000	1000	1000	53725	1	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	61	950	25	1000	1000	1000	53725	1	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	1	16	1	1	2031	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	61	950	25	1000	1000	1000	53725	1	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	61	950	25	1000	1000	1000	53725	1	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	61	950	25	1000	1000	1000	53725	1	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	16	61	950	25	1000	1000	1000	53725	0	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	61	950	25	1000	1000	1000	53725	1	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	61	950	25	1000	1000	1000	53725	1	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	61	950	25	1000	1000	1000	53725	1	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	1	16	1	1	1980	1000	1000	2040	2040	2040	2040	2040

Test 2: Latency 1->2

Chain cycles: 2

Code:

  udiv x0, x1, x2
  eor x1, x1, x0
  eor x1, x1, x0

Initialization

  mov x1, #0xffffffff
  mov x2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30204	100035	749	0	814	91261	25	30100	30100	30100	9493443	0	49	96955	0	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	1910	2	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	61	91261	25	30100	30100	30100	9493443	1	49	96955	0	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	61	91261	25	30100	30100	30100	9493443	1	49	96955	0	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	750	0	61	91261	25	30100	30100	30100	9493443	1	49	96955	0	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	1910	1	17	1	1	99722	30015	30100	100036	100036	100036	100036	100036
30204	100035	749	0	61	91261	25	30100	30100	30100	9493443	1	49	96955	0	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	61	91261	25	30100	30100	30100	9493443	0	49	96955	3	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	210	91261	25	30100	30100	30100	9493443	1	49	96955	0	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	750	0	61	91261	25	30100	30100	30100	9493443	1	49	96955	0	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	61	91261	25	30100	30100	30100	9493443	1	49	96955	0	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	61	91261	25	30100	30100	30100	9493443	1	49	96955	0	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100077	100036	100036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30024	100035	750	0	0	0	15	0	726	91182	25	30010	30010	30010	9478767	49	96955	100035	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	1	0	0	0	1890	2	16	2	2	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	0	0	0	0	61	91182	25	30010	30010	30010	9478767	49	96955	100035	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	2	16	2	2	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	0	0	0	0	61	91182	25	30010	30010	30010	9478767	49	96955	100035	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	2	16	2	2	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	0	0	0	0	61	91182	25	30010	30010	30010	9478767	49	96955	100075	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	2	16	2	2	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	0	0	0	0	61	91182	25	30010	30010	30010	9478767	49	96955	100035	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	2	16	2	2	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	0	0	0	0	61	91182	25	30010	30010	30010	9478767	49	96955	100035	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	2	16	2	2	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	750	0	0	0	0	0	61	91182	25	30010	30010	30010	9478767	49	96955	100035	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	2	16	2	2	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	0	0	0	0	82	91182	25	30010	30010	30010	9478767	49	96955	100035	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	2	0	1890	2	41	2	2	99714	30017	30010	100036	100036	100036	100036	100036
30024	100035	750	0	0	0	0	0	103	91182	25	30010	30010	30010	9478767	49	96955	100035	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	2	24	2	2	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	0	0	0	0	82	91182	25	30010	30010	30010	9478767	49	96955	100035	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	2	16	2	2	99714	30000	30010	100036	100036	100036	100036	100036

Test 3: Latency 1->3

Chain cycles: 2

Code:

  udiv x0, x1, x2
  eor x2, x2, x0
  eor x2, x2, x0

Initialization

  mov x1, #0xffffffff
  mov x2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	18	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30204	100035	749	0	0	0	0	66	91261	25	30100	30100	30100	9480390	49	96955	0	100035	100035	95873	0	13	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	2	17	1	3	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	750	0	0	0	9	61	91261	25	30100	30100	30100	9493443	49	96955	0	100035	100035	95873	0	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	0	61	91261	25	30100	30100	30100	9493443	49	96955	0	100035	100035	95873	0	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	2	0	0	0	0	1910	1	17	1	2	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	0	61	91261	25	30100	30100	30100	9493443	49	96955	0	100035	100035	95873	0	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	0	61	91261	25	30100	30100	30100	9493443	49	96955	0	100035	100035	95873	0	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100077	100036	100036
30204	100035	749	0	0	0	0	61	91261	25	30100	30100	30100	9493443	49	96955	0	100035	100035	95873	0	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	33	0	0	1910	1	17	1	2	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	0	726	91261	25	30100	30100	30100	9493443	49	96955	0	100035	100035	95873	0	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	2	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	0	61	91261	25	30100	30100	30100	9493443	49	96955	0	100035	100035	95873	0	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	0	61	91261	25	30107	30100	30100	9493443	49	96955	0	100035	100035	95873	0	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	0	61	91261	25	30100	30100	30100	9493443	49	96955	0	100035	100035	95873	0	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	1	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30024	100035	749	0	61	91182	25	30010	30010	30010	9478767	49	96955	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	4	16	3	3	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	61	91182	25	30010	30010	30010	9484530	49	96955	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	3	16	3	3	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	61	91182	25	30010	30010	30010	9478767	49	96955	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	3	16	3	3	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	61	91182	25	30010	30010	30010	9478767	98	96955	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	3	16	3	3	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	61	91182	25	30010	30010	30010	9478767	49	96955	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	3	0	1890	3	16	3	3	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	61	91182	25	30010	30010	30010	9478767	49	96955	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	3	16	3	3	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	61	91182	25	30010	30010	30010	9478767	49	96955	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	3	1890	3	16	3	3	99714	30000	30010	100077	100036	100036	100036	100036
30024	100035	749	0	61	91182	25	30010	30010	30010	9478767	49	96955	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	3	16	3	3	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	61	91182	25	30010	30010	30010	9478767	49	96955	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	3	16	3	3	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	750	0	61	91182	25	30010	30010	30010	9478767	49	96955	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1890	3	16	3	3	99714	30000	30010	100036	100036	100036	100036	100036

Test 4: throughput

Count: 8

Code:

  udiv x0, x8, x9
  udiv x1, x8, x9
  udiv x2, x8, x9
  udiv x3, x8, x9
  udiv x4, x8, x9
  udiv x5, x8, x9
  udiv x6, x8, x9
  udiv x7, x8, x9

Initialization

  mov x8, #0xffffffff
  mov x9, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	18	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	160039	1199	0	0	0	0	61	79950	25	80100	80100	80100	4399225	1	49	156959	0	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	5110	4	16	4	4	159980	80000	80100	160040	160040	160040	160040	160040
80204	160039	1199	0	0	0	0	61	79950	25	80100	80100	80100	4399225	0	49	156959	0	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	5110	4	16	4	5	159980	80000	80100	160040	160040	160040	160040	160040
80204	160039	1199	0	0	0	9	61	79950	25	80129	80100	80100	4399225	0	49	156959	0	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	5110	3	16	4	5	159980	80000	80100	160040	160040	160040	160040	160079
80204	160039	1199	0	0	0	0	61	79950	25	80100	80100	80100	4399225	0	49	156959	0	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	0	5110	4	16	4	4	159980	80000	80100	160040	160186	160040	160040	160040
80204	160039	1199	0	0	0	0	61	79950	25	80100	80100	80100	4399225	0	49	156959	0	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	135	0	0	0	5131	4	16	4	4	159980	80000	80100	160040	160040	160040	160040	160040
80204	160039	1199	0	0	0	0	61	79950	25	80100	80100	80100	4399225	0	49	156959	0	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	5110	5	16	5	4	159980	80000	80100	160040	160083	160040	160040	160040
80204	160039	1199	0	0	0	0	61	79950	25	80100	80100	80100	4399225	1	49	156959	0	160039	160039	149901	3	150027	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	5110	5	16	4	5	159980	80000	80100	160040	160040	160040	160040	160040
80204	160039	1198	0	0	0	0	61	79950	25	80100	80100	80271	4399225	0	49	156959	0	160039	160089	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	5110	5	16	5	4	159980	80000	80100	160040	160040	160040	160040	160040
80204	160039	1198	0	0	0	648	61	79950	25	80100	80100	80100	4399225	0	49	156959	0	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	5110	4	16	3	3	159980	80000	80100	160040	160040	160040	160040	160040
80204	160039	1198	0	0	0	0	61	79950	25	80100	80100	80100	4399225	0	49	156959	0	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	9	0	0	0	5110	4	16	4	4	159980	80000	80100	160040	160040	160040	160040	160040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	3f	4d	50	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	160039	1199	0	0	0	726	79950	0	25	80010	80010	80010	4398775	1	0	49	156959	160039	160039	149923	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	1	0	0	5020	5	0	4	16	4	4	159980	80000	80010	160040	160040	160040	160040	160040
80024	160039	1198	0	657	0	279	79950	0	25	80010	80010	80010	4398775	1	5	49	156959	160039	160039	149923	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	5	0	5	16	4	3	159980	80000	80010	160040	160040	160040	160040	160040
80024	160039	1198	0	0	0	61	79950	0	25	80010	80010	80010	4398775	1	5	49	156959	160039	160039	149923	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	4	0	0	5020	5	1	5	16	5	4	159980	80000	80010	160040	160040	160040	160040	160040
80024	160039	1199	0	0	0	61	79950	0	110	80025	80010	80010	4399347	1	5	49	156959	160039	160188	149923	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	5	1	4	16	4	3	159980	80000	80010	160040	160040	160040	160040	160040
80024	160039	1199	0	0	0	61	79950	0	25	80010	80010	80010	4398775	1	5	49	156959	160039	160039	149923	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	5	1	3	16	3	4	159980	80000	80010	160040	160040	160040	160040	160040
80024	160039	1199	0	0	0	1127	79950	0	25	80010	80010	80010	4398775	1	5	49	156959	160039	160039	149923	3	150019	80010	80076	160122	160039	261	1	1	80021	10	9	10	80010	10	0	0	3	12	0	5020	5	1	3	16	4	4	159980	80000	80010	160040	160040	160040	160040	160040
80024	160039	1199	0	0	0	726	79950	0	25	80010	80010	80010	4398775	1	0	49	156959	160039	160039	149923	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5076	5	1	5	16	4	4	159980	80000	80010	160040	160040	160040	160040	160040
80024	160039	1199	1	0	598	902	79950	0	67	80010	80010	80010	4398924	1	5	49	156959	160039	160039	149923	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	1	3	0	5020	5	1	4	16	4	5	160124	80015	80010	160040	160040	160090	160089	160089
80024	160089	1200	0	24	0	61	79950	0	25	80064	80024	80010	4398775	1	5	49	156959	160039	160039	149923	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	2	5	870	0	5020	5	1	3	16	4	3	159980	80000	80010	160040	160040	160040	160040	160040
80024	160039	1199	0	0	0	61	79950	0	25	80010	80010	80010	4398775	1	5	49	156959	160039	160039	149923	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	5	1	4	16	4	4	159980	80000	80010	160040	160040	160040	160040	160040

UDIV (medium, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations