Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

BFC (64-bit)

Test 1: uops

Code:

  bfc x0, #3, #7
  mov x0, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100410368070251000100010005999010361036864389410001000100010361641110011000000731161110321000100010371037103710371037
100410367047251000100010005999010361036864389410001000100010361641110011000000731161110321000100010371037103710371037
100410368047251000100010005999010361036864389410001000100010361641110011000013731161110321000100010371037103710371037
1004103679472510001000100059990103610368643894100010001000103616411100110000012731161110321000100010371037103710371037
1004103680472510001000100059990103610368643894100010001000103616411100110000018731161110321000100010371037103710371037
100410368066251000100010005999010361036864389410001000100010361641110011000000731161110321000100010371037103710371037
100410368070251000100010005999010361036864389410001000100010361641110011000009731161110321000100010371037103710371037
100410367047251000100010005999010361036864389410001000100010361641110011000009731161110321000100010371037103710371037
1004103680472510001000100059990103610368643894100010001000103616411100110000015731161110321000100010371037103710371037
1004103670142251000100010005999010361036864389410001000100010361641110011000000731161110321000100010371037103710371037

Test 2: Latency 1->1

Code:

  bfc x0, #3, #7
  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0036

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1020410036753935251010010100101006049949695610036100368721687391010010208102081003616211102011009910010100100111718161003310000101001003710037100371003710037
102041003675056251010010100101006049949695610036100368721787401010010208102081003616211102011009910010100100111717161003310000101001003710037100371003710037
102041003675036251010010100101006049949695610036100368721687401010010208102081003616211102011009910010100100111717161003310000101001003710037100371003710037
102041003675635251010010100101006049949695610036100368721687391010010208102081003616211102021009910010100100111717161003310000101001003710037100371003710037
102041003675936251010010100101006049949695610036100368721687401010010208102081003616211102011009910010100100111718161003310000101001003710037100371003710037
10204100367515036251010010100101006049998695610036100368721687401010010208102081003616211102011009910010100100111718161003310000101001003710037100371003710037
102041003675035251010010100101006049949695610036100368721787401010010208102081003616211102011009910010100100111717161003310000101001003710037100371003710037
10204100367736336251010010100101006049949695610036100368721687391010010208102081003616211102011009910010100100111717161003310000101001003710037100371003710037
102041003675035251010010100101006049949695610036100368721787401010010208102081003616211102011009910010100100111717161003310000101001003710037100371003710037
102041003675036251010010100101006049949695610036100368721687391010010208102081003616211102011009910010100100111717161003310000101001003710037100371003710037

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0036

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024100377500000240472510010100101001060049149695601003610036873638766100101002010020100361641110021109101001010000000640316221003210000100101003710037100371008410037
1002410036750000000702510010100101001060049149695601003610036873638766100101002010020100361641110021109101001010000000640216221003210000100101003710037100371003710037
10024100367500000210472510010100101001060049149695601003610036873638766100101002010020100361641110021109101001010000000640216221003210000100101003710037100371003710037
100241003675000001860472510010100101001060049149695601003610036873638766100101002010020100361641110021109101001010000000640216221003210000100101003710037100371003710037
10024100367500000005852510010100101001060049149695601003610036873638766100101002010020100361641110021109101001010000000640216221003210000100101003710037100371003710037
1002410036750000000702510010100101001060049149695601003610036873638766100101002010020100361641110021109101001010000000640216221003210000100101003710037100371003710037
1002410036760000000472510010100101001060049149695601003610036873638766100101002010020100361641110021109101001010000000640216221003210000100101003710037100371003710037
10024100367500000150472510010100101001060049149695601003610036873638766100101002010020100361641110021109101001010000000640216221003210000100101003710037100371003710037
1002410036750000000472510010100101001060049149695601003610036873638766100101002010020100361641110021109101001010000000640216221003210000100101003710037100371003710037
10024100367500000750472510010100101001060049149695601003610036873638766100101002010020100361641110021109101001010000000640216221003210000100101003710037100371003710037

Test 3: throughput

Count: 8

Code:

  bfc x0, #3, #7
  bfc x1, #3, #7
  bfc x2, #3, #7
  bfc x3, #3, #7
  bfc x4, #3, #7
  bfc x5, #3, #7
  bfc x6, #3, #7
  bfc x7, #3, #7

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e1f3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8020480035599000046258010080100801004005004976955800358003569964369993801008020080200800351641180201100991008010010000005110316338003180000801008003680036800368003680036
8020480035599000061258010080100801004005004976955800358003569964369993801008020080200800351641180201100991008010010000005110316338003180000801008003680036800368003680036
8020480214599000046258010080100801004005004976955800358003569964369993801008020080200800351641180201100991008010010000005110316338003180000801008003680036800368003680036
8020480035599000067258010080100801004005004976955800358003569964369993801008020080200800351641180201100991008010010000005110316338003180000801008003680036800368003680036
8020480035600000046258010080100801004005004976955800358003569964369993801008020080200800351641180201100991008010010000005110316338003180000801008003680036800368003680036
8020480035599000046258010080100801004005004976955800358003569964369993801008020080200800351641180201100991008010010000005110316338003180000801008003680036800368003680036
80204800356000048074258010080100801004005004976955800358003569964369993801008020080200800351641180201100991008010010000005110316338003180000801008003680036800368003680036
8020480035599000046258010080100801004005004976955800358003569964369993801008020080200800351641180201100991008010010000005110316338003180000801008003680036800368003680036
8020480035599000046258010080100801004005004976955800358003569964369993801008020080200800351641180201100991008010010000105110316338003180000801008003680036800368003680036
8020480035599000046258010080100801004005004976955800358003569964369993801008020080200800351641180201100991008010010000005110316338003180000801008003680036800368003680036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80024800356000000000004625800108001080010400050497695508003580035699863700158001080020800208003516411800211091080010100000000050200316118003280000800108003680036800368003680036
80024800356000000004004625800108001080010400050497695508003580035699863700158001080020800208003516411800211091080010100030001983050200116118003280000800108003680036800368003680036
80024800355990000000004625800108001080010400050497695508003580035699863700158001080020800208003516411800211091080010100000000050200116118003280000800108003680036800368003680036
80024800355990000000604625800108001080010400050497695508003580035699863700158001080020800208003516411800211091080010100000000050200116218003280000800108003680036800368003680036
80024800356000000000004625800108001080010400050497695508003580035699863700158001080020800208003516411800211091080010100000000050200116228003280000800108003680036800368003680036
80024800356000000000004625800108001080010400050497695508003580035699863700158001080020800208003516411800211091080010100000003050200116118003280000800108003680036800368003680036
80024800355990000000004625800108001080010400050497695508003580035699863700158001080020800208003516411800221091080010100000000050200116118003280000800108003680036800368003680036
80024800355990000000004625800108001080010400050497695508003580035699863700158001080020800208003516411800211091080010100000000050200116118003280000800108003680036800368003680036
80024800356000000000007925800108001080010400050497695508007380035699863700158001080020800208003516411800211091080010100000000050200116118003280000800108003680036800368003680036
80024800355990000000004625800108003280010400050497695508003580035699863700158001080020800208003516411800211091080010100000000050200116328003280000800108003680036800368003680036