Firestorm: LDURB measurements

Code:

  ldurb w0, [x6, #1]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	402	2	1	1	44	0	0	1	383	0	1	0	16	25	1000	1000	1000	15274	1	398	398	221	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	6	1	39	44	73	1	16	1	1	398	0	0	0	1000	375	399	375	399	399
1004	398	3	0	1	44	0	0	1	359	2	0	1	0	25	1000	1000	1000	15274	1	374	398	221	3	256	1000	1000	1000	404	77	1	1	1001	1000	1000	0	1000	43	1000	0	38	1000	6	1	39	44	73	1	16	1	1	395	0	10	4	1000	399	375	399	399	399
1004	374	3	0	1	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15208	1	398	374	221	3	256	1000	1000	1000	398	56	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	6	1	38	44	73	1	16	1	1	395	14	14	0	1000	399	399	399	375	375
1004	398	3	1	0	44	0	0	1	383	2	0	1	19	25	1000	1000	1000	15274	1	398	374	221	3	256	1000	1000	1000	374	77	1	1	1001	1000	1000	0	1000	43	1038	0	38	1000	0	0	38	43	73	1	16	1	1	391	14	0	0	1000	395	375	375	375	375
1004	374	3	0	0	45	0	0	0	383	2	0	12	19	25	1000	1000	1000	14989	1	398	398	197	3	232	1000	1000	1000	398	56	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	0	0	39	43	73	1	16	1	1	395	14	14	7	1000	399	399	375	399	399
1004	398	3	1	0	44	0	0	1	388	2	0	1	19	25	1000	1000	1000	14060	1	398	400	197	3	233	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	0	1038	0	38	1039	6	1	39	44	73	1	16	1	1	395	14	14	4	1000	399	375	402	399	399
1004	374	3	1	0	44	1	0	0	359	2	0	1	19	25	1000	1000	1000	15274	1	398	398	221	3	232	1000	1000	1000	374	77	1	1	1001	1000	1000	0	1000	0	1000	0	38	1038	0	0	39	0	73	1	16	1	1	395	14	14	7	1000	399	399	399	375	399
1004	398	3	0	0	0	1	0	1	379	0	0	1	0	25	1000	1000	1000	14060	1	374	398	197	3	232	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	0	1038	0	38	1038	6	0	38	44	73	1	16	1	1	371	14	14	0	1000	396	399	375	395	375
1004	374	2	0	0	45	0	0	1	359	2	1	12	19	25	1000	1000	1000	14060	1	394	398	217	3	232	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	43	1038	0	38	1000	6	1	39	44	73	1	16	1	1	395	0	14	0	1000	399	399	399	375	399
1004	374	2	0	1	45	0	0	0	383	0	12	12	0	25	1000	1000	1000	14060	1	394	394	197	3	232	1000	1000	1000	394	56	1	1	1001	1000	1000	0	1000	43	1000	0	0	1038	0	0	39	44	73	1	16	1	1	391	14	14	4	1000	399	399	399	399	399

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldurb w0, [x6, #1]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70057	525	1	1	1	1	0	70020	69785	59713	25	40104	30103	10001	30100	10000	616014	3342398	49	66971	70058	70035	64650	0	3	64957	40100	30200	10000	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	10000	1	1	0	0	0	0	2610	2	71	1	1	69798	30003	13	10	13	10000	30100	70055	70055	70055	70036	70055
40204	70035	525	0	0	1	1	0	70039	69785	59710	25	40100	30100	10000	30100	10000	616175	3342398	49	66971	70053	70063	64650	0	3	64954	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	1	0	0	0	0	2610	1	71	1	1	69817	30003	13	0	0	10000	30100	70055	70055	70055	70055	70052
40204	70054	525	0	0	1	0	0	70020	69785	59713	25	40104	30103	10001	30100	10000	616014	3341470	49	66971	70056	70056	64631	0	3	64938	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	0	1	0	0	0	0	2610	1	71	1	1	69817	30000	0	10	14	10000	30100	70055	70036	70036	70036	70036
40204	70051	525	0	0	1	0	0	70039	69764	59713	25	40104	30103	10000	30100	10000	616175	3341470	49	66971	70037	70058	64650	0	3	64957	40100	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	10000	0	1	0	0	0	0	2610	1	71	1	1	69817	30003	13	0	0	10000	30100	70036	70055	70055	70055	70055
40204	70054	525	0	0	1	0	0	70020	69764	59713	25	40104	30103	10001	30100	10000	616041	3342398	49	66973	70457	70056	64673	0	3	64954	40296	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	10000	0	0	10000	0	1	0	0	0	0	2610	1	71	1	1	69817	30003	10	10	0	10000	30100	70036	70052	70052	70036	70055
40204	70054	524	0	0	0	1	0	70020	69764	59713	25	40104	30103	10001	30100	10000	616041	3342398	49	66971	70054	70097	64647	0	3	64954	40100	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	1	0	0	0	0	2610	1	71	1	1	69814	30003	10	13	10	10000	30100	70055	70055	70103	70056	70055
40204	70051	525	0	0	1	1	0	70039	69785	59695	25	40100	30100	10001	30100	10000	616175	3342398	49	66971	70054	70055	64650	0	3	64938	40100	30200	10000	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	0	0	0	0	0	0	2610	1	71	1	1	69772	30003	10	10	0	10000	30100	70055	70055	70036	70052	70036
40204	70054	524	0	0	1	0	0	70039	69782	59695	25	40100	30103	10001	30100	10000	616175	3342398	49	67081	70078	70054	64653	0	3	64938	40100	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10003	61	0	10000	1	1	0	0	0	0	2610	1	71	1	1	69798	30003	13	10	13	10000	30100	70052	70052	70055	70036	70052
40204	70054	525	0	0	25	1	0	70020	69782	59710	25	40100	30103	10000	30100	10000	616014	3342254	49	66971	70051	70059	64647	0	3	64957	40100	30200	10000	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	0	0	0	0	0	2610	1	71	1	1	69798	30003	10	10	0	10000	30100	70052	70036	70036	70052	70036
40204	70035	525	0	0	1	0	0	70020	69782	59695	25	40104	30103	10001	30100	10000	616014	3342398	49	66971	70409	70051	64651	0	3	64954	40100	30200	10000	60594	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	10000	0	0	10000	0	1	0	0	0	0	2610	1	71	1	1	69814	30003	10	10	13	10000	30100	70055	70055	70036	70036	70036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0057

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70057	524	1	1	1	0	0	0	74	0	1	0	1	70042	69781	59701	25	40018	30016	10002	30010	10000	616995	3342542	1	49	66977	0	70107	70061	64675	3	64976	40010	30020	10000	60020	10000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10001	0	0	1	1	10000	1	0	1	0	0	0	2520	1	71	1	1	69820	30006	10	10	10	10000	30010	70042	70042	70058	70058	70058
40024	70057	525	1	0	0	0	0	0	2	0	1	0	0	70026	69781	59716	25	40018	30013	10002	30010	10000	617045	3342542	0	49	66961	0	70058	70062	64675	3	64982	40010	30020	10000	60020	10000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	0	10003	1	0	1	1	10000	1	1	0	1	1	0	2520	1	71	1	1	69804	30006	10	0	10	10000	30010	70058	70058	70058	70058	70058
40024	70057	524	1	1	1	0	0	0	2	0	1	0	1	70026	69702	59718	25	40018	30016	10002	30010	10000	616995	3341769	1	49	66977	0	70096	70043	64675	3	64982	40010	30020	10000	60020	10000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	3	0	10001	0	0	2	4	10000	1	1	1	1	1	0	2520	1	71	1	1	69820	30006	0	10	0	10000	30010	70058	70058	70042	70058	70058
40024	70057	524	1	1	0	0	0	0	2	0	1	0	1	70042	69702	59701	25	40010	30010	10001	30010	10000	617068	3342254	0	49	66971	0	70135	70058	64675	3	64982	40010	30020	10000	60020	10000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10003	1	1	10003	0	0	0	1	10000	1	1	1	1	0	0	2520	1	71	1	1	69820	30006	0	10	10	10000	30010	70058	70058	70058	70058	70058
40024	70095	525	1	0	0	0	0	0	2	0	0	0	0	70042	69781	59716	25	40018	30016	10002	30010	10000	617045	3342542	1	49	66977	0	70125	70104	64677	3	64982	40010	30020	10000	60020	10000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	0	10001	0	0	1	1	10000	1	1	1	1	2	0	2520	1	71	1	1	69820	30006	10	10	10	10000	30010	70042	70058	70058	70058	70058
40024	70057	524	1	0	1	0	0	4	1	0	1	0	1	70042	69702	59716	25	40018	30016	10001	30010	10000	617045	3342542	1	49	66977	0	70057	70061	64675	3	64982	40010	30020	10000	60020	10000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10003	1	1	10002	0	0	1	1	10000	1	1	1	1	0	0	2520	1	71	1	1	69820	30006	10	10	0	10000	30010	70058	70058	70058	70058	70058
40024	70057	525	1	1	1	0	0	0	2	0	0	0	1	70042	69781	59716	25	40018	30016	10002	30010	10000	617045	3342542	0	49	66977	0	70137	70057	64675	3	64982	40010	30020	10000	60020	10000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	1	10002	0	0	0	1	10000	1	1	1	1	1	0	2520	1	71	1	1	69804	30006	0	10	10	10000	30010	70059	70044	70058	70042	70058
40024	70057	524	1	1	0	0	0	0	2	0	0	0	1	70042	69781	59701	25	40018	30016	10002	30010	10000	617045	3342542	0	49	66980	0	70057	70060	64659	3	64982	40010	30020	10000	60020	10000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	1	10001	0	0	2	1	10000	1	1	1	1	1	0	2520	1	71	1	1	69820	30006	10	0	10	10000	30010	70058	70058	70058	70058	70058
40024	70057	524	1	1	0	0	0	0	2	0	1	0	0	70042	69781	59716	25	40018	30016	10002	30010	10000	617045	3342542	0	49	66977	0	70102	70058	64675	3	64982	40010	30020	10000	60020	10000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	3	1	10002	0	1	1	1	10000	1	1	1	1	0	0	2520	1	71	1	1	69820	30006	10	0	0	10000	30010	70042	70042	70042	70058	70058
40024	70072	524	1	1	1	0	0	0	2	0	0	0	0	70026	69781	59701	25	40014	30013	10002	30010	10000	617045	3342542	0	49	66977	0	70118	70096	64680	3	64982	40010	30020	10000	60020	10000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10003	2	0	10002	0	0	2	1	10000	1	1	0	1	1	0	2520	1	71	1	1	69820	30015	10	10	10	10000	30010	70058	70058	70059	70042	70042

Test 3: throughput

Count: 8

Code:

  ldurb w0, [x6, #1]
  ldurb w0, [x6, #1]
  ldurb w0, [x6, #1]
  ldurb w0, [x6, #1]
  ldurb w0, [x6, #1]
  ldurb w0, [x6, #1]
  ldurb w0, [x6, #1]
  ldurb w0, [x6, #1]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	18	19	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26722	200	1	0	0	0	0	45	0	0	2	26704	2	12	18	0	25	80100	100	80000	100	80015	500	1167303	0	49	23642	0	26722	26727	16655	6	16674	80114	200	80024	200	80024	26727	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80035	0	39	80039	6	1	35	0	1	1	1	5118	0	16	0	0	26770	0	0	0	80000	100	26728	26708	26728	26728	26728
80204	26707	200	0	0	0	0	0	0	0	0	2	26723	2	12	0	16	25	80100	100	80000	100	80014	500	1165856	1	49	23632	0	26722	26707	16635	6	16679	80115	200	80024	200	80024	26727	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80039	0	39	80039	6	1	35	39	1	1	1	5118	0	16	0	0	26769	6	0	4	80000	100	26728	26723	26708	26728	26728
80204	26707	200	0	0	0	0	0	0	0	0	0	26707	2	12	0	16	25	80100	100	80000	100	80000	500	1166525	1	49	23627	0	26722	26707	16650	3	16685	80100	200	80000	200	80000	26727	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80000	0	0	80039	6	1	39	43	0	0	0	5110	1	16	1	1	26707	10	6	4	80000	100	26708	26708	26723	26728	26708
80204	26707	200	0	0	0	0	0	0	0	0	2	26712	0	12	0	16	25	80100	100	80000	100	80000	500	1177038	0	49	23627	0	26722	26727	16650	3	16685	80100	200	80000	200	80000	26727	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80035	0	39	80039	6	1	35	39	0	0	0	5110	1	16	1	4	26730	10	6	4	80000	100	26728	26728	26728	26728	26708
80204	26727	200	0	0	0	0	0	54	0	0	2	26712	0	12	12	16	25	80100	100	80000	100	80000	500	1167808	1	49	23647	0	26727	26727	16650	3	16665	80100	200	80000	200	80000	26707	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	0	0	80039	0	1	39	0	0	0	0	5110	1	16	1	1	26739	0	10	0	80000	100	26728	26708	26723	26728	26728
80204	26707	200	0	0	0	3	1	45	0	0	2	26712	2	18	0	0	25	80100	100	80000	100	80000	500	1177038	0	49	23647	0	26727	26727	16650	3	16685	80100	200	80000	200	80000	26707	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80039	0	39	80039	6	0	0	43	0	0	0	5110	1	16	1	1	26711	10	0	2	80000	100	26728	26708	26708	26708	26708
80204	26722	200	0	0	0	0	0	45	0	0	2	26712	0	0	0	16	25	80100	100	80000	100	80000	500	1166525	0	49	23647	0	26727	26727	16650	3	16685	80100	200	80000	200	80000	26707	71	1	1	80201	100	99	100	80000	100	80000	1	100	80000	39	80035	0	0	80000	6	1	35	0	0	0	0	5110	1	16	1	1	26714	10	6	0	80000	100	26728	26728	26708	26723	26728
80204	26727	200	1	1	0	0	0	45	0	0	0	26694	2	0	18	0	25	80100	100	80000	100	80000	500	1166525	0	49	23647	0	26727	26727	16650	3	16686	80100	200	80000	200	80000	26707	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80000	0	0	80039	6	1	35	0	0	0	0	5110	1	16	1	1	26817	6	0	0	80000	100	26708	26723	26723	26728	26708
80204	26722	200	0	0	0	0	0	45	0	0	2	26692	2	0	0	16	25	80100	100	80000	100	80000	500	1165789	0	49	23647	0	26707	26727	16650	3	16665	80100	200	80000	200	80000	26707	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80039	0	39	80039	6	1	35	43	0	0	0	5110	1	16	1	1	26711	10	6	4	80000	100	26728	26728	26708	26708	26728
80204	26727	200	0	0	0	0	0	0	1	0	2	26692	2	12	12	16	25	80100	100	80000	100	80000	500	1166525	1	49	23627	0	26707	26722	16630	3	16665	80100	200	80000	200	80000	26727	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80039	0	39	80039	6	1	0	43	0	0	0	5110	1	16	1	1	26724	0	6	4	80000	100	26708	26708	26728	26728	26708

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26722	200	0	1	0	0	0	0	45	0	1	0	2	26707	2	18	18	16	25	80010	10	80000	10	80000	50	1166750	1	49	23647	26728	26728	16672	3	16707	80010	20	80000	20	80000	26727	71	1	1	80021	10	9	10	80000	10	80000	1	10	80000	39	80035	0	39	80039	6	1	35	39	0	5020	20	16	9	22	26891	10	6	2	80000	10	26728	26709	26729	26729	26709
80024	26727	200	0	0	0	0	0	0	45	0	0	0	1	26712	2	12	12	16	25	80010	10	80000	10	80000	50	1167605	0	49	23648	26728	26722	16652	3	16707	80010	20	80000	20	80000	26727	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80000	0	0	80000	6	1	35	0	0	5020	22	16	11	22	26881	0	10	2	80000	10	26723	26728	26709	26723	26729
80024	26708	200	0	0	0	0	0	0	257	108	1	0	1	26713	0	12	12	16	25	80010	10	80000	10	80000	50	1166750	0	49	23647	26727	26722	16672	3	16702	80010	20	80000	20	80000	26708	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80000	0	0	80000	6	0	35	43	1	5020	9	16	22	11	26728	0	6	2	80000	10	26709	26709	26728	26729	26709
80024	26727	200	0	0	0	0	0	0	0	0	0	0	2	26693	0	12	0	12	25	80010	10	80000	10	80000	50	1166886	0	49	23647	26728	26708	16652	3	16707	80010	20	80000	20	80000	26728	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80000	0	44	80035	0	0	0	43	0	5020	22	16	11	22	26851	0	6	2	80000	10	26709	26709	26729	26729	26709
80024	26722	200	0	0	0	0	0	0	45	0	0	0	1	26707	0	12	12	16	25	80010	10	80000	10	80000	50	1166750	0	49	23628	26727	26708	16652	3	16707	80010	20	80000	20	80000	26727	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80000	0	39	80000	6	0	0	43	0	5020	22	16	22	9	26890	10	0	0	80000	10	26729	26723	26723	26728	26729
80024	26728	200	0	0	0	0	0	0	0	0	1	0	1	26712	2	12	12	16	25	80010	10	80000	10	80000	50	1168843	0	49	23628	26728	26727	16672	3	16708	80010	20	80000	20	80000	26708	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80039	0	0	80000	6	0	35	43	0	5020	10	16	11	22	26790	6	6	0	80000	10	26728	26728	26709	26709	26729
80024	26708	200	0	0	0	0	0	0	45	0	1	0	2	26693	2	12	12	16	25	80010	10	80000	10	80000	50	1168843	0	49	23628	26727	26727	16672	3	16707	80010	20	80000	20	80000	26728	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80035	0	0	80000	0	1	35	43	0	5020	22	16	22	10	26705	0	6	4	80000	10	26709	26709	26729	26729	26728
80024	26727	200	0	0	0	0	0	0	212	0	0	0	2	26693	2	18	12	16	25	80010	10	80000	10	80000	50	1166886	0	49	23628	26708	26727	16652	3	16707	80010	20	80000	20	80000	26728	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80000	0	39	80035	6	0	35	43	0	5020	22	16	22	11	27091	6	10	2	80000	10	26728	26710	26873	26932	26709
80024	26708	200	0	0	1	0	0	0	0	0	0	0	1	26721	2	18	12	16	48	80140	10	80000	10	80000	50	1166886	1	49	23651	26732	26728	16672	3	16688	80010	20	80000	20	80000	26708	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80040	1	3	80039	6	0	39	0	0	5020	22	16	22	22	26724	0	0	0	80000	10	26732	26729	26709	26729	26709
80024	26708	200	0	0	0	0	1	0	45	0	1	0	2	26866	2	18	0	2	25	80010	10	80000	10	80000	50	1166352	1	49	23648	26722	26727	16667	3	16707	80010	20	80000	20	80000	26727	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80000	0	0	80039	6	1	35	0	0	5020	9	16	22	11	26705	10	6	4	80000	10	26728	26709	26723	26732	26732

LDURB

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations