Firestorm: STR (unsigned offset, 32-bit) measurements

Code:

  str w0, [x6, #8]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	1f	22	23	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	551	4	0	0	3	1	0	525	16	0	0	25	1000	1000	1000	22424	0	550	540	362	3	398	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	34	1002	0	8	1002	0	34	73	2	16	2	2	548	1000	541	551	552	541	543
1004	540	4	0	0	0	1	0	536	16	0	0	25	1000	1000	1000	22424	0	542	542	355	3	398	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	34	1002	0	2	1002	0	0	75	2	16	2	2	539	1000	543	543	543	541	543
1004	549	4	0	0	0	1	0	525	0	0	0	25	1000	1000	1000	22424	0	549	542	353	3	400	1000	1000	2000	540	542	1	1	1001	1000	1000	1000	0	1002	0	8	1002	2	0	73	2	16	2	2	537	1000	543	543	543	541	543
1004	542	4	0	0	0	0	0	535	0	16	0	25	1000	1000	1000	22424	0	540	542	353	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	34	1000	0	0	1002	0	0	73	2	16	2	2	539	1000	543	551	541	543	541
1004	540	4	0	0	3	0	0	527	16	16	0	25	1000	1000	1000	23217	0	540	549	353	3	398	1000	1000	2000	542	549	1	1	1001	1000	1000	1000	0	1012	0	0	1002	0	34	73	2	16	2	2	539	1000	550	543	543	543	541
1004	540	4	0	0	9	0	0	527	16	0	0	25	1000	1000	1000	22424	0	540	550	353	3	398	1000	1000	2000	542	540	1	1	1001	1000	1000	1000	0	1002	0	2	1002	0	34	75	3	16	3	2	539	1000	551	552	541	541	543
1004	542	4	0	6	3	0	0	525	16	16	0	25	1000	1000	1000	22352	0	540	540	362	3	398	1000	1000	2000	542	540	1	1	1001	1000	1000	1000	34	1002	0	5	1002	2	34	75	2	16	2	2	539	1000	550	541	543	543	543
1004	542	4	0	0	3	0	0	527	16	16	0	25	1000	1000	1000	22424	0	550	540	353	3	398	1000	1000	2000	540	542	1	1	1001	1000	1000	1000	34	1002	0	2	1002	2	34	75	2	16	2	3	537	1000	541	543	543	543	543
1004	549	4	0	0	9	0	0	535	0	16	0	25	1000	1000	1000	22352	0	542	540	353	3	398	1000	1000	2000	540	540	1	1	1001	1000	1000	1000	34	1002	1	8	1002	0	34	75	2	16	2	2	547	1000	552	541	541	543	543
1004	542	4	0	0	3	1	0	527	0	0	0	25	1000	1000	1000	22424	0	549	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	1000	0	2	1002	2	34	75	2	16	2	2	539	1000	552	543	543	541	543

Count: 8

Code:

  str w0, [x6, #8]
  str w0, [x6, #8]
  str w0, [x6, #8]
  str w0, [x6, #8]
  str w0, [x6, #8]
  str w0, [x6, #8]
  str w0, [x6, #8]
  str w0, [x6, #8]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	18	19	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40042	300	1	0	0	0	0	0	0	3	1	0	0	40028	16	16	1	25	80100	100	80000	100	80000	500	1839448	0	49	36962	40042	40042	29955	3	30000	80100	200	80000	200	160000	40043	31996	1	1	80201	100	99	100	80000	100	80000	100	80000	42	80002	0	2	80002	0	42	0	5110	3	16	3	3	40039	80000	100	40044	40044	40043	40041	40043
80204	40042	300	0	0	0	0	0	0	0	3	1	0	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839448	0	49	36963	40043	40043	29955	3	30001	80100	200	80000	200	160000	40040	31996	1	1	80201	100	99	100	80000	100	80000	100	80000	42	80002	0	2	80002	2	42	0	5110	3	16	3	3	40039	80000	100	40043	40043	40044	40044	40043
80204	40043	300	0	0	0	0	0	0	0	3	0	0	0	40027	16	16	1	25	80100	100	80000	100	80000	500	1839352	0	49	36962	40042	40054	29955	3	29998	80100	200	80000	200	160000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	42	80002	0	2	80000	2	42	0	5110	3	16	3	3	40039	80000	100	40043	40043	40043	40041	40043
80204	40042	299	0	0	0	0	0	0	0	3	1	0	0	40028	16	16	1	25	80100	100	80000	100	80000	500	1839472	0	49	36962	40042	40040	29953	3	30000	80100	200	80000	200	160000	40121	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	42	80002	0	2	80002	2	42	0	5110	3	16	3	3	40039	80000	100	40041	40043	40044	40044	40043
80204	40043	300	0	0	0	0	0	0	0	0	1	0	0	40028	16	16	1	25	80100	100	80000	100	80000	500	1839472	0	49	36962	40043	40043	29955	3	30000	80100	200	80000	200	160000	40043	31993	1	1	80201	100	99	100	80000	100	80000	100	80060	42	80002	0	5	80002	2	0	0	5110	3	16	3	3	40040	80000	100	40044	40041	40043	40043	40043
80204	40042	300	0	0	0	0	0	0	0	3	1	0	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839448	0	49	36963	40042	40043	29955	3	30001	80100	200	80000	200	160000	40042	31996	1	1	80201	100	99	100	80000	100	80000	100	80000	0	80002	0	2	80002	0	0	0	5110	3	16	3	3	40040	80000	100	40044	40044	40043	40043	40043
80204	40042	300	0	0	0	0	0	0	0	3	1	0	0	40028	16	16	0	25	80100	100	80000	100	80000	500	1839472	0	49	36960	40042	40042	29955	3	30000	80100	200	80000	200	160000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	42	80002	0	2	80002	2	42	1	5110	3	16	3	3	40040	80000	100	40044	40041	40043	40044	40043
80204	40040	300	0	0	0	0	0	0	0	3	0	0	0	40025	16	16	1	25	80100	100	80000	100	80000	500	1839448	0	49	36962	40054	40042	29955	3	30000	80100	200	80000	200	160000	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	80002	0	2	80002	2	42	0	5110	3	16	3	3	40039	80000	100	40043	40055	40043	40041	40043
80204	40042	300	0	0	0	0	0	0	0	3	1	0	0	40027	16	16	1	25	80100	100	80000	100	80000	500	1839352	0	49	36962	40042	40054	29955	3	30000	80100	200	80000	200	160238	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	42	80002	0	0	80002	2	42	0	5110	3	16	3	3	40040	80000	100	40041	40043	40043	40044	40043
80204	40054	300	0	0	0	0	0	0	0	0	0	0	0	40028	0	16	0	25	80100	100	80000	100	80000	500	1839448	0	49	36974	40042	40042	29955	3	29998	80100	200	80000	200	160000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	42	80002	0	2	80002	2	42	0	5110	3	16	3	3	40039	80000	100	40043	40041	40043	40043	40043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	18	1e	1f	22	23	24	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40042	300	0	0	0	3	1	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839448	1	49	36962	40042	40042	29977	3	30023	80010	20	80000	20	160000	40040	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	80002	9	5	80002	2	0	5020	2	16	0	3	4	40039	80000	10	40043	40044	40044	40043	40041
80024	40042	300	0	0	0	3	0	0	0	40025	16	16	0	25	80010	10	80000	10	80000	50	1839472	1	49	36962	40040	40042	29977	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	80002	0	6	80002	2	42	5020	2	16	0	1	3	40040	80000	10	40043	40044	40044	40043	40043
80024	40054	300	0	0	0	0	0	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839448	1	49	36962	40042	40042	29977	3	30020	80010	20	80000	20	160000	40043	40043	1	1	80021	10	9	10	80000	10	80000	10	80000	42	0	80002	0	8	80002	2	0	5038	1	16	0	1	3	40282	80000	10	40044	40043	40041	40044	40046
80024	40181	301	1	0	144	0	1	0	0	40025	16	0	0	25	80010	10	80000	10	80000	50	1839472	1	49	37122	40043	40043	29977	3	30020	80010	20	80000	20	160000	40043	40043	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	80002	0	11	80002	0	42	5020	2	16	0	3	4	40039	80000	10	40044	40044	40043	40043	40041
80024	40040	300	0	0	0	3	1	0	0	40025	16	0	0	25	80010	10	80000	10	80000	50	1839472	1	49	36962	40042	40040	29977	3	30022	80010	20	80000	20	160000	40042	40043	1	1	80021	10	9	10	80000	10	80000	10	80000	42	0	80002	1	102	80002	12	42	5020	1	16	0	1	3	40040	80000	10	40044	40044	40043	40043	40043
80024	40043	300	0	0	0	3	1	0	0	40027	16	16	1	25	80010	10	80000	10	80000	50	1839448	1	49	36962	40042	40042	29977	3	30022	80010	20	80000	20	160000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	42	0	80000	6	0	80002	2	42	5020	1	16	0	1	3	40039	80000	10	40041	40043	40044	40043	40041
80024	40042	300	0	0	0	7	0	0	0	40025	16	0	1	25	80010	10	80000	10	80000	50	1839448	1	49	36962	40042	40042	29975	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	42	0	80000	8	2	80002	2	42	5020	1	16	0	1	3	40039	80000	10	40043	40043	40043	40043	40043
80024	40043	300	0	0	0	3	0	0	0	40028	16	16	0	25	80010	10	80000	10	80000	50	1839352	1	49	36960	40040	40042	29977	3	30034	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	42	0	80002	6	11	80002	0	42	5020	4	16	0	5	4	40037	80000	10	40043	40044	40044	40043	40053
80024	40042	300	0	0	0	3	1	0	0	40025	16	16	1	25	80010	10	80000	10	80000	50	1839448	1	49	36963	40042	40042	29978	3	30023	80010	20	80000	20	160000	40042	40043	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	80002	7	14	80000	2	0	5020	2	16	0	3	4	40039	80000	10	40043	40041	40044	40044	40041
80024	40042	300	0	0	0	3	0	0	0	40028	0	16	0	25	80010	10	80000	10	80000	50	1839448	1	49	36962	40042	40042	29977	3	30022	80010	20	80000	20	160000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	42	0	80000	3	8	80002	2	42	5020	4	16	0	4	2	40039	80000	10	40041	40041	40055	40043	40043

STR (unsigned offset, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations