Firestorm: LDRSB (register, sxtw, 32-bit) measurements

Code:

  ldrsb w0, [x6, w7, sxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	399	3	1	0	1	1	68	0	0	2	384	2	18	18	17	25	1000	1000	1000	15375	398	399	221	3	257	1000	1000	2000	399	83	1	1	1001	1000	1000	1020	22	42	1057	0	0	0	58	1038	6	1	57	42	19	1	73	1	16	1	1	395	9	9	2	1000	399	400	400	400	399
1004	399	3	1	1	1	1	65	1	0	3	383	2	18	18	17	25	1000	1000	1000	15320	399	399	221	3	257	1000	1000	2000	399	82	1	1	1001	1000	1000	1020	20	41	1057	1	0	1	59	1038	6	1	57	42	19	1	73	1	16	1	1	395	9	9	2	1000	400	400	399	400	400
1004	399	3	1	0	1	0	65	0	0	3	383	2	18	18	16	25	1000	1000	1000	15362	399	399	221	3	256	1000	1000	2000	399	81	1	1	1001	1000	1000	1020	20	42	1057	1	0	0	59	1038	6	1	57	42	19	1	73	1	16	1	1	397	9	9	2	1000	400	403	400	399	400
1004	399	2	1	1	1	1	65	0	0	2	383	2	18	18	16	25	1000	1000	1000	15362	399	399	221	3	256	1000	1000	2000	399	81	1	1	1001	1000	1000	1021	19	42	1057	1	1	1	59	1037	6	1	57	42	19	0	73	1	16	1	1	395	9	9	2	1000	399	400	400	400	400
1004	399	3	1	1	1	1	65	1	0	3	384	3	18	18	16	25	1000	1000	1000	15375	399	398	222	3	257	1000	1000	2000	398	81	1	1	1001	1000	1000	1019	21	42	1057	1	0	0	59	1038	6	1	57	41	19	2	73	1	16	1	1	396	9	9	2	1000	400	400	401	400	399
1004	398	3	1	0	0	1	77	0	0	3	383	2	18	18	17	25	1000	1000	1000	15328	399	399	221	3	257	1000	1000	2000	399	81	1	1	1001	1000	1000	1019	20	42	1057	0	0	0	59	1038	6	1	54	42	19	1	73	1	16	1	1	396	9	9	2	1000	400	400	399	400	400
1004	399	3	1	1	1	1	65	0	0	2	384	3	18	18	16	25	1000	1000	1000	15375	398	399	221	3	257	1000	1000	2000	399	81	1	1	1001	1000	1000	1019	19	42	1057	1	0	2	59	1038	6	1	57	42	19	2	73	1	16	1	1	397	9	9	2	1000	400	399	400	400	399
1004	398	3	1	0	0	1	65	0	0	2	383	2	18	18	15	25	1000	1000	1000	15958	399	399	222	3	256	1000	1000	2000	399	81	1	1	1001	1000	1000	1020	20	42	1057	0	0	0	59	1038	6	1	56	42	19	0	73	1	16	1	1	396	9	9	2	1000	400	399	400	400	399
1004	398	3	1	0	0	1	65	0	0	3	385	2	18	18	16	25	1000	1000	1000	15315	398	399	223	3	257	1000	1000	2000	399	81	1	1	1001	1000	1000	1021	21	42	1058	1	0	1	59	1038	6	1	58	42	19	1	73	1	16	1	1	396	9	9	2	1000	400	400	400	399	400
1004	399	3	1	1	1	1	65	1	0	3	385	2	18	18	16	25	1000	1000	1000	15315	399	400	229	3	257	1000	1000	2000	399	81	1	1	1001	1000	1000	1019	19	42	1057	0	0	0	59	1038	6	1	57	42	19	1	73	1	16	1	1	396	9	9	2	1000	400	400	399	400	400

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb w0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70050	525	0	0	0	0	0	1	0	1	0	70035	69781	59706	25	40104	30103	10002	30100	10000	616680	3345326	1	49	66970	0	70050	70050	64631	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	0	1	0	2610	3	71	2	2	69810	30003	6	6	9	10000	30100	70036	70036	70036	70051	70051
40204	70047	525	0	0	0	0	0	1	0	0	0	70035	69781	59801	25	40104	30103	10001	30100	10000	616726	3342686	1	49	66967	0	70047	70035	64643	3	64953	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	0	1	0	2610	2	71	2	2	69813	30003	9	6	9	10000	30100	70051	70036	70130	70063	70059
40204	70050	525	0	0	0	0	0	1	0	0	0	70032	69735	59706	25	40104	30103	10001	30100	10000	616896	3343006	1	49	66970	0	70050	70050	64646	3	64953	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10001	0	0	10000	1	0	1	0	2610	2	71	2	2	69813	30003	9	9	9	10000	30100	70051	70051	70051	70051	70051
40204	70050	524	0	0	0	1	0	0	0	0	0	70035	69735	59709	25	40116	30100	10001	30100	10000	616717	3345278	1	49	66970	0	70059	70050	64652	3	64950	40100	30200	10000	60536	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	0	1	0	2610	2	71	2	2	69813	30003	0	9	6	10000	30100	70048	70048	70051	70048	70048
40204	70047	524	0	0	0	0	0	1	0	0	0	70035	69782	59709	25	40104	30103	10001	30100	10000	616591	3342590	1	49	66970	0	70050	70050	64643	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	0	1	0	2610	2	71	2	2	69813	30006	0	6	0	10000	30100	70036	70051	70036	70051	70051
40204	70050	525	0	0	0	0	0	1	0	0	1	70035	69781	59709	25	40104	30103	10001	30100	10000	616015	3347198	1	49	66970	0	70035	70050	64646	3	64953	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	0	1	0	2610	2	71	2	2	69813	30003	9	6	9	10000	30100	70051	70051	70051	70051	70051
40204	70050	525	0	0	0	0	0	1	0	0	0	70020	69764	59709	25	40104	30103	10001	30100	10000	616015	3346094	1	49	66967	0	70050	70050	64643	3	64953	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	0	0	0	2610	2	71	2	2	69813	30003	9	6	9	10000	30100	70051	70036	70036	70051	70059
40204	70050	525	0	0	0	1	0	1	0	0	0	70032	69781	59706	25	40104	30103	10001	30100	10000	616015	3342062	1	49	66955	0	70050	70050	64646	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	0	1	0	2610	2	71	2	2	69810	30003	9	9	9	10000	30100	70048	70048	70051	70051	70048
40204	70050	524	0	0	0	0	0	1	0	0	0	70035	69781	59709	25	40104	30103	10000	30100	10000	616005	3346526	1	49	66970	0	70050	70050	64631	3	64958	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	0	0	0	2610	2	71	2	2	69813	30003	9	0	9	10000	30100	70051	70051	70051	70051	70036
40204	70050	525	0	0	0	1	0	1	0	0	1	70035	69781	59709	25	40104	30100	10002	30100	10000	616015	3345758	1	49	66970	0	70050	70047	64643	3	64953	40100	30200	10000	60200	20000	70050	35	2	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	0	1	0	2610	2	71	2	2	69813	30003	9	6	9	10000	30100	70036	70051	70051	70048	70051

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70053	524	1	0	1	1	1	0	0	0	2	0	0	0	70026	69780	59701	25	40014	30016	10002	30010	10000	616995	3341769	1	49	66976	0	70056	70056	64671	0	3	64966	40010	30020	10000	60020	20000	70056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	1	10002	0	0	1	10000	1	1	1	1	0	2523	9	71	3	5	69819	30006	9	6	9	10000	30010	70042	70042	70054	70054	70042
40024	70056	524	1	0	0	0	0	0	1	0	1	0	0	0	70041	69702	59715	25	40014	30016	10001	30010	10000	616995	3342494	0	49	66973	0	70053	70056	64674	0	3	64981	40010	30020	10000	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	0	10001	0	0	1	10000	1	1	1	1	0	2523	6	71	6	5	69819	30006	0	9	0	10000	30010	70057	70042	70054	70057	70057
40024	70111	525	1	0	0	1	0	0	0	0	2	0	0	0	70026	69780	59715	25	40018	30016	10002	30010	10000	616995	3341769	0	49	66977	0	70053	70056	64671	0	3	64966	40010	30020	10000	60020	20000	70056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10003	1	1	10003	0	0	1	10000	1	1	1	1	1	2525	4	71	7	4	69804	30003	9	0	9	10000	30010	70057	70042	70042	70057	70042
40024	70041	525	1	0	0	1	1	0	0	0	2	1	0	0	70041	69780	59715	25	40014	30013	10002	30010	10000	617036	3342494	0	49	66961	0	70056	70041	64674	0	3	64981	40010	30020	10000	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	1	10002	0	1	4	10000	1	1	1	1	0	2523	3	71	5	3	69819	30003	6	9	6	10000	30010	70054	70042	70054	70054	70057
40024	70056	524	1	0	0	0	0	0	0	0	2	0	0	0	70041	69777	59701	25	40018	30016	10004	30010	10000	617009	3342494	0	49	66976	0	70056	70056	64659	0	3	64981	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	3	0	10001	0	1	10	10000	1	1	1	1	1	2523	2	71	6	5	69804	30006	9	6	0	10000	30010	70057	70058	70057	70057	70057
40024	70056	526	1	0	1	1	0	0	0	0	2	1	0	0	70041	69780	59715	25	40018	30016	10001	30010	10000	617036	3342494	0	49	66976	0	70056	70053	64674	0	3	64966	40010	30020	10000	60020	20000	70056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10001	0	0	1	10000	1	1	1	1	0	2523	5	71	3	4	69819	30006	9	0	0	10000	30010	70042	70057	70054	70054	70057
40024	70056	525	1	0	1	0	1	0	0	0	1	1	0	0	70031	69777	59715	25	40014	30016	10001	30010	10000	617009	3342494	0	49	66976	0	70056	70056	64674	0	3	64966	40010	30020	10000	60020	20000	70056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	1	10002	0	1	1	10000	1	1	1	1	0	2523	5	71	3	4	69820	30003	9	9	0	10000	30010	70057	70057	70042	70057	70057
40024	70056	524	1	0	1	1	1	0	0	0	2	0	0	0	70026	69780	59715	25	40018	30013	10002	30010	10000	617036	3342494	0	49	66976	0	70041	70056	64674	0	3	64981	40010	30020	10000	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	3	1	10001	0	1	1	10000	1	1	1	1	1	2523	4	71	5	4	69819	30006	9	6	9	10000	30010	70042	70057	70057	70042	70057
40024	70056	525	1	0	1	0	0	0	0	0	2	0	0	0	70038	69777	59715	25	40018	30016	10002	30010	10000	617036	3342494	0	49	66973	0	70056	70041	64671	0	3	64978	40010	30020	10000	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	3	1	10001	0	1	1	10000	1	1	1	1	1	2525	6	71	4	6	69819	30006	9	9	0	10000	30010	70057	70057	70057	70057	70042
40024	70056	525	1	0	0	0	0	0	0	0	1	0	0	1	70041	69780	59715	25	40018	30013	10001	30010	10000	617036	3342494	0	49	66976	0	70058	70056	64685	0	3	64981	40010	30020	10000	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10002	0	1	1	10000	1	1	0	1	1	2523	3	71	4	5	69819	30003	9	6	0	10000	30010	70057	70057	70054	70057	70057

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb w0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	0e	0f	19	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70047	525	1	1	0	1	0	0	1	0	3	70035	69735	59723	25	40104	30103	10002	30100	10000	616015	3342206	49	66955	70035	70035	64646	0	3	64938	40100	30200	10000	60200	20000	70050	80	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	0	0	0	2616	10	71	10	10	69798	30003	0	6	9	10000	30100	70051	70051	70048	70123	70036
40204	70050	524	1	1	1	0	0	1	1	0	3	70035	69735	59734	25	40100	30103	10001	30100	10000	616193	3342206	49	66970	70050	70047	64646	0	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10003	0	10000	4	12	10000	1	1	1	0	2616	9	17	9	9	69813	30003	6	6	6	10000	30100	70051	70048	70048	70138	70051
40204	70050	525	1	1	0	0	0	1	0	0	3	70035	69735	59734	25	40104	30103	10001	30100	10000	616015	3342062	49	66970	70047	70035	64643	0	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	1	0	0	2616	9	71	9	9	69813	30003	9	0	6	10000	30100	70051	70051	70048	70121	70048
40204	70050	525	1	1	0	0	0	0	1	0	3	70032	69764	59743	25	40104	30103	10001	30100	10000	616175	3342206	49	66970	70050	70050	64631	0	3	64953	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	3	10000	1	1	0	0	2616	9	71	5	9	69813	30003	9	9	9	10000	30100	70036	70048	70048	70142	70052
40204	70050	525	1	1	0	0	0	1	0	0	3	70035	69735	59701	25	40104	30103	10000	30100	10000	616015	3341470	49	66970	70037	70035	64631	0	3	64938	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	0	2616	9	71	9	4	69810	30003	9	6	9	10000	30100	70036	70036	70074	70036	70048
40204	70050	524	1	1	0	0	0	1	0	0	3	70020	69781	59728	25	40100	30100	10001	30100	10000	616005	3342206	49	66970	70050	70050	64643	0	3	64953	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	0	0	0	0	2616	9	71	9	9	69813	30000	9	6	9	10000	30100	70051	70036	70048	70118	70051
40204	70035	525	1	1	0	0	0	0	0	0	3	70035	69764	59760	25	40104	30103	10001	30100	10000	616175	3342206	49	66967	70050	70035	64646	0	3	64950	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	0	1	0	0	2616	9	71	7	7	69798	30000	0	6	9	10000	30100	70051	70051	70048	70062	70036
40204	70050	525	1	1	0	0	0	0	0	1	3	70098	69781	59757	25	40104	30103	10001	30100	10000	616005	3342206	49	66970	70095	70040	64633	0	3	64940	40100	30200	10000	60200	20000	70050	35	2	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	0	1	0	0	2616	5	71	9	9	69813	30003	0	6	0	10000	30100	70036	70051	70048	70132	70036
40204	70050	525	1	1	0	0	0	0	0	0	3	70035	69735	59743	25	40104	30103	10001	30100	10000	616005	3342206	49	66970	70035	70050	64646	0	3	64950	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	0	1	0	0	2616	10	71	9	10	69813	30000	6	0	9	10000	30100	70051	70036	70048	70139	70052
40204	70050	524	1	1	1	0	0	171	0	0	3	70035	69764	59776	25	40104	30100	10001	30100	10000	616015	3342062	49	66970	70050	70050	64643	0	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	10000	1	0	0	0	2616	7	71	9	9	69810	30003	6	6	0	10000	30100	70036	70051	70051	70124	70036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70051	525	0	0	1	0	0	0	0	0	1	1	0	0	70039	69743	59710	25	40014	30013	10001	30010	10000	616991	3342398	0	49	66955	70051	70051	64672	3	64983	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	2520	6	71	1	1	69814	30003	10	10	10	10000	30010	70052	70052	70052	70052	70052
40024	70051	524	0	0	0	0	0	0	0	0	6	0	0	0	70042	69775	59713	25	40014	30013	10004	30010	10000	617054	3342302	0	49	66971	70035	70051	64653	3	64998	40010	30020	10000	60020	20132	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	1	10002	0	1	1	10000	0	1	1	1	2	2520	1	17	2	1	69814	30003	10	10	10	10000	30010	70052	70052	70052	70036	70052
40024	70051	524	0	0	0	0	0	1	0	0	1	1	0	1	70042	69781	59716	25	40018	30016	10002	30010	10000	617045	3342542	0	49	66971	70054	70051	64672	3	65024	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	0	0	1	0	0	2520	1	71	1	1	69820	30006	10	10	10	10000	30010	70058	70058	70042	70042	70042
40024	70057	525	1	1	0	0	0	0	0	0	2	1	0	0	70036	69743	59710	25	40014	30013	10001	30010	10000	617018	3341470	0	49	66971	70051	70051	64672	3	65020	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	2520	1	71	1	1	69814	30003	10	10	10	10000	30010	70052	70055	70052	70052	70052
40024	70096	525	0	0	0	0	0	0	0	0	1	1	0	0	70026	69781	59701	25	40018	30013	10002	30010	10000	617072	3342686	0	49	66977	70057	70041	64675	3	65053	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	1	0	0	10000	1	0	1	0	0	2520	1	71	1	1	69820	30006	10	10	10	10000	30010	70058	70061	70058	70061	70058
40024	70057	524	1	0	1	1	0	0	0	0	7	1	0	0	70036	69775	59710	25	40014	30013	10001	30010	10000	616991	3342254	0	49	66971	70051	70051	64669	3	65013	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	2520	2	71	2	1	69814	30000	10	10	10	10000	30010	70052	70052	70052	70052	70052
40024	70051	525	0	0	0	0	0	0	0	0	1	0	0	0	70036	69743	59710	25	40014	30013	10001	30163	10000	616991	3342254	0	49	66971	70051	70054	64669	3	65005	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	0	0	1	0	0	2520	1	71	1	1	69814	30003	13	10	10	10000	30010	70052	70052	70052	70055	70052
40024	70051	525	0	0	0	0	0	0	0	0	1	1	0	0	70036	69775	59710	25	40014	30013	10001	30010	10000	616991	3342254	0	49	66971	70054	70051	64669	3	65043	40010	30020	10000	60020	20000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	2520	1	71	1	1	69814	30003	10	10	13	10000	30010	70036	70052	70055	70055	70052
40024	70051	524	0	0	0	0	0	0	0	0	1	0	0	0	70036	69775	59710	25	40014	30013	10001	30010	10000	616991	3342254	0	49	66971	70054	70051	64669	3	65015	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	2520	1	71	1	1	69820	30003	10	10	10	10000	30010	70055	70052	70052	70052	70036
40024	70051	525	0	0	0	0	0	0	0	0	1	1	0	0	70036	69775	59710	25	40014	30013	10001	30010	10000	616991	3342254	0	49	66983	70051	70055	64653	3	65005	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	2520	1	71	1	1	69814	30003	10	10	10	10000	30010	70052	70052	70052	70036	70052

Test 4: throughput

Count: 8

Code:

  ldrsb w0, [x6, w7, sxtw]
  ldrsb w0, [x6, w7, sxtw]
  ldrsb w0, [x6, w7, sxtw]
  ldrsb w0, [x6, w7, sxtw]
  ldrsb w0, [x6, w7, sxtw]
  ldrsb w0, [x6, w7, sxtw]
  ldrsb w0, [x6, w7, sxtw]
  ldrsb w0, [x6, w7, sxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26736	200	1	0	0	1	1	1	1	67	1	0	3	26721	0	7	7	63	25	80100	100	80000	100	80016	500	1167628	0	49	23656	0	26736	26736	16663	6	16689	80115	200	80024	200	160048	26714	64	1	1	80201	100	99	100	80000	100	80000	1	100	80019	20	43	80059	1	0	0	21	80040	6	1	59	43	19	0	1	1	1	5118	0	16	0	0	26733	13	0	5	80000	100	26737	26808	26737	26739	26716
80204	26736	200	1	0	1	1	1	0	0	21	1	0	3	26722	3	7	7	25	25	80100	100	80000	100	80015	500	1167215	0	49	23634	0	26714	26736	16664	6	16688	80113	200	80024	200	160048	26737	85	1	1	80201	100	99	100	80000	100	80000	1	100	80020	19	0	80061	0	0	1	64	80000	0	0	59	0	19	1	1	1	1	5118	0	16	0	0	26733	0	0	5	80000	100	26737	26750	26746	26742	26739
80204	26736	200	1	0	0	0	1	0	0	67	1	0	2	26721	2	0	7	23	25	80100	100	80000	100	80013	500	1182551	0	49	23634	0	26736	26736	16664	6	16688	80115	200	80024	200	160048	26714	86	1	1	80201	100	99	100	80000	100	80000	0	100	80019	19	43	80059	1	0	1	61	80039	6	0	59	0	19	0	1	1	1	5118	0	16	0	0	26711	0	0	5	80000	100	26740	26723	26724	26739	26737
80204	26736	200	1	0	0	1	1	0	0	66	0	0	1	26721	0	7	7	5	25	80100	100	80000	100	80015	500	1167628	0	49	23656	0	26736	26714	16663	6	16689	80116	200	80024	200	160048	26736	86	1	1	80201	100	99	100	80000	100	80000	1	100	80019	19	43	80019	0	0	1	21	80000	6	1	58	0	19	1	1	1	1	5118	0	16	0	0	26733	13	0	0	80000	100	26718	26743	26725	26737	26715
80204	26736	200	1	0	0	0	0	0	0	21	1	0	1	26721	0	0	7	25	25	80100	100	80000	100	80015	500	1167215	0	49	23634	0	26737	26736	16664	6	16666	80115	200	80024	200	160048	26714	85	1	1	80201	100	99	100	80000	100	80000	1	100	80020	19	43	80060	1	0	0	61	80039	6	1	59	43	19	0	1	1	1	5118	0	16	0	0	26733	13	13	5	80000	100	26742	26737	27019	26819	26741
80204	26719	200	1	0	1	1	1	0	0	66	1	0	3	26722	0	9	0	21	25	80100	100	80000	100	80015	500	1167215	0	49	23810	0	26736	26736	16642	6	16666	80113	200	80024	200	160048	26736	85	1	1	80201	100	99	100	80000	100	80000	0	100	80020	19	0	80019	1	1	1	21	80040	0	1	19	0	19	0	1	1	1	5118	0	16	0	0	26711	10	10	4	80000	100	26736	26834	26730	26708	26737
80204	26727	200	0	0	0	0	0	0	0	675	1	0	0	26712	2	0	0	19	25	80100	100	80000	100	80014	500	1166596	0	49	23627	0	26727	26727	16635	6	16659	80115	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	0	0	0	80000	6	1	0	43	0	0	1	1	1	5118	0	16	0	0	26704	10	0	4	80000	100	26731	26715	26716	26728	26728
80204	26707	200	0	0	0	0	0	0	0	45	1	0	1	26712	2	12	12	5	25	80100	100	80000	100	80015	500	1167303	0	49	23647	0	26727	26727	16635	6	16659	80116	200	80024	200	160048	26707	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80000	0	0	0	39	80039	0	1	39	43	0	0	1	1	1	5118	0	16	0	0	26704	0	10	0	80000	100	26731	26734	26716	26731	26708
80204	26707	200	0	0	0	0	0	0	0	45	0	0	1	26712	2	12	12	8	25	80100	100	80000	100	80016	500	1166596	0	49	23647	0	26731	26731	16655	6	16682	80116	200	80024	200	160048	26707	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	0	0	39	80039	6	0	39	43	0	0	1	1	1	5118	0	16	0	0	26704	0	10	4	80000	100	26738	26714	26736	26732	26728
80204	26727	200	0	0	0	0	0	0	0	45	0	0	1	26712	0	12	12	21	25	80100	100	80000	100	80015	500	1167303	0	49	23647	0	26727	26727	16655	6	16679	80115	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80000	0	0	0	39	80040	0	0	39	0	0	0	1	1	1	5118	0	16	0	0	26704	0	10	0	80000	100	26714	26711	27026	26733	26718

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	1f	22	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26723	200	0	0	45	0	0	0	0	2	26707	2	0	12	12	25	80010	10	80000	10	80000	50	1168843	1	49	23642	0	26728	26727	16672	3	16813	80010	20	80000	20	160000	26728	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80039	0	0	80039	6	1	35	43	5020	8	16	0	4	2	26725	10	0	4	80000	10	26709	26729	26709	26723	26723
80024	26727	200	1	1	45	0	1	0	0	2	26712	0	12	18	16	25	80010	10	80000	10	80000	50	1166750	1	49	23642	0	26727	26727	16672	3	16830	80010	20	80000	20	160000	26708	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80000	0	0	80039	6	1	35	0	5043	2	16	0	4	4	26724	10	10	4	80000	10	26723	26728	26723	26729	26709
80024	26727	200	0	0	0	0	1	0	0	2	26713	2	0	12	12	25	80010	10	80000	10	80000	50	1168843	1	49	23649	0	26722	26727	16667	3	16820	80010	20	80000	20	160000	26727	72	1	1	80021	10	9	10	80000	10	80000	1	10	80000	39	80039	0	0	80035	0	0	39	43	5020	2	16	0	4	2	26705	10	10	4	80000	10	26709	26729	26729	26728	26729
80024	26728	200	0	0	45	0	1	0	0	0	26713	2	12	0	11	25	80010	10	80000	10	80000	50	1166750	1	49	23648	0	26708	26727	16672	3	16725	80010	20	80000	20	160000	26728	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80039	0	39	80039	6	1	39	39	5020	2	16	0	4	6	26724	0	6	2	80000	10	26723	26709	26709	26709	26709
80024	26708	200	0	0	45	0	1	0	0	0	26693	2	12	12	16	25	80010	10	80000	10	80000	50	1168843	1	49	23648	0	26728	26727	16652	3	16799	80010	20	80000	20	160000	26728	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80039	0	39	80039	6	0	0	0	5020	2	16	0	2	4	26724	10	10	4	80000	10	26723	26728	26709	26728	26729
80024	26708	200	0	0	0	0	0	0	0	0	26874	2	12	12	16	25	80010	10	80000	10	80000	50	1166750	1	49	23647	0	26727	26722	16672	3	16825	80010	20	80000	20	160000	26727	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80000	0	35	80040	6	1	39	43	5020	4	16	0	2	4	26719	0	0	2	80000	10	26723	26729	26729	26723	26723
80024	26722	200	0	0	0	0	1	0	0	2	26693	0	0	18	16	25	80010	10	80000	10	80000	50	1166886	1	49	23647	0	26728	26728	16652	3	16821	80010	20	80000	20	160000	26727	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80000	0	39	80039	6	1	35	43	5089	5	16	0	2	4	26724	10	0	4	80000	10	26728	26728	26728	26728	26709
80024	26728	200	0	0	45	0	0	0	0	2	26707	2	18	12	16	25	80010	10	80000	10	80000	50	1166896	1	49	23647	0	26708	26728	16667	3	16791	80010	20	80000	20	160000	26722	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80039	0	39	80169	6	0	0	0	5020	4	16	0	2	4	26705	0	10	0	80000	10	26723	26723	26729	26728	26728
80024	26728	200	0	0	57	0	1	0	0	1	26712	2	12	12	0	25	80010	10	80000	10	80000	50	1166896	1	49	23628	0	26727	26728	16672	3	16707	80010	20	80000	20	160000	26728	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80039	0	39	80000	6	1	35	43	5020	3	16	0	2	4	26705	18	10	4	80000	10	26729	26729	26709	26728	26728
80024	26722	201	0	0	45	0	1	0	0	2	26712	2	12	12	16	25	80010	10	80000	10	80000	50	1168843	1	49	23628	0	26728	26722	16652	3	16799	80010	20	80000	20	160000	26727	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80000	0	35	80039	0	1	35	43	5020	4	16	2	4	2	26724	0	10	0	80000	10	26709	26723	26728	26728	26724

LDRSB (register, sxtw, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations