Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

DMB (NSH)

Test 1: uops

Code:

  dmb nsh

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)60696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)8283flush restart other nonspec (84)85inst all (8c)inst barrier (9c)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)f5f6f7f8fd
1004303522030122001100010001000600004230353026328931000100030353026111001100010000073116113032100030273036302830363028
1004302722030202009100010001000600004230353025328851000100030263035111001100010000073116113032100030273036302830363027
1004302622030122001100010001000653603330263035328931000100030353026111001100010000073116113032100030273036302730363028
1004302723030202009100010001000600004230273035328851000100030273035111001100010001073116113024100030363027303630263027
1004302623030122001100010001000600003430253035328931000100030353027111001100010000073116113032100030283036302730363028
1004302723030202009100010001000600004230353027328931000100030353026111001100010000073116113022100030363028303630283036
1004303522030202009100010001000600004230353027328851000100030353026111001100010000073116113032100030273036302730363027
1004302622030202009100010001000600004230353027328931000100030353027111001100010000073116113032100030273036302830363028
1004302723030112000100010001000600003430263035328851000100030273035111001100010000073116113024100030363027303630273036
1004303523030122001100010001000600003230263035328851000100030253035111001100010000073116113032100030283036302830363027

Test 2: throughput

Code:

  dmb nsh

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.9043

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696a6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst barrier (9c)9fl1d tlb access (a0)st unit uop (a7)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)? int retires (ef)f5f6f7f8fd
1020429094218212902818908101001001000010010000500598001492605529042291353278431010020010000200291352320811102011009910010010000100010000007101161129031100001002913629044291362903529136
10204291352173152912019008101001001000010010000500598001492595629135290423277351010020010000200290282329511102011009910010010000100010000007101161129132100001002902829136290372913629026
10204290252183572902018916101001001000010010000500598001492605529027291353278431010020010000200291352321511102011009910010010000100010000027101161129132100001002903729136291362904429136
1020429135217212902918899101001001000010010000500598001492605529043291353278431010020010000200291352322111102011009910010010000100010000007101161129132100001002903629136290292913629036
1020429035218122912019008101001001000010010000500598000492595529135290283278431010020010000200291352322111102011009910010010000100010000007101161129132100001002903629136290452913629035
1020429034218722901918917101001001000010010000500598000492605529043291353278431010020010000200290352329511102011009910010010000100010000007101161129132100001002903629136290282913629035
102042903421862912019008101001001000010010000500598000492594729135290363278431010020010000200291352321411102011009910010010000100010000007101161129032100001002913629044291362903629136
10204291352182882901018916101001001000010010000500598001492605529034291353278431010020010000200291352320711102011009910010010000100010000007101161129040100001002913629028291362903729136
1020429027218242902018917101001001000010010000500598001492605529025291353277521010020010000200290422329511102011009910010010000100010000007102161129032100001002913629037291362904329136
102042913521802912019008101001001000010010000500598001492596329135290353278431010020010000200291352322111102011009910010010000100010000007101161129040100001002913629028291362903729136

1000 unrolls and 10 iterations

Result (median cycles for code): 2.9867

retire uop (01)cycle (02)0318191e1f3f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6061696a6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst barrier (9c)9fst unit uop (a7)l1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)? int retires (ef)f5f6f7f8fd
10024298892240090298511991510010101000010100005059982014926786298662986732868110010201000020299512995111100211091010100001010000006401216332986310000102986829867298682986829867
100242986622300270299361991510010101000010100005059982104926871298672986432859610010201000020299512995111100211091010100001010000006401216222994810000102986829866298662986829866
10024298672240060299361991510010101000010100005059982014926871299512995132868110010201000020299512995111100211091010100001010000006401316332986310000102986629868298662986629868
10024298662240000299361991510010101000010100005059982104926871298662986632859410010201000020298652986511100211091010100001010000036400216232994810000102986729868298672986729866
100242986622300150298511983110010101000010100005059984104926784299512995132868110010201000020299512995111100211091010100001010000006401316322994810000102986729868298672986729868
100242986522300390299361991510010101000010100005059982104926871299512995132868110010201000020299512995111100211091010100001010000006401216222994810000102995229952299522995229952
10024299512240000299361991510010101000010100005059982104926871298672986632859610010201000020298662986711100211091010100001010000006400316222994810000102995229952299522995229867
10024298662240000298491983010010101000010100005059982014926787298652986732859710010201000020298662986611100211091010100001010000006401316222994810000102995229952299522995229952
10024299512240000298501983110010101000010100005059982014926787299512995132868110010201000020299512995111100211091010100001010000006401216222986310000102986829866298662986829866
100242986722300270298521983010010101000010100005059982014926786299512995132868110010201000020298672986611100211091010100001010000006401216222986410000102986829868298672986829868