Firestorm: STR (unsigned offset, 64-bit) measurements

Code:

  str x0, [x6, #8]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	22	3a	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	559	4	1	1	0	1	0	20	1	1	535	16	16	0	25	1000	1000	1000	23197	1	547	558	360	3	405	1000	1000	2000	551	547	1	1	1001	1000	1000	1014	14	36	0	0	1014	1	1	18	1002	16	36	14	2	73	1	16	1	1	549	1000	559	548	548	548	548
1004	547	4	1	0	1	0	0	21	1	1	536	16	16	0	25	1000	1000	1000	22692	1	552	558	360	3	416	1000	1000	2000	552	558	1	1	1001	1000	1000	1014	14	34	0	1	1016	0	1	18	1002	16	36	14	0	73	1	16	1	1	557	1000	553	551	548	558	548
1004	547	4	1	1	1	1	0	17	1	1	533	0	16	0	25	1000	1000	1000	22692	1	558	550	372	3	417	1000	1000	2000	558	547	1	1	1001	1000	1000	1014	14	36	0	1	1016	1	0	14	1000	14	36	14	0	73	1	16	1	1	547	1000	560	553	548	550	561
1004	558	4	1	1	0	1	0	14	1	1	545	16	16	5	25	1000	1000	1000	23244	1	547	547	360	3	416	1000	1000	2000	559	547	1	1	1001	1000	1000	1015	14	36	0	0	1016	0	1	20	1002	14	36	14	1	73	1	16	1	1	556	1000	548	548	560	548	560
1004	559	4	1	0	0	0	0	21	1	1	532	16	0	2	25	1000	1000	1000	22718	1	547	558	364	3	419	1000	1000	2000	558	553	1	1	1001	1000	1000	1014	16	36	0	0	1016	0	0	18	1000	16	36	14	0	73	1	16	1	1	555	1000	553	548	562	558	560
1004	547	4	1	1	1	0	0	20	1	1	532	0	16	2	25	1000	1000	1000	23292	1	552	547	365	3	409	1000	1000	2000	560	559	1	1	1001	1000	1000	1015	16	36	0	0	1016	0	0	14	1000	14	36	14	1	73	1	16	1	1	544	1000	548	551	548	549	559
1004	558	4	1	1	1	1	0	14	0	1	532	0	0	5	25	1000	1000	1000	22692	1	547	552	372	3	416	1000	1000	2000	547	549	1	1	1001	1000	1000	1015	14	36	0	0	1014	0	1	16	1002	16	35	14	0	73	1	16	1	1	555	1000	558	559	559	553	548
1004	553	4	1	0	1	0	0	14	0	1	546	16	16	2	25	1000	1000	1000	23268	1	547	547	371	3	410	1000	1000	2000	547	547	1	1	1001	1000	1000	1015	14	0	0	1	1016	0	0	17	1000	16	36	14	2	73	1	16	1	1	555	1000	553	551	562	558	560
1004	547	4	1	1	1	1	0	14	1	1	544	0	0	5	25	1000	1000	1000	22718	1	547	559	364	3	417	1000	1000	2000	559	552	1	1	1001	1000	1000	1014	14	36	0	1	1016	0	0	14	1002	16	36	14	2	73	1	16	1	1	554	1000	550	548	559	559	559
1004	547	4	1	0	1	1	0	20	1	1	532	0	16	2	25	1000	1000	1000	23292	1	551	547	366	3	411	1000	1000	2000	551	558	1	1	1001	1000	1000	1015	15	0	0	0	1016	0	0	18	1002	14	36	14	0	73	1	16	1	1	544	1000	553	552	550	559	560

Count: 8

Code:

  str x0, [x6, #8]
  str x0, [x6, #8]
  str x0, [x6, #8]
  str x0, [x6, #8]
  str x0, [x6, #8]
  str x0, [x6, #8]
  str x0, [x6, #8]
  str x0, [x6, #8]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	23	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40049	300	0	9	1	0	40027	0	16	2	25	80100	100	80000	100	80000	500	1839424	0	49	36962	40051	40042	29963	3	30000	80100	200	80000	200	160000	40058	32004	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80000	0	0	80002	2	34	5110	2	16	2	2	40039	80000	100	40041	40050	40043	40041	40043
80204	40050	300	0	3	1	0	40025	16	16	0	25	80100	100	80000	100	80121	500	1839808	0	49	36962	40040	40042	29955	3	30000	80100	200	80000	200	160000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	8	80002	2	34	5110	2	16	2	2	40039	80000	100	40041	40041	40043	40050	40043
80204	40042	300	0	9	1	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839424	1	49	33970	40050	40042	29955	3	29998	80100	200	80000	200	160000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	2	80002	2	0	5110	2	16	2	2	40046	80000	100	40050	40043	40051	40043	40043
80204	40042	300	0	3	0	0	40027	16	0	0	25	80100	100	80000	100	80000	500	1839424	1	49	36962	40042	40042	29955	3	30000	80100	200	80000	200	160000	40051	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	8	80002	2	0	5110	2	16	2	2	40037	80000	100	40043	40051	40043	40124	40043
80204	40049	300	0	3	1	0	40027	16	16	0	25	80100	100	80120	100	80216	500	1839808	1	49	37107	40042	40146	29963	3	30000	80100	200	80000	200	160000	40202	40199	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	2	80002	2	34	5110	2	16	2	2	40037	80000	100	40051	40043	40043	40043	40043
80204	40042	300	0	3	1	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839784	1	49	36962	40042	40050	29964	3	30000	80100	200	80000	200	160000	40050	32003	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	2	80002	0	0	5110	2	16	2	2	40048	80000	100	40043	40043	40043	40043	40043
80204	40042	299	0	0	1	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839424	0	49	36962	40049	40040	29955	3	30000	80100	200	80000	200	160000	40059	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	80002	0	5	80002	2	34	5110	2	16	2	2	40037	80000	100	40050	40043	40041	40043	40043
80204	40042	299	0	3	0	0	40027	0	16	0	25	80100	100	80000	100	80000	500	1839424	1	49	36962	40042	40040	29955	3	30000	80100	200	80000	200	160000	40045	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	2	80002	2	34	5110	2	16	2	2	40039	80000	100	40051	40043	40051	40043	40041
80204	40040	300	0	3	1	0	40025	16	16	0	25	80100	100	80000	100	80000	500	1839424	1	49	36962	40050	40042	29953	3	30000	80100	200	80000	200	160000	40042	32003	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	2	80002	2	34	5110	2	16	2	2	40048	80000	100	40043	40043	40052	40043	40041
80204	40040	299	0	3	1	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839424	0	49	36970	40042	40042	29955	3	30007	80100	200	80000	200	160242	40052	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	0	80002	2	34	5110	2	16	2	2	40039	80000	100	40051	40043	40051	40043	40043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40042	300	0	0	0	6	6	1	40035	0	16	0	25	80010	10	80000	10	80000	50	1839424	1	49	36960	40040	40042	29977	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	34	80002	11	2	80002	2	34	0	5020	0	23	16	17	8	40039	80000	10	40041	40050	40043	40051	40051
80024	40040	300	0	0	0	0	9	1	40027	0	16	28	25	80010	10	80000	10	80000	50	1839856	0	49	36962	40042	40042	29977	3	30020	80010	20	80000	20	160000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	34	80002	11	8	80002	2	34	0	5020	0	8	16	8	17	40047	80000	10	40121	40043	40052	40043	40043
80024	40042	300	0	0	0	0	3	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839424	0	49	36962	40040	40042	29977	3	30022	80010	20	80000	20	160000	40049	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	34	80002	39	2	80002	2	34	0	5020	0	17	16	17	17	40048	80000	10	40043	40043	40043	40043	40043
80024	40050	300	0	0	0	0	0	1	40027	16	16	0	25	80010	10	80000	10	80000	50	1839424	0	49	36962	40040	40049	29985	3	30022	80010	20	80000	20	160000	40050	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	34	80000	9	9	80002	2	34	0	5020	0	17	16	17	6	40039	80000	10	40043	40051	40043	40043	40043
80024	40050	299	0	0	0	0	3	1	40027	16	16	97	25	80010	10	80000	10	80000	50	1839808	0	49	36962	40042	40042	29977	3	30022	80010	20	80000	20	160000	40040	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	34	80002	11	14	80002	2	34	0	5020	0	17	16	17	6	40039	80000	10	40041	40043	40041	40043	40043
80024	40042	300	0	0	0	0	3	0	40025	16	16	0	25	80010	10	80000	10	80000	50	1839352	0	49	36960	40042	40042	29977	3	30031	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	34	80002	7	17	80002	2	34	0	5020	0	8	16	17	17	40039	80000	10	40043	40043	40043	40043	40043
80024	40042	300	0	0	0	0	3	1	40027	16	16	0	25	80010	10	80000	10	80000	50	1839424	0	49	36962	40042	40042	29975	3	30031	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	34	80002	9	5	80002	0	0	1	5020	0	17	16	17	6	40039	80000	10	40043	40041	40043	40041	40041
80024	40042	300	0	0	0	0	3	1	40036	16	16	2	25	80010	10	80000	10	80000	50	1839424	0	49	36962	40042	40042	29977	3	30022	80010	20	80000	20	160000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	80002	10	23	80002	2	34	0	5020	0	17	16	14	6	40039	80000	10	40043	40051	40043	40051	40043
80024	40042	300	0	0	0	0	9	1	40027	16	16	0	25	80010	10	80000	10	80000	50	1839424	0	49	36962	40050	40042	29975	3	30022	80010	20	80000	20	160000	40050	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	80002	10	17	80002	2	34	0	5020	0	17	16	17	6	40039	80000	10	40043	40041	40043	40043	40052
80024	40042	300	0	0	0	0	3	0	40027	0	16	0	25	80010	10	80000	10	80000	50	1839424	0	49	36962	40042	40042	29977	3	30031	80010	20	80000	20	160000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	34	80002	5	6	80002	2	34	0	5020	0	11	16	17	17	40047	80000	10	40043	40043	40050	40043	40043

STR (unsigned offset, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations