Firestorm: CNEG (32-bit) measurements

Code:

  cneg w0, w0, hi

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1035	7	2	66	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	0	0	77	4	27	4	4	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	2	66	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	1	0	77	4	27	4	3	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	2	66	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	0	0	77	4	27	4	3	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	2	66	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	0	0	77	4	27	4	4	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	2	66	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	0	0	77	4	27	4	4	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	2	66	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	1	0	77	4	27	4	4	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	2	66	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	0	0	77	4	27	4	4	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	2	66	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	3	0	77	4	27	4	4	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	2	66	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	1	0	77	4	27	4	4	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	2	189	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	0	0	77	4	27	4	4	990	1000	1000	1036	1036	1036	1036	1036

Test 2: Latency 1->2

Code:

  cneg w0, w0, hi

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10082
10204	10214	75	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10327	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647688	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	126	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	102	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	640	2	27	2	2	9993	10000	10010	10036	10170	10036	10036	10036
10024	10080	75	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	9	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	105	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036

Test 3: Latency 1->3

Chain cycles: 1

Code:

  cneg w0, w1, hi
  tst x0, 1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	149	0	0	199	19926	25	20200	20200	20200	1297650	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	0	0	1310	2	28	2	2	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	9	132	61	19926	25	20200	20200	20200	1297650	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	0	0	1310	2	28	2	2	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19926	25	20200	20200	20200	1297650	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	0	0	1310	2	28	1	2	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	105	19926	25	20200	20200	20200	1297650	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	0	0	1310	2	28	2	2	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	82	19926	25	20200	20200	20200	1297650	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	0	3	1310	2	28	2	2	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19926	25	20200	20200	20200	1297650	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	0	0	1310	2	28	2	2	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19926	25	20200	20200	20200	1297650	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	0	0	1310	1	28	2	2	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19926	25	20200	20200	20200	1297650	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	0	0	1310	2	28	2	2	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19926	25	20200	20200	20200	1297650	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	1	0	1310	2	28	2	2	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19926	25	20200	20200	20200	1297650	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	0	0	1310	2	28	2	2	19992	20100	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	0	103	19918	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	104	2	1	20021	10	9	20010	10000	0	0	0	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	197	19918	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	104	1	1	20021	10	9	20010	10000	0	0	0	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	212	19918	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	104	1	1	20021	10	9	20010	10000	0	0	0	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	104	1	1	20021	10	9	20010	10000	0	0	0	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	273	19918	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	104	1	1	20021	10	9	20010	10000	0	0	0	0	0	1270	2	27	2	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	132	84	19918	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	104	1	1	20021	10	9	20010	10000	0	0	0	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19924	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	104	1	1	20021	10	9	20010	10000	0	0	1	0	0	1295	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	822	19918	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	104	1	1	20021	10	9	20010	10000	0	0	1	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	104	1	1	20021	10	9	20010	10000	0	0	0	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	506	19918	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	104	1	1	20021	10	9	20010	10000	0	0	0	0	3	1270	1	27	1	2	19995	20010	10010	20036	20036	20036	20036	20036

Test 4: throughput

Count: 8

Code:

  cneg w0, w8, hi
  cneg w1, w8, hi
  cneg w2, w8, hi
  cneg w3, w8, hi
  cneg w4, w8, hi
  cneg w5, w8, hi
  cneg w6, w8, hi
  cneg w7, w8, hi

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3344

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26763	200	0	0	0	0	0	0	0	28	27	80118	80118	80124	479916	49	23660	26740	26740	16679	6	16689	80124	80232	240296	26740	66	1	1	80201	100	99	100	80100	80100	0	0	0	0	0	0	0	0	1	1	1	5118	0	16	0	0	26737	80018	80100	26741	26741	26741	26741	26741
80204	26740	200	0	0	0	0	12	0	0	28	27	80118	80118	80124	479916	49	23660	26740	26740	16679	6	16689	80124	80232	240296	26740	66	1	1	80201	100	99	100	80100	80100	0	0	0	0	0	0	0	0	1	1	1	5118	0	16	0	0	26737	80018	80100	26741	26741	26741	26741	26741
80204	26740	200	0	0	0	0	0	0	0	28	27	80118	80118	80124	479916	49	23660	26740	26740	16679	6	16689	80124	80232	240296	26740	66	1	1	80201	100	99	100	80100	80100	0	0	0	0	0	0	0	0	1	1	1	5118	0	16	0	0	26737	80018	80100	26741	26741	26741	26741	26741
80204	26740	200	0	0	0	0	0	0	0	28	27	80118	80118	80124	479916	49	23660	26740	26740	16679	6	16689	80124	80232	240533	26740	66	1	1	80201	100	99	100	80100	80100	0	0	0	0	0	0	0	0	1	1	1	5118	0	16	0	0	26737	80018	80100	26741	26741	26741	26741	26741
80204	26740	200	0	0	0	0	0	0	0	28	27	80118	80118	80124	479916	49	23660	26740	26740	16679	6	16689	80124	80455	240296	26740	66	1	1	80201	100	99	100	80100	80100	0	0	0	0	0	0	0	0	1	1	1	5118	0	16	0	0	26737	80018	80100	26741	26741	26741	26741	26741
80204	26740	200	0	0	0	0	0	0	0	28	27	80118	80118	80124	479916	49	23660	26740	26740	16679	6	16689	80124	80232	240296	26740	66	1	1	80201	100	99	100	80100	80100	0	0	0	0	0	0	0	0	1	1	1	5118	0	16	0	0	26737	80018	80100	26741	26741	26741	26741	26741
80204	26740	201	0	0	0	0	0	0	0	28	27	80118	80118	80124	479916	49	23660	26740	26740	16679	6	16689	80124	80232	240296	26740	66	1	1	80201	100	99	100	80100	80100	0	0	0	0	0	0	0	0	1	1	1	5118	0	16	0	0	26737	80018	80100	26741	26741	26741	26741	26741
80204	26740	200	0	0	0	0	0	0	0	28	27	80118	80118	80124	479916	49	23660	26740	26740	16679	6	16689	80124	80232	240296	26740	66	1	1	80201	100	99	100	80100	80100	0	0	0	0	0	0	0	0	1	1	1	5118	0	16	0	0	26737	80018	80100	26741	26741	26741	26741	26741
80204	26740	200	0	0	0	0	0	0	0	28	27	80118	80118	80124	479916	49	23660	26740	26740	16679	6	16689	80124	80232	240296	26740	66	1	1	80201	100	99	100	80100	80100	0	0	0	0	0	0	0	0	1	1	1	5118	0	16	0	0	26737	80018	80100	26741	26741	26741	26741	26741
80204	26740	200	0	0	0	0	0	0	0	28	27	80118	80118	80124	479916	49	23660	26740	26740	16679	6	16689	80124	80232	240296	26740	66	1	1	80201	100	99	100	80100	80100	0	0	0	0	0	0	0	0	1	1	1	5118	0	16	0	0	26737	80018	80100	26741	26741	26741	26741	26741

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	26724	200	0	0	0	0	0	0	0	0	0	36	25	80010	80010	80010	472059	0	0	49	23626	26706	26706	16665	3	16684	80010	80020	240020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	0	0	0	0	0	5020	11	18	11	12	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	0	0	0	0	0	0	36	25	80010	80010	80010	472059	0	1	49	23626	26706	26706	16665	3	16684	80010	80020	240020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	0	0	0	0	0	5020	12	18	13	13	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	0	0	0	6	0	0	36	25	80010	80010	80010	472059	0	1	49	23626	26706	26706	16665	3	16684	80010	80020	240020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	0	0	0	0	0	5020	14	18	14	13	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	0	0	0	0	0	0	36	25	80010	80010	80010	472059	0	1	49	23626	26706	26706	16665	3	16684	80010	80020	240020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	0	0	0	0	0	5020	12	18	10	13	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	0	0	0	0	0	0	36	25	80010	80010	80010	472059	0	0	49	23626	26706	26706	16665	3	16684	80010	80020	240020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	0	0	0	0	0	5020	11	18	12	12	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	0	0	0	0	0	0	36	25	80010	80010	80010	472059	1	0	49	23626	26706	26706	16665	3	16684	80010	80020	240020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	1	0	0	3	0	5020	12	18	12	12	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	0	0	0	0	0	0	36	25	80010	80010	80010	472059	0	1	49	23626	26799	26940	16740	28	16857	80426	80463	241292	27033	66	7	1	80021	10	9	10	80010	80010	2	2	0	0	1	2	2805	3	5053	13	75	13	15	26917	80466	80010	26988	27035	27023	26989	26985
80024	27032	202	2	0	2	1	5	5	936	528	0	1128	173	80475	80143	80500	449327	0	0	49	23720	27035	26987	16740	19	16831	80503	80521	241316	27030	66	8	1	80021	10	9	10	80010	80010	2	0	2	0	1	2	3258	0	5131	13	76	14	13	26948	80401	80010	26895	26940	27035	27028	26983
80024	26752	203	4	1	0	0	5	4	804	528	0	1297	152	80542	80478	80501	446824	0	0	49	23903	26988	27032	16752	26	16712	80497	80532	241517	27032	66	7	1	80021	10	9	10	80010	80010	2	0	3	0	1	0	2783	4	5113	17	75	16	12	26915	80465	80010	27126	27079	27124	27126	27078
80024	27125	203	0	0	0	0	8	8	1059	704	1	1686	196	80614	80675	80219	449093	0	0	49	24048	27079	27077	16777	39	16918	80641	80595	241715	27126	66	9	1	80021	10	9	10	80010	80010	2	0	0	0	0	2	3240	4	5035	11	43	15	14	26739	80405	80010	26987	26847	26986	27034	26991

CNEG (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations