Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UXTB

Test 1: uops

Code:

  uxtb w0, w0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)033f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10041035761862251000100010001691610351035728386810001000100010354111100110000073241119371000100010361036103610361036
10041035861862251000100010001691610351035728386810001000100010354111100110000073141119371000100010361036103610361036
10041035861862251000100010001691610351035728386810001000100010354111100110000073141119371000100010361036103610361036
10041035761862251000100010001691610351035728386810001000100010354111100110000073141119371000100010361036103610361036
10041035861862251000100010001691610351035728386810001000100010354111100110000073141119371000100010361036103610361036
10041035861862251000100010001691610351035728386810001000100010354111100110000073141119371000100010361036103610361036
10041035861862251000100010001691610351035728386810001000100010354111100110000073141119371000100010361036103610361036
10041035761862251000100010001691610351035728386810001000100010354111100110000073141119371000100010361036103610361036
10041035761862251000100010001691610351035728386810001000100010354111100110001094141119371000100010361036103610361036
10041035861862251000100010001691610351035728386810001000100010354111100110000073141119371000100010361036103610361036

Test 2: Latency 1->2

Code:

  uxtb w0, w0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)int prf full (71)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204100357501416198772510100101001010088664049695501003510035858003872210100102001020010035411110201100991001010010071013711994110000101001003610036100361003610036
1020410035750186198772510100101001010088664149695501003510035858003872210100102001020010035411110201100991001010010071013711994110000101001003610036100361003610036
102041003575006198772510100101001010088664149695501003510035858003872210100102001020010035411110201100991001010010071013711994110000101001003610036100361003610036
1020410035750546198772510100101001010088664149695501003510035858003872210100102001020010035411110201100991001010010071013711994110000101001003610036100361003610036
1020410035750246198772510100101001010088664149695501003510035858003872210100102001020010035411110201100991001010010071013711994110000101001003610036100361003610036
102041003575066198772510100101001010088664149695501003510035858003872210100102001020010035411110201100991001010010071013711994110000101001003610036100361003610036
102041003575006198772510100101001010088664149695501003510035858003872210100102001020010035411110201100991001010010071013711994110000101001003610036100361003610036
102041003575006198772510100101001010088664149695501003510035858003872210100102001020010035411110201100991001010010071013711994110000101001003610036100361003610036
1020410035750126198772510100101001010088664049695501003510035858003872210100102001020010035411110201100991001010010071013711994110000101001003610036100361003610036
102041003575008498772510100101001010088664049695501003510035858003872210100102001020010035411110201100991001010010071013711994110000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3a3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024100357511031339863251001010010100108878414969551003510035860238740100101002010020100354111100211091010010100064611411113994010000100101003610036100361003610036
1002410035751103689863251001010010100108878404969551003510035860238740100101002010020100354111100211091010010100064611411112994010000100101003610036100361003610036
1002410035751103689863251001010010100108878414969551003510035860238740100101002010020100354111100211091010010100064613411313994010000100101003610036100361003610036
1002410035751103689863251001010010100108878404969551003510035860238740100101002010020100354111100211091010010100064612411112994010000100101003610036100361003610036
100241003575110391986325100101001010010887841496955100351003586023874010010100201002010035411110021109101001010006468411313994010000100101003610036100361003610036
100241003575110389986325100101001010010887841496955100351003586023874010010100201002010035411110021109101001010006466411113994010000100101003610036100361003610036
1002410035751103919863251001010010100108878404969551003510035860238740100101002010020100354111100211091010010100064611411113994010000100101003610036100361003610036
1002410035751103254986325100101001010010887841496955100351003586023874010010100201002010035411110021109101001010006461141611994010000100101003610036100361003610036
10024100357511034969863251001010010100108878414969551003510035860238740100101002010020100354111100211091010010100064611411212994010000100101003610036100361003610036
100241003575110368986325100101001010010887841496955100351003586023874010010100201002010035411110021109101001010006466411111994010000100101003610036100361003610036

Test 3: throughput

Count: 8

Code:

  uxtb w0, w8
  uxtb w1, w8
  uxtb w2, w8
  uxtb w3, w8
  uxtb w4, w8
  uxtb w5, w8
  uxtb w6, w8
  uxtb w7, w8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.1674

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)int prf full (71)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80204134141000000000282780136801368014840071014910310013390133903326063336801488026480264133903911802011009910080100100000000301115119116001338780036801001339113391133911339113391
80204133901000000000282780136801368014840071004910310013390133903326063336801488026480264133903911802011009910080100100000000001115119016001338780036801001339113391133911339113391
80204133901010000000282780136801368014840071004910310013390133903326063336801488026480264133903911802011009910080100100000020301115119016001338780036801001339113391133911339113391
802041339010000000002827801368013680148400710049103100133901339033260633368014880264802641339039118020110099100801001000000001201115119016001338780036801001339113391133911339113391
8020413390101000000028278013680136801484007100491031001339013390332606333680148802648026413390391180201100991008010010000002208701115119016001338780036801001339113391133911339113391
80204133901000000000282780136801368014840071004910310013390133903326063336801488026480264133903911802011009910080100100000000001115119016001338780036801001339113391133911339113391
802041339010000000007027801368013680148400710049103100133901339033260633368014880264802641339039118020110099100801001000000004801115119016001338780036801001339113391133911339113391
802041339010100000002827801368013680148400710049103100133901339033260633368014880264802641339039118020110099100801001000000003601115119016001338780036801001339113391133911339113391
80204133901010000000282780136801368014840071004910310013390133903326063336801488026480264133903911802011009910080100100000060001115119016001338780036801001339113391133911339113391
80204133901010000000282780136801368014840071004910310013390133903326063336801488026480264133903911802011009910080100100000000001115119016001338780036801001339113391133911339113391

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.1671

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3a3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)5f60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)d9ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80024136071010133399264065714180397804018053540262000491048813552136143332153400805438042380423135533941800211091080010100000013702510091210731358280645800101361613674136671361813673
800241361210201445400089115280529805318054240335100491053413619136123332203424800108055680699136153951800211091080010102200018430510051190731336880000800101343413498135701355513491
8002413478101113440801981198039480010805414026410049104741359413555333021342280147800208042513554394180021109108001010003120050805960531356380635800101355213372136121355813555
8002413603100113340888048225800108001080010400050004910291133711337133303334880010801518002013371391180021109108001010000000050213190361336880000800101337213372133721337213372
800241337110000000003525800108001080010400050004910291133711337133303334880010800208002013371391180021109108001010000000050215190661336880000800101337213372133721337213372
800241337110000000007725800108001080010400050114910291133711337133303334880010800208002013371391180021109108001010000000050203190451336880000800101337213372133721337213372
800241337110000000003525800108001080010400050004910291133711337133303334880010800208002013371391180021109108001010000000050215190551336880000800101337213372133721337213372
800241337110000000003525800108001080010400050004910291133711337133303334880010800208002013371391180021109108001010000003050215190531336880000800101337213372133721337213372
800241337110000000003525800108001080010400050004910291133711337133303334880010800208002013371391180021109108001010000000050215190451336880000800101337213372133721337213372
800241337110000000003525800108001080010400050004910291133711337133303334880010800208002013371391180021109108001010000000050213190561336880000800101337213372133721337213372