Firestorm: LDP (post-index, 64-bit) measurements

Code:

  ldp x0, x1, [x6], #8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 3.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	ldst x64 uop (b1)	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
3005	1060	8	0	0	216	0	26	0	0	4	0	1025	20	4	5	9	34	25	2000	1000	1000	1000	1000	52827	45592	0	1040	1057	574	3	648	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	1032	0	1	89	1039	8	0	36	6	41	1027	125	45	9	40	77	0	0	73	2	16	1	1	1037	0	1000	17	32	1000	2000	1041	1041	1041	1041	1041
3004	1040	8	0	0	104	0	43	0	0	2	0	1025	0	2	3	3	19	25	2000	1000	1000	1000	1000	52831	45592	0	1040	1040	574	3	648	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	1000	0	0	95	1038	0	1	0	0	44	1035	125	45	8	44	60	0	0	73	1	16	1	1	1018	0	1000	17	20	1000	2000	1046	1046	1046	1046	1046
3004	1040	8	0	0	64	0	17	1	0	1	0	1025	9	3	8	8	22	25	2000	1000	1000	1000	1000	52814	45589	0	1040	1045	574	3	648	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	1027	0	1	67	1038	6	1	29	10	48	1060	125	45	5	35	60	0	0	73	1	16	1	1	1037	1	1000	27	27	1000	2000	1041	1041	1041	1041	1041
3004	1040	8	0	0	82	0	19	1	0	7	12	1025	26	3	4	4	20	25	2000	1000	1000	1000	1000	52814	45595	0	1040	1045	574	3	648	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	1024	0	0	66	1040	7	0	21	10	39	1047	125	38	6	30	51	0	0	73	1	16	1	1	1021	0	1000	18	33	1000	2000	1041	1041	1041	1041	1041
3004	1040	8	0	0	107	0	28	0	0	2	0	1025	10	3	8	5	17	25	2000	1000	1000	1000	1000	52806	45590	1	1040	1040	574	3	653	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	1013	0	2	85	1043	0	1	0	0	43	1038	125	56	6	34	60	0	0	73	1	16	1	1	1037	0	1000	27	27	1000	2000	1041	1041	1041	1041	1041
3004	1040	8	0	0	127	0	13	1	0	5	0	1025	0	3	7	5	19	25	2000	1000	1000	1000	1000	52843	45590	1	1040	1040	574	3	648	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	1013	0	1	59	1049	10	1	15	10	52	1041	125	45	7	52	51	0	0	73	1	16	1	1	1037	0	1000	33	34	1000	2000	1041	1041	1041	1041	1041
3004	1040	7	0	0	88	0	21	1	0	5	0	1025	13	4	8	4	17	25	2000	1000	1000	1000	1000	52839	45591	1	1040	1040	574	3	648	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	1000	0	0	86	1036	0	0	0	0	37	1034	125	45	7	29	59	0	0	73	1	16	1	1	1037	0	1000	23	29	1000	2000	1041	1041	1041	1041	1041
3004	1040	7	0	0	71	0	23	0	0	2	0	1025	0	5	5	6	28	25	2000	1000	1000	1000	1000	52819	45592	0	1045	1040	574	3	648	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	1000	0	0	75	1037	0	1	0	0	40	1037	125	39	9	33	68	0	0	73	1	16	1	1	1037	0	1000	27	40	1000	2000	1041	1041	1041	1041	1041
3004	1040	8	0	1	145	0	32	0	0	2	0	1025	0	3	4	4	23	25	2000	1000	1000	1000	1000	52816	45586	1	1040	1040	575	3	648	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	1000	0	0	65	1033	0	0	0	0	34	1026	125	39	5	27	68	0	0	73	1	16	1	1	1037	0	1000	33	22	1000	2000	1041	1041	1041	1041	1041
3004	1040	7	0	0	180	0	20	0	0	5	0	1030	0	6	7	6	33	25	2000	1000	1000	1000	1000	52781	45591	1	1040	1040	574	3	648	2000	1000	2000	1000	1000	1045	38	1	1	1001	1000	1000	1017	0	2	75	1059	13	0	28	10	39	1059	125	33	7	35	43	3	1	73	1	16	1	1	1037	0	1000	33	28	1000	2000	1041	1041	1041	1041	1041

Test 2: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldp x0, x1, [x6], #8
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.8522

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	0e	0f	1e	20	22	24	3a	3f	40	43	46	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	ldst x64 uop (b1)	ldst xpg uop (b2)	b5	bb	be	l1d cache miss ld nonspec (bf)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60209	84072	598	0	0	0	313	10	1	0	475	78465	7	2	0	2	78373	25	52815	42156	10632	40110	10007	675029	2980669	1	49	74681	77686	77377	70486	0	6	71382	50117	40232	20016	70256	10008	77934	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10017	513	10020	19	9	12	10019	1250	4	658	10	4	506	0	0	2610	2	58	1	1	78087	42024	5141	4969	4884	10000	50100	77644	77782	78146	78286	78400
60204	78588	586	1	0	0	339	9	1	0	488	77873	7	2	0	1	78992	25	52650	42132	10503	40100	10000	669630	2994044	0	49	74725	78696	78399	70531	0	3	70504	50100	40200	20000	70200	10000	78429	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10014	553	10021	10	9	13	10019	1250	4	536	10	4	510	0	0	2610	1	56	2	1	78528	42259	5384	5414	5330	10000	50100	79155	79031	78570	77992	78895
60204	78485	588	0	0	0	339	10	1	0	481	78669	9	2	0	0	78392	25	52600	42367	10508	40100	10000	684551	3005200	0	49	76091	78085	78262	70600	0	3	70898	50100	40200	20000	70200	10000	78720	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10018	541	10019	10	9	16	10020	1250	4	540	10	4	516	0	0	2610	1	57	1	1	77753	42208	5352	5145	5498	10000	50100	78603	79941	79864	79096	78008
60204	77986	587	0	0	0	335	8	1	0	484	77800	11	2	0	0	78324	25	52655	42184	10506	40100	10000	680503	3035128	0	49	75271	78598	78487	69967	0	3	70429	50304	40200	20100	70200	10000	78823	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10017	558	10019	18	7	12	10017	1250	4	493	10	4	495	0	0	2610	1	58	1	1	78449	42340	5593	5505	5334	10000	50100	78390	78405	78377	78402	78238
60204	78522	587	0	0	0	324	10	1	0	511	78881	8	2	0	0	77481	25	52735	42216	10527	40100	10000	676954	2984000	0	49	75289	79080	78674	70985	0	3	71882	50100	40200	20000	70200	10000	78180	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10018	539	10020	13	7	19	10019	1250	4	540	10	4	551	0	0	2610	1	57	1	1	78625	42144	5612	5274	5137	10000	50100	77995	77941	78104	78224	78092
60204	77963	584	0	0	0	322	9	1	0	468	78713	10	2	0	0	78359	25	52695	42168	10524	40100	10000	674072	2987749	0	49	75333	78370	78898	70402	0	3	71063	50100	40200	20000	70200	10000	78304	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10017	487	10020	14	9	10	10019	1250	4	541	10	4	505	0	0	2610	1	58	0	1	78159	42064	5127	5026	5306	10000	50100	78469	78230	78899	78178	78587
60204	78357	583	0	0	0	303	10	1	0	511	78580	9	2	0	0	78393	25	52715	42132	10510	40100	10000	678422	2999176	0	49	75538	78926	78498	70711	0	3	70528	50100	40200	20000	70200	10000	81243	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10015	549	10020	16	9	16	10020	1250	4	536	10	4	531	0	0	2610	1	56	1	1	78679	42020	5286	5286	5479	10000	50100	78221	79461	78811	78764	79367
60204	78997	589	0	0	0	312	9	1	0	513	78331	11	2	0	0	78337	25	52755	42300	10547	40100	10000	680856	3002914	1	49	76128	78547	78744	70890	0	3	70980	50100	40200	20000	70200	10000	78797	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10017	526	10017	12	8	13	10017	1250	4	498	10	4	558	0	1	2610	1	57	1	1	78574	42236	5500	5339	5400	10000	50100	79160	78922	78789	79036	79021
60204	79135	591	0	0	0	317	7	1	0	510	78758	10	2	0	0	80459	25	52810	42128	10497	40100	10000	685906	3000083	0	49	75465	79456	78311	70815	0	3	71212	50100	40200	20000	70200	10000	78017	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10017	533	10017	12	10	13	10017	1250	4	501	10	4	508	0	0	2610	1	58	1	1	78071	42116	5270	5346	5226	10000	50100	78555	78483	79240	78850	79024
60204	79423	595	0	0	0	308	7	1	0	509	78756	11	2	0	0	78292	25	52690	42204	10516	40100	10000	677800	3027982	0	49	75375	77966	78302	70510	0	3	70720	50100	40200	20000	70200	10000	78113	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10016	537	10018	16	9	13	10017	1250	4	513	10	4	507	0	0	2610	1	58	1	1	78369	42136	5140	5503	5002	10000	50100	78529	77918	78063	77887	78411

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.8721

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	20	22	23	24	3a	3f	40	43	46	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	ldst x64 uop (b1)	ldst xpg uop (b2)	b5	bb	be	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60029	84692	599	1	1	1	1	1	0	0	0	131	0	7	1	0	0	488	78560	8	9	0	9	78394	25	52485	41950	10619	40010	10000	676074	3000834	0	49	75664	78165	78189	70501	3	71540	50010	40020	20000	70020	10000	78343	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10019	1	489	10029	10	10	28	10026	1250	4	616	17	4	532	1	1	0	2520	3	64	2	2	5	79221	41976	5527	5634	5987	10000	50010	78426	78463	78769	79326	78559
60024	78849	586	1	1	0	0	0	0	0	0	163	0	12	2	0	0	501	79584	15	9	1	7	78097	25	52485	42002	10516	40010	10000	677719	3009606	1	49	76089	78728	78643	70709	44	71262	50010	40020	20000	70020	10000	78690	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10017	2	506	10035	7	10	20	10026	1250	4	502	17	4	484	1	0	0	2520	3	64	2	3	4	78095	42044	5797	5824	5421	10000	50010	80184	78873	78673	78485	78721
60024	78770	594	0	0	0	0	0	0	0	0	157	0	6	1	0	0	488	78773	8	10	0	6	78498	25	52585	42230	10507	40010	10000	678626	2994923	0	49	76383	78517	78496	70674	3	71027	50010	40020	20000	70020	10000	78530	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10015	0	513	10022	15	6	25	10021	1250	4	518	16	4	500	0	0	0	2520	2	64	2	5	2	78299	41980	5353	5323	5577	10000	50010	79454	78800	78697	79245	78541
60024	78234	588	0	0	0	0	0	0	0	0	154	0	5	1	0	0	478	78277	10	9	0	7	79257	25	52690	42026	10484	40010	10000	677575	3036774	1	49	75442	78177	78294	70940	3	70977	50010	40020	20000	70020	10000	78501	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10017	0	531	10026	15	10	26	10027	1250	4	473	16	4	459	0	0	0	2520	4	64	2	2	3	79162	42064	5963	5795	5517	10000	50010	78746	78701	78691	78441	78287
60024	78235	589	0	0	0	0	0	0	0	0	141	0	10	1	0	0	465	79007	7	8	0	6	78458	25	52495	41962	10546	40010	10000	683164	3015247	1	49	75912	78507	78210	70407	3	71620	50010	40020	20000	70020	10000	78661	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10018	0	499	10027	10	9	22	10025	1250	4	488	16	4	524	0	0	0	2520	3	64	2	2	2	79405	42052	5341	5206	6010	10000	50010	78364	79593	79058	78681	78728
60024	78721	591	0	0	0	0	0	0	0	0	142	0	8	1	0	0	504	78786	8	10	0	7	78824	25	52700	42218	10513	40010	10000	682066	3022852	1	49	75600	79351	79315	70739	3	71147	50010	40020	20000	70020	10000	79076	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10015	0	512	10026	12	7	25	10022	1250	4	508	17	4	522	0	0	0	2520	3	64	2	4	4	78717	42016	5500	5662	5310	10000	50010	79062	78425	78855	78679	78653
60024	79470	590	0	0	0	0	0	0	0	0	164	0	6	1	0	0	462	78326	11	10	0	4	78450	25	52425	42018	10514	40010	10000	676153	3002523	1	49	75974	78721	78752	71494	3	71037	50010	40020	20000	70020	10000	79693	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10017	0	525	10024	8	7	22	10023	1250	4	452	15	4	483	0	0	0	2520	2	64	2	3	2	78178	42132	5385	5237	5354	10000	50010	78438	78190	78579	79299	78751
60024	78300	593	0	0	0	0	0	0	0	0	158	0	10	1	0	0	488	79766	10	7	0	6	78094	25	52620	42030	10523	40010	10000	677208	3005252	0	49	76017	79324	78593	71633	3	70623	50010	40520	20000	70020	10000	78332	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10030	0	533	10026	10	9	24	10026	1250	4	586	17	4	489	0	0	0	2520	2	64	2	2	2	79510	41992	5573	5879	5279	10000	50010	78719	78467	78511	78368	78066
60024	77932	586	0	0	0	0	0	0	0	0	155	0	7	1	0	0	535	79020	10	7	0	6	78174	25	52675	42066	10525	40010	10000	675703	2997225	0	49	75624	78469	78129	71423	3	71675	50010	40020	20000	70020	10000	79028	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10017	0	543	10023	8	9	23	10035	1250	4	472	17	4	510	0	0	0	2520	2	64	2	5	2	78280	42128	5585	5906	5645	10000	50010	79225	80216	78746	78530	78439
60024	78150	585	0	0	0	0	1	0	0	0	241	264	12	1	0	0	487	79050	10	9	0	6	78466	25	52630	42058	10516	40010	10000	679915	2998721	0	49	75745	78616	78945	70957	3	70293	50010	40020	20000	70020	10000	78843	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10015	0	494	10022	11	7	19	10023	1250	4	469	14	4	470	0	0	0	2520	2	64	2	2	2	78568	42048	5401	5270	5151	10000	50010	78320	78394	78575	78413	78443

Test 3: Latency 2->3 (with chain penalty)

Chain cycles: 3

Code:

  ldp x0, x1, [x6], #8
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.9960

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0f	18	19	1e	1f	20	22	24	3a	3f	40	43	46	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	ldst x64 uop (b1)	ldst xpg uop (b2)	b5	bb	be	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60209	84916	608	0	0	0	0	0	0	0	243	0	7	1	0	535	80444	6	125	0	67	79732	25	53370	42992	10787	40100	10000	692400	3065018	0	49	77340	0	80353	80112	71928	3	73133	50100	40200	20000	70200	10000	80383	35	1	1	40201	100	99	100	10000	30100	10000	100	10017	0	611	10140	0	15	6	129	10142	1250	4	583	129	4	504	0	0	0	0	2610	5	56	1	1	79508	42464	5614	5415	5300	10000	50100	79818	79981	79487	79308	79131
60204	79662	601	0	0	0	0	0	0	0	263	0	11	1	0	466	79935	11	130	0	71	79793	25	53285	42560	10619	40100	10000	688756	3048421	1	49	76546	0	79486	79477	71449	3	71970	50100	40200	20000	70200	10000	79594	35	1	1	40201	100	99	100	10000	30100	10000	100	10015	1	588	10146	0	15	8	133	10150	1250	4	503	125	4	491	2	0	0	0	2610	1	58	1	1	79552	42408	5515	5839	5465	10000	50100	80244	79699	79810	80432	79921
60204	80802	598	0	0	0	0	0	0	0	252	0	8	1	0	526	79818	9	122	0	71	78894	25	53280	42664	10631	40100	10000	691582	3058172	0	49	77037	0	79932	79457	71454	3	72329	50100	40200	20000	70200	10000	79910	35	1	1	40201	100	99	100	10000	30100	10000	100	10018	0	585	10133	0	8	9	122	10139	1250	4	497	134	4	501	0	0	0	0	2610	1	56	1	1	79849	42576	5939	5911	6024	10000	50100	79923	79940	79689	79836	80426
60204	80702	596	0	0	0	0	0	0	0	252	0	6	1	0	489	80597	10	113	0	77	79835	25	53450	42884	10655	40100	10000	688793	3058860	0	49	76790	0	80667	80233	73046	3	72753	50100	40200	20000	70200	10000	80127	35	1	1	40201	100	99	100	10000	30100	10000	100	10017	0	585	10140	0	19	9	135	10142	1250	4	496	132	4	505	0	0	0	0	2610	1	57	1	1	80236	42588	5686	5701	5604	10000	50100	80821	80129	80349	80352	80146
60204	79987	600	0	0	1	0	0	0	0	241	0	8	1	0	540	79943	9	117	0	66	79385	25	53330	42592	10655	40100	10000	694175	3045926	1	49	77086	0	80041	80197	72453	3	72912	50100	40200	20000	70200	10000	80155	35	3	1	40201	100	99	100	10000	30100	10000	100	10017	0	617	10133	0	8	7	135	10155	1250	4	530	126	4	542	0	0	0	0	2610	1	56	1	1	79463	42592	5697	5901	5945	10000	50100	79687	79765	79693	79106	80068
60204	80626	599	0	0	0	0	0	0	0	277	0	10	1	0	487	79475	10	131	0	75	79736	25	53290	42652	10621	40100	10000	692455	3051778	0	49	76762	0	80262	79729	71720	3	72187	50100	40200	20000	70200	10000	79846	35	1	1	40201	100	99	100	10000	30100	10000	100	10017	0	591	10138	0	13	9	136	10139	1250	4	492	144	4	540	0	0	0	0	2610	1	56	1	1	79503	42712	5785	5439	5699	10000	50100	79928	80259	79837	79922	79431
60204	79655	597	0	0	0	0	0	0	0	264	0	10	1	0	498	79937	7	122	0	75	81925	25	53445	42648	10639	40100	10000	685777	3033478	1	49	76923	0	79983	80503	72173	22	74281	50100	40200	20000	70200	10000	80401	35	1	1	40201	100	99	100	10000	30100	10000	100	10018	0	621	10134	0	11	9	142	10142	1250	4	501	134	4	501	0	0	0	0	2610	2	57	1	1	79446	42592	5837	6046	6003	10000	50100	80157	79353	79693	79842	79925
60204	80267	604	0	0	0	0	0	0	0	277	0	9	1	0	539	79622	10	107	0	66	79549	25	53435	42768	10640	40100	10000	704013	3070435	1	49	77581	0	79304	80523	71934	3	72126	50100	40200	20000	70200	10000	80782	35	1	1	40201	100	99	100	10000	30100	10000	100	10017	0	618	10133	0	9	9	137	10154	1250	4	521	132	4	569	0	0	0	0	2610	1	57	1	1	79895	42600	5854	5920	5815	10000	50100	80341	79555	79786	80339	79905
60204	80085	595	0	0	0	0	0	0	0	251	0	9	1	0	503	80248	9	130	0	70	79213	25	53365	42672	10634	40100	10000	696569	3068124	1	49	77811	0	79914	80063	71918	3	72474	50100	40200	20000	70200	10000	79878	35	1	1	40201	100	99	100	10000	30100	10000	100	10015	0	587	10160	0	11	9	132	10140	1250	4	538	128	4	528	1	0	0	0	2610	1	56	1	1	80086	42536	5814	5612	5899	10000	50100	79442	79735	80300	79581	79747
60204	80787	600	1	1	1	0	0	0	0	289	0	10	1	0	501	79992	7	120	0	59	79726	25	53295	42532	10650	40100	10000	688295	3033481	1	49	76424	0	79559	79714	71721	3	71959	50100	40200	20000	70200	10000	79651	35	1	1	40201	100	99	100	10000	30100	10000	100	10015	0	572	10126	0	16	9	132	10138	1250	4	532	124	4	485	0	0	0	0	2610	1	56	1	1	79248	42476	5605	5652	5783	10000	50100	79904	79249	79221	79683	79822

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.8656

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0f	18	19	1e	1f	20	22	23	3a	3f	40	43	46	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	ldst x64 uop (b1)	ldst xpg uop (b2)	b5	bb	be	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60029	83567	595	0	0	0	0	0	0	0	0	138	0	9	1	0	498	78275	7	0	0	0	78381	25	52415	42006	10601	40010	10000	679488	2979130	49	75710	78171	78394	71413	3	71212	50010	40020	20000	70020	10000	79276	35	2	1	40021	10	9	10	10000	30010	10000	0	10	10015	2	527	10018	12	7	18	10015	1250	4	601	9	4	480	1	1	0	0	2520	2	64	1	1	78234	41952	5490	5540	5310	10000	50010	78087	78983	78932	78624	78626
60024	78737	589	1	0	0	0	1	0	0	0	131	0	7	1	0	501	78445	10	0	0	0	78428	25	52605	41918	10509	40010	10000	677279	2993228	49	75946	78569	79272	70541	3	71333	50010	40020	20000	70020	10000	78863	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10017	2	485	10018	8	8	12	10015	1250	4	523	10	4	495	1	0	0	0	2520	1	64	1	1	79193	42000	5241	5371	5528	10000	50010	78322	78181	78693	78730	78935
60024	78656	587	1	0	1	0	0	0	0	0	144	0	7	1	0	459	78587	7	0	1	0	77903	25	52485	42062	10489	40010	10000	679556	3040206	49	75823	78582	78815	71014	3	71144	50010	40020	20000	70020	10000	78772	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10018	1	499	10018	13	8	18	10016	1250	4	500	11	4	582	1	0	0	0	2520	1	64	1	1	78479	41980	5556	5337	5431	10000	50010	78814	78839	78820	78638	78732
60024	78558	587	1	0	0	0	0	0	0	0	140	0	7	1	0	468	78484	7	0	1	0	78619	25	52760	42110	10511	40010	10000	676938	2998327	49	75515	78611	78266	70795	3	72091	50010	40020	20000	70020	10000	79511	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10018	2	465	10022	11	7	15	10017	1250	4	500	9	4	453	1	0	0	0	2520	1	64	1	1	78182	42008	5316	5349	5397	10000	50010	79150	78660	78581	78418	78817
60024	78804	589	0	0	0	0	0	0	0	0	125	0	9	1	0	449	78512	10	0	0	0	78553	25	52570	41998	10496	40010	10000	679205	3000222	49	75594	78634	78790	70794	3	71005	50010	40020	20000	70020	10000	78779	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10018	2	487	10019	16	8	21	10016	1250	4	500	9	4	534	1	0	0	0	2520	1	64	1	1	79021	42104	5752	5384	5341	10000	50010	78918	78620	78630	78711	79009
60024	78950	591	1	0	1	0	0	0	0	0	147	0	7	1	0	544	79261	9	0	0	0	78715	25	52550	42066	10503	40010	10000	688244	3025871	49	75587	79004	78387	70987	3	71571	50010	40020	20000	70020	10000	78610	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10016	2	514	10016	13	9	20	10019	1250	4	498	10	4	508	1	1	0	0	2520	1	64	1	1	79243	42132	5998	6037	5974	10000	50010	78763	78460	79651	78844	78804
60024	78755	592	1	0	1	0	1	0	0	0	137	0	9	1	0	476	78640	11	0	0	0	78248	25	52455	42050	10521	40010	10000	682580	3038518	49	75520	78897	78867	70462	3	71433	50010	40020	20000	70020	10000	78890	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10016	1	497	10018	7	11	16	10014	1250	4	481	11	4	484	1	1	0	0	2520	1	64	1	1	78453	42112	6033	5782	5730	10000	50010	78691	78860	78801	79086	78868
60024	78779	592	1	0	1	0	1	0	0	0	152	0	7	1	0	480	78507	9	0	1	0	78894	25	52520	42046	10497	40010	10000	678998	3044094	49	76233	78230	78209	70778	3	71654	50010	40020	20000	70020	10000	79370	35	2	1	40021	10	9	10	10000	30010	10000	0	10	10014	0	495	10020	12	7	15	10017	1250	4	501	9	4	508	0	0	0	0	2520	1	64	1	2	78612	42048	5700	5591	5786	10000	50010	78980	78707	80900	80297	78623
60024	78658	586	0	0	0	0	0	0	0	0	135	0	7	1	0	464	78450	6	0	0	1	78796	25	52470	42218	10496	40010	10000	681527	3004827	49	75600	79104	78808	71140	3	71458	50010	40020	20000	70020	10000	79070	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10017	3	530	10017	16	8	15	10016	1250	4	505	11	4	482	1	0	0	0	2520	1	64	1	1	78596	41936	5309	5332	5816	10000	50010	78306	78353	78273	78186	78639
60024	78735	589	1	0	1	0	0	0	0	0	159	0	7	1	0	502	78562	10	0	1	1	78171	25	52520	42082	10501	40010	10000	682193	3045017	49	75545	78684	79051	71015	3	71512	50010	40020	20000	70020	10000	78751	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10019	2	510	10018	15	9	15	10021	1250	4	489	11	4	498	1	0	0	0	2520	1	64	1	1	78455	42068	5686	5056	5346	10000	50010	78760	78159	78643	79516	78308

Test 4: throughput

Count: 8

Code:

  ldp x0, x1, [x6], #8
  ldp x0, x1, [x7], #8
  ldp x0, x1, [x8], #8
  ldp x0, x1, [x9], #8
  ldp x0, x1, [x10], #8
  ldp x0, x1, [x11], #8
  ldp x0, x1, [x12], #8
  ldp x0, x1, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.4083

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	ldst x64 uop (b1)	ldst xpg uop (b2)	b5	b6	bb	be	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240209	32983	246	0	0	0	0	0	0	7676	852	1	528	461	160	32727	841	706	1468	1306	1812	801	160154	80138	80012	80118	80019	400673	692943	0	24	49	29497	32662	32999	1463	1048	8	2717	160137	80218	160038	80218	80019	32376	38	1	1	80201	100	99	13	100	80000	100	80000	100	80961	8	492	4743	85533	737	11	968	92	5543	86126	10000	32	622	126	5944	32	4549	0	0	3	1	1	1	5118	0	16	0	0	32878	154	80034	539	522	3	80000	160100	32527	32470	32666	32857	32773
240204	32895	246	1	1	0	0	1	0	7212	803	1	560	465	144	32700	769	723	1459	1604	1530	753	160150	80131	80011	80118	80019	400634	691053	0	28	49	29711	32445	32513	1522	1244	7	2426	160137	80218	160038	80218	80019	32687	38	1	1	80201	100	99	22	100	80000	100	80000	100	80992	16	409	4746	85928	727	12	936	76	6261	86230	10000	32	694	123	5692	32	4983	16	7	0	1	1	1	5118	0	16	0	0	32744	170	80050	718	665	2	80000	160100	32708	32694	32553	32740	32913
240204	32553	243	1	0	0	0	1	0	7517	813	1	640	489	148	32819	807	707	1566	1343	1735	795	160118	80121	80000	80100	80000	400555	660962	1	30	49	29580	32673	32550	1378	1017	3	2657	160100	80200	160000	80200	80000	32831	38	1	1	80201	100	99	4	100	80000	100	80000	100	81004	17	494	4489	85941	760	10	950	90	5625	86497	10000	32	634	140	5015	32	5250	16	0	16	0	0	0	5110	1	16	1	1	32630	150	80023	636	555	13	80000	160100	32805	32561	32414	33001	32699
240204	32949	245	1	1	0	0	1	0	7621	821	1	720	466	196	32594	840	694	1474	1277	1628	736	160130	80118	80000	80100	80000	400557	632989	1	25	49	29555	32725	32586	1369	1024	3	2574	160100	80200	160000	80200	80000	32624	38	1	1	80201	100	99	26	100	80000	100	80000	100	81010	15	423	5033	85426	747	11	942	34	5965	86140	10000	32	608	129	5957	32	6365	16	6	2	0	0	0	5110	1	16	1	1	32742	156	80023	566	506	3	80000	160100	32704	32779	32787	32636	32546
240204	32638	244	1	0	0	0	0	0	6959	825	1	784	435	136	32667	805	685	1505	1398	1587	749	160128	80115	80000	80100	80000	400585	654478	1	24	49	29620	32632	32628	1727	1021	3	2823	160100	80200	160000	80200	80000	32658	38	1	1	80201	100	99	16	100	80000	100	80000	100	81005	16	391	5305	86367	759	9	917	170	6058	86613	10000	32	624	114	5967	32	4683	16	0	4	0	0	0	5110	1	16	1	1	32632	138	80022	587	565	5	80000	160100	32863	32471	32690	32762	32952
240204	32544	245	1	0	0	1	1	0	7502	809	1	672	467	96	32550	814	662	1334	1640	1478	749	160128	80122	80000	80100	80000	400586	702512	0	29	49	29565	32684	32423	1661	1142	3	2755	160100	80200	160000	80200	80000	32637	38	1	1	80201	100	99	15	100	80000	100	80000	100	80977	16	452	5655	85454	788	11	901	34	5314	86592	10000	32	689	120	6023	32	4747	16	1	0	0	0	0	5110	1	16	1	1	32543	169	80026	501	541	7	80000	160100	32537	32738	32872	32559	32731
240204	32715	242	1	1	0	1	0	0	8117	808	1	760	448	140	32552	807	644	1388	1639	1452	799	160129	80119	80000	80100	80000	400606	682541	1	29	49	29749	32566	32747	1359	1039	3	2337	160100	80200	160000	80200	80000	32611	38	1	1	80201	100	99	17	100	80000	100	80000	100	81014	15	434	5448	87070	795	9	928	94	5681	87335	10000	32	688	126	6043	32	4777	15	0	5	0	0	0	5110	1	16	1	1	32616	172	80029	607	561	7	80000	160100	32604	32655	32711	32825	32520
240204	32500	244	1	0	0	0	0	0	7101	815	1	632	369	116	32843	789	758	1521	1543	1711	755	160133	80127	80000	80100	80000	400600	708626	1	23	49	29735	32812	32670	1719	1007	3	2678	160100	80200	160000	80200	80000	32797	38	1	1	80201	100	99	8	100	80000	100	80000	100	81002	16	431	5661	85998	748	11	902	84	5805	86598	10000	32	633	127	5326	32	5388	16	0	5	0	1	0	5110	1	16	1	1	32572	164	80023	679	545	4	80000	160100	32588	32455	32671	32844	32677
240204	32529	244	1	0	0	0	0	0	7683	834	1	728	433	96	32700	806	665	1289	1467	1625	754	160137	80123	80000	80100	80000	400577	677603	1	22	49	29560	32582	32488	1650	1093	3	2558	160100	80200	160000	80200	80000	32696	38	1	1	80201	100	99	36	100	80000	100	80000	100	81002	17	421	5069	86228	773	12	919	36	6396	86566	10000	32	648	129	5826	32	4660	16	0	5	0	0	0	5110	1	16	1	1	32599	161	80022	532	550	4	80000	160100	32589	32731	32936	32725	32894
240204	32654	242	1	0	0	0	1	0	7549	802	1	752	479	264	32526	806	615	1275	1420	1549	764	160124	80125	80000	80100	80000	400551	688235	0	29	49	29636	32592	32599	1870	1204	3	2483	160100	80200	160000	80200	80000	32626	38	1	1	80201	100	99	33	100	80000	100	80000	100	81000	16	450	4879	86368	748	13	870	100	5474	86741	10000	32	574	112	5647	32	4735	16	0	9	0	0	0	5110	1	16	1	1	32427	161	80025	555	485	3	80000	160100	32502	32309	32490	32663	32965

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.4074

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	1e	1f	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	61	67	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	ldst x64 uop (b1)	ldst xpg uop (b2)	b5	b6	bb	be	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch mispred nonspec (cb)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240029	33086	243	1	0	0	0	1	0	7715	0	789	1	728	524	144	32483	808	673	1881	1988	1583	773	160042	80031	80000	80010	80000	400161	643119	0	0	0	30	49	29686	32491	32444	1627	1050	3	2595	160010	80020	160000	80020	80000	32340	38	1	1	80021	10	9	17	10	80000	10	80000	10	80913	8	410	6341	86055	763	17	866	56	5932	86174	10000	32	650	114	5862	32	4889	15	0	0	0	0	5020	0	0	0	16	16	0	17	6	32524	130	80020	438	442	2	80000	160010	32477	32695	32728	32817	32555
240024	32536	245	2	2	1	0	0	0	7336	0	834	1	728	555	180	32688	756	657	1764	2006	1646	866	160040	80047	80000	80010	80000	400165	663910	0	0	0	20	49	29627	32653	32653	1447	1078	3	2478	160010	80133	160225	80020	80000	32714	38	1	1	80021	10	9	0	10	80000	10	80000	10	80958	16	428	5868	85729	748	14	863	38	4910	86331	10000	32	651	126	5435	32	5452	16	1	12	0	0	5020	0	0	0	6	16	0	17	17	32675	151	80014	455	399	3	80000	160010	32644	32987	32598	32626	32444
240024	32631	243	1	0	0	0	0	0	8089	0	808	1	752	506	96	32402	801	643	1746	1856	1694	765	160035	80044	80000	80010	80000	400136	670884	0	0	0	32	49	29610	32800	32588	1316	1204	3	2480	160010	80020	160000	80020	80000	32577	38	1	1	80021	10	9	13	10	80000	10	80000	10	80967	16	410	4820	85721	784	12	902	40	5755	86215	10000	32	634	130	5875	32	4445	16	1	8	0	0	5020	0	0	0	17	15	0	17	6	32538	146	80023	414	409	1	80000	160010	32727	32430	32519	32282	32634
240024	32609	244	1	0	0	0	0	0	7228	0	816	1	720	530	128	32424	791	640	1716	1712	1220	825	160035	80032	80000	80010	80000	400135	663083	0	0	0	23	49	29325	32533	32520	1413	1027	3	2505	160010	80020	160000	80020	80000	32627	38	1	1	80021	10	9	9	10	80000	10	80000	10	80989	32	365	4912	85261	776	13	880	34	5981	86488	10000	32	674	133	6003	32	4891	32	0	0	0	0	5020	0	0	0	13	16	0	17	8	32523	149	80024	468	434	3	80000	160010	32640	32494	32494	32628	32646
240024	32703	244	1	1	0	0	0	0	7797	0	788	1	712	590	124	32458	777	665	1737	1882	1447	816	160028	80028	80000	80010	80000	400158	662874	0	0	0	26	49	29337	32471	32489	1435	1084	3	2622	160010	80020	160000	80020	80000	32479	38	1	1	80021	10	9	11	10	80000	10	80000	10	80977	15	428	5030	86389	755	13	832	32	6174	86998	10000	32	690	130	6010	32	4656	0	6	0	0	0	5020	0	0	0	6	16	0	17	6	32580	142	80026	371	480	4	80000	160010	32571	32730	32337	32539	32449
240024	32416	244	1	0	0	0	0	0	7755	0	831	1	688	502	92	32773	783	565	1956	1648	1657	760	160033	80040	80000	80010	80000	400120	672280	1	1	0	19	49	29432	32746	32540	1264	1102	3	2421	160010	80020	160000	80020	80000	32672	38	1	1	80021	10	9	9	10	80000	10	80000	10	80915	16	413	5553	85612	753	9	833	32	5715	86341	10000	32	611	129	6092	32	4549	16	0	3	0	0	5020	0	0	0	17	16	0	17	6	32520	155	80022	414	427	2	80000	160010	32493	32768	32506	32464	32387
240024	32573	246	0	0	0	0	0	0	7230	0	811	1	720	485	116	32813	777	663	1945	1887	1384	805	160030	80033	80000	80010	80000	400165	675929	0	0	0	27	49	29368	32761	32527	1377	1162	3	2662	160010	80130	160000	80020	80000	32666	38	1	1	80021	10	9	10	10	80000	10	80000	10	80992	0	375	5320	85451	759	14	848	50	5910	86860	10000	32	605	132	5861	32	4662	0	0	0	0	0	5020	0	0	0	8	15	0	17	8	32426	147	80020	497	417	0	80000	160010	32579	32631	32648	32640	32561
240024	32784	244	0	0	0	0	0	0	6493	0	779	1	648	557	132	32645	734	641	1757	1729	1397	849	160037	80039	80000	80010	80000	400157	660872	0	1	0	25	49	29278	32591	32439	1313	1042	3	2465	160010	80020	160000	80020	80000	32696	38	1	1	80021	10	9	6	10	80000	10	80000	10	80924	0	413	5628	85925	754	9	864	50	5807	86911	10000	32	592	111	5651	32	4937	0	0	11	0	0	5020	0	0	0	17	16	0	17	17	32437	142	80017	399	466	12	80000	160010	32474	32666	32449	32611	32599
240024	32290	243	0	0	0	0	0	0	7578	0	788	1	680	540	96	32952	765	739	1791	1810	1432	803	160035	80034	80000	80010	80000	400155	655560	0	0	0	24	49	29414	32794	32708	1496	1077	3	2467	160010	80020	160000	80020	80000	32723	38	1	1	80021	10	9	5	10	80000	10	80000	10	80944	0	424	5038	86257	782	15	885	42	6182	86152	10000	32	636	133	5446	32	4797	0	0	6	0	0	5020	0	0	0	17	15	0	8	17	32553	157	80021	414	351	4	80000	160010	32624	32476	32561	32636	32379
240024	32657	244	1	0	0	0	0	0	7357	0	789	1	680	572	144	32518	760	665	2061	1731	1419	833	160030	80033	80000	80010	80000	400141	645569	0	1	0	28	49	29541	32283	32408	1425	1174	3	2741	160010	80020	160000	80020	80000	32506	38	1	1	80021	10	9	5	10	80000	10	80000	10	80910	0	411	5410	85879	769	20	862	24	6270	86951	10000	32	604	132	5962	32	4747	16	0	3	0	0	5020	0	0	0	17	16	0	17	17	32485	140	80029	411	363	1	80000	160010	32336	32586	32595	32570	32333

LDP (post-index, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations