Firestorm: SUBS (shifted immediate, 64-bit) measurements

Code:

  subs x0, x0, #3, lsl #12

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1035	7	0	0	0	0	0	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	1000	1035	40	1	1	1001	1000	0	0	0	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	0	0	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	1000	1035	40	1	1	1001	1000	0	0	0	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	0	0	0	0	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	1000	1035	40	1	1	1001	1000	0	0	0	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	0	3	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	1000	1035	40	1	1	1001	1000	0	0	0	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	0	0	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	1000	1035	40	1	1	1001	1000	0	0	0	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	0	0	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	1000	1035	40	1	1	1001	1000	0	0	0	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	0	0	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	1000	1035	40	1	1	1001	1000	0	0	0	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	0	0	0	82	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	1000	1035	40	1	1	1001	1000	0	0	0	0	3	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	0	0	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	1000	1035	40	1	1	1001	1000	0	0	0	0	3	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	0	0	0	0	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	1000	1035	40	1	1	1001	1000	0	0	0	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036

Test 2: Latency 1->2

Code:

  subs x0, x0, #3, lsl #12

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	21	0	82	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	10200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	10200	10035	40	1	1	10201	100	99	100	10100	100	0	1	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	82	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	10200	10035	40	1	1	10201	100	99	100	10100	100	0	4	171	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	103	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	10200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	10200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	10200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	103	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	10200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	10200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	10200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	10200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	76	0	0	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	10020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	10020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	10020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	3	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	10020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	10020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	10020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	10020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	156	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	10020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	10020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	10020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036

Test 3: Latency 3->2

Chain cycles: 1

Code:

  subs x0, x1, #3, lsl #12
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	61	19930	25	20100	20100	20192	1297233	49	16955	20035	20035	17425	11	17485	20112	20224	20224	20080	64	1	1	20201	100	99	100	20100	10100	2	0	0	0	0	0	1	1	1	1320	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17432	7	17486	20112	20224	20224	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20192	1297839	49	17000	20035	20035	17425	10	17534	20200	20319	20224	20082	64	2	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	9	764	19930	46	20100	20100	20112	1297233	49	17000	20035	20035	17444	15	17486	20112	20224	20224	20035	64	1	1	20201	100	99	100	20100	10100	0	2	0	0	848	2	1	1	1	1320	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	149	18	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	7	17486	20112	20224	20224	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1320	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	103	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	7	17485	20112	20224	20224	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	103	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	7	17486	20112	20224	20224	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1320	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	12	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	7	17486	20112	20224	20224	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	187	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	8	17486	20112	20224	20224	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1320	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	8	17485	20112	20224	20224	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20309	152	2	1	2	0	6	6	924	264	0	1615	19915	149	20120	20142	20502	1301642	1	49	17274	20354	20263	17476	19	17580	20338	20020	20117	20080	64	6	1	20021	10	9	10	20010	10010	2	2	2	0	2	1630	4	0	1355	5	69	6	3	20128	20110	20010	20265	20216	20081	20265	20036
20024	20263	152	0	1	0	1	5	4	534	440	1	1220	19918	108	20120	20054	20256	1299759	0	49	17135	20264	20263	17482	17	17607	20256	20495	20020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	1270	2	27	2	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	20020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	1270	2	27	2	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	20020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	1270	2	27	3	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	20020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	1270	2	27	2	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	20020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	1270	2	27	2	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	20020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	1270	2	27	2	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	20020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	1270	2	27	2	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	20020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	1270	2	27	2	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	20020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	1270	2	27	2	2	19995	20000	20010	20036	20036	20036	20036	20036

Test 4: throughput

Count: 8

Code:

  subs x0, x8, #3, lsl #12
  subs x1, x8, #3, lsl #12
  subs x2, x8, #3, lsl #12
  subs x3, x8, #3, lsl #12
  subs x4, x8, #3, lsl #12
  subs x5, x8, #3, lsl #12
  subs x6, x8, #3, lsl #12
  subs x7, x8, #3, lsl #12

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26763	200	0	0	93	29	80115	80115	80121	400590	0	49	23661	0	26741	26741	16679	8	16689	80121	80232	80232	26741	39	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5119	0	16	0	0	26738	80015	80100	26742	26742	26742	26742	26742
80204	26741	200	0	0	28	29	80115	80115	80121	400590	0	49	23661	0	26741	26741	16679	8	16689	80121	80232	80232	26741	39	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5120	0	16	0	0	26738	80015	80100	26742	26742	26742	26742	26742
80204	26741	200	0	0	116	25	80100	80100	80100	400500	0	49	23655	0	26735	26735	16672	3	16690	80100	80200	80200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	19	1	1	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	35	25	80100	80100	80100	400500	0	49	23655	0	26735	26735	16672	3	16690	80100	80200	80200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	19	1	1	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	144	25	80100	80100	80100	400500	1	49	23655	0	26735	26735	16672	3	16690	80100	80200	80200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	19	1	1	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	144	25	80100	80100	80100	400500	0	49	23655	0	26735	26735	16672	3	16690	80100	80200	80200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	19	1	1	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	575	25	80100	80100	80100	400500	0	49	23655	0	26735	26735	16672	3	16690	80100	80200	80200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	19	1	1	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	123	25	80100	80100	80100	400500	0	49	23655	0	26735	26735	16672	3	16690	80100	80200	80200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	19	1	1	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	35	25	80100	80100	80100	400500	0	49	23655	0	26735	26735	16672	3	16690	80100	80200	80200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	19	1	1	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	201	0	0	123	25	80100	80100	80100	400500	0	49	23655	0	26735	26735	16672	3	16690	80100	80200	80200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	19	1	1	26731	80000	80100	26736	26736	26736	26736	26736

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	26712	200	0	35	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	3	16683	80010	80020	80020	26705	39	1	1	80021	10	9	10	80010	10	0	0	66	0	5020	16	18	10	14	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	35	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	3	16683	80010	80020	80020	26705	39	1	1	80021	10	9	10	80010	10	0	0	66	0	5020	17	18	14	11	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	917	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	3	16683	80010	80020	80020	26705	39	1	1	80021	10	9	10	80010	10	0	18	0	0	5020	10	18	17	13	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	35	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	3	16710	80078	80020	80020	26705	39	1	1	80021	10	9	10	80010	10	0	0	102	0	5020	13	18	9	14	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	35	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	3	16683	80010	80020	80020	26705	39	1	1	80021	10	9	10	80010	10	0	0	93	0	5020	15	18	16	17	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	510	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	3	16683	80010	80020	80020	26705	39	1	1	80021	10	9	10	80010	10	0	0	54	0	5020	16	18	20	15	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	35	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	3	16683	80010	80020	80020	26705	39	1	1	80021	10	9	10	80010	10	0	0	63	0	5020	15	18	16	13	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	35	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	3	16683	80010	80020	80020	26705	39	1	1	80021	10	9	10	80010	10	0	0	66	0	5020	15	18	16	13	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	35	25	80010	80010	80010	400050	1	49	23625	26705	26751	16665	3	16683	80010	80020	80020	26705	39	1	1	80021	10	9	10	80010	10	0	0	93	0	5020	11	18	14	14	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	35	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	3	16683	80010	80020	80020	26705	39	1	1	80021	10	9	10	80010	10	0	0	60	0	5020	16	18	15	11	26702	80000	80010	26706	26706	26706	26706	26706

SUBS (shifted immediate, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations