Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SUBS (shifted immediate, 64-bit)

Test 1: uops

Code:

  subs x0, x0, #3, lsl #12
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100410357000000619172510001000100062250110351035805388210001000100010354011100110000000073127119931000100010361036103610361036
100410358000000619172510001000100062250110351035805388210001000100010354011100110000000073127119931000100010361036103610361036
100410357000000619172510001000100062250110351035805388210001000100010354011100110000000073127119931000100010361036103610361036
100410358000030619172510001000100062250110351035805388210001000100010354011100110000000073127119931000100010361036103610361036
100410358000000619172510001000100062250110351035805388210001000100010354011100110000000073127119931000100010361036103610361036
100410358000000619172510001000100062250110351035805388210001000100010354011100110000000073127119931000100010361036103610361036
100410358000000619172510001000100062250110351035805388210001000100010354011100110000000073127119931000100010361036103610361036
100410358000000829172510001000100062250110351035805388210001000100010354011100110000000373127119931000100010361036103610361036
100410358000000619172510001000100062250110351035805388210001000100010354011100110000000373127119931000100010361036103610361036
100410357000000619172510001000100062250110351035805388210001000100010354011100110000000073127119931000100010361036103610361036

Test 2: Latency 1->2

Code:

  subs x0, x0, #3, lsl #12
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e1f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102041003575210829920251010010100101006471521496955100351003586563873210100102001020010035401110201100991001010010000071012711999510000101001003610036100361003610036
10204100357500619920251010010100101006471521496955100351003586563873210100102001020010035401110201100991001010010001071012711999510000101001003610036100361003610036
1020410035750082992025101001010010100647152149695510035100358656387321010010200102001003540111020110099100101001000417171012711999510000101001003610036100361003610036
102041003575001039920251010010100101006471521496955100351003586563873210100102001020010035401110201100991001010010000071012711999510000101001003610036100361003610036
10204100357500619920251010010100101006471521496955100351003586563873210100102001020010035401110201100991001010010000071012711999510000101001003610036100361003610036
10204100357500619920251010010100101006471521496955100351003586563873210100102001020010035401110201100991001010010000071012711999510000101001003610036100361003610036
102041003575001039920251010010100101006471521496955100351003586563873210100102001020010035401110201100991001010010000071012711999510000101001003610036100361003610036
10204100357500619920251010010100101006471521496955100351003586563873210100102001020010035401110201100991001010010000071012711999510000101001003610036100361003610036
10204100357500619920251010010100101006471521496955100351003586563873210100102001020010035401110201100991001010010000071012711999510000101001003610036100361003610036
10204100357500619920251010010100101006471521496955100351003586563873210100102001020010035401110201100991001010010000071012711999510000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1002410035760000619918251001010010100106472460496955100351003586783875410010100201002010035401110021109101001010000064022722999710000100101003610036100361003610036
1002410035750000619918251001010010100106472460496955100351003586783875410010100201002010035401110021109101001010000064022722999710000100101003610036100361003610036
1002410035750000619918251001010010100106472461496955100351003586783875410010100201002010035401110021109101001010000364022722999710000100101003610036100361003610036
1002410035750000619918251001010010100106472461496955100351003586783875410010100201002010035401110021109101001010000064022722999710000100101003610036100361003610036
1002410035750000619918251001010010100106472460496955100351003586783875410010100201002010035401110021109101001010000064022722999710000100101003610036100361003610036
1002410035750000619918251001010010100106472460496955100351003586783875410010100201002010035401110021109101001010000064022722999710000100101003610036100361003610036
1002410035750000619918251001010010100106472460496955100351003586783875410010100201002010035401110021109101001010000064022722999710000100101003610036100361003610036
10024100357500001569918251001010010100106472460496955100351003586783875410010100201002010035401110021109101001010000064022722999710000100101003610036100361003610036
1002410035750000619918251001010010100106472460496955100351003586783875410010100201002010035401110021109101001010000064022722999710000100101003610036100361003610036
1002410035750000619918251001010010100106472460496955100351003586783875410010100201002010035401110021109101001010000064022722999710000100101003610036100361003610036

Test 3: Latency 3->2

Chain cycles: 1

Code:

  subs x0, x1, #3, lsl #12
  cset x1, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20204200351500611993025201002010020192129723349169552003520035174251117485201122022420224200806411202011009910020100101002000001111320162001220000201002003620036200362003620036
2020420035150061199302520100201002011212972334916955200352003517432717486201122022420224200356411202011009910020100101000000001111319162001220000201002003620036200362003620036
20204200351500611993025201002010020192129783949170002003520035174251017534202002031920224200826421202011009910020100101000000001111319162001220000201002003620036200362003620036
20204200351509764199304620100201002011212972334917000200352003517444151748620112202242022420035641120201100991002010010100020084821111320162001220000201002003620036200362003620036
20204200351491861199302520100201002011212972334916955200352003517425717486201122022420224200356411202011009910020100101000000001111320162001220000201002003620036200362003620036
20204200351500103199302520100201002011212972334916955200352003517425717485201122022420224200356411202011009910020100101000000001111319162001220000201002003620036200362003620036
20204200351500103199302520100201002011212972334916955200352003517425717486201122022420224200356411202011009910020100101000000001111320162001220000201002003620036200362003620036
20204200351501261199302520100201002011212972334916955200352003517425717486201122022420224200356411202011009910020100101000000001111319162001220000201002003620036200362003620036
20204200351500187199302520100201002011212972334916955200352003517425817486201122022420224200356411202011009910020100101000000001111320162001220000201002003620036200362003620036
2020420035150061199302520100201002011212972334916955200352003517425817485201122022420224200356411202011009910020100101000000001111319162001220000201002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20024203091522120669242640161519915149201202014220502130164214917274203542026317476191758020338200202011720080646120021109102001010010222021630401355569632012820110200102026520216200812026520036
20024202631520101545344401122019918108201202005420256129975904917135202642026317482171760720256204952002020035641120021109102001010010000000001270227221999520000200102003620036200362003620036
200242003515000000000061199182520010200102001012972470491695520035200351742831750420010200202002020035641120021109102001010010000000001270227221999520000200102003620036200362003620036
200242003515000000000061199182520010200102001012972471491695520035200351742831750420010200202002020035641120021109102001010010000000001270227321999520000200102003620036200362003620036
200242003515000000000061199182520010200102001012972470491695520035200351742831750420010200202002020035641120021109102001010010000000001270227221999520000200102003620036200362003620036
200242003515000000000061199182520010200102001012972470491695520035200351742831750420010200202002020035641120021109102001010010000000001270227221999520000200102003620036200362003620036
200242003515000000000061199182520010200102001012972470491695520035200351742831750420010200202002020035641120021109102001010010000000001270227221999520000200102003620036200362003620036
200242003515000000000061199182520010200102001012972470491695520035200351742831750420010200202002020035641120021109102001010010000000001270227221999520000200102003620036200362003620036
200242003515000000000061199182520010200102001012972470491695520035200351742831750420010200202002020035641120021109102001010010000000001270227221999520000200102003620036200362003620036
200242003515000000000061199182520010200102001012972470491695520035200351742831750420010200202002020035641120021109102001010010000000001270227221999520000200102003620036200362003620036

Test 4: throughput

Count: 8

Code:

  subs x0, x8, #3, lsl #12
  subs x1, x8, #3, lsl #12
  subs x2, x8, #3, lsl #12
  subs x3, x8, #3, lsl #12
  subs x4, x8, #3, lsl #12
  subs x5, x8, #3, lsl #12
  subs x6, x8, #3, lsl #12
  subs x7, x8, #3, lsl #12
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8020426763200009329801158011580121400590049236610267412674116679816689801218023280232267413911802011009910080100100001115119016002673880015801002674226742267422674226742
8020426741200002829801158011580121400590049236610267412674116679816689801218023280232267413911802011009910080100100001115120016002673880015801002674226742267422674226742
80204267412000011625801008010080100400500049236550267352673516672316690801008020080200267353911802011009910080100100000005110119112673180000801002673626736267362673626736
8020426735200003525801008010080100400500049236550267352673516672316690801008020080200267353911802011009910080100100000005110119112673180000801002673626736267362673626736
80204267352000014425801008010080100400500149236550267352673516672316690801008020080200267353911802011009910080100100000005110119112673180000801002673626736267362673626736
80204267352000014425801008010080100400500049236550267352673516672316690801008020080200267353911802011009910080100100000005110119112673180000801002673626736267362673626736
80204267352000057525801008010080100400500049236550267352673516672316690801008020080200267353911802011009910080100100000005110119112673180000801002673626736267362673626736
80204267352000012325801008010080100400500049236550267352673516672316690801008020080200267353911802011009910080100100000005110119112673180000801002673626736267362673626736
8020426735200003525801008010080100400500049236550267352673516672316690801008020080200267353911802011009910080100100000005110119112673180000801002673626736267362673626736
80204267352010012325801008010080100400500049236550267352673516672316690801008020080200267353911802011009910080100100000005110119112673180000801002673626736267362673626736

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8002426712200035258001080010800104000501492362526705267051666531668380010800208002026705391180021109108001010006605020161810142670280000800102670626706267062670626706
8002426705200035258001080010800104000501492362526705267051666531668380010800208002026705391180021109108001010006605020171814112670280000800102670626706267062670626706
80024267052000917258001080010800104000501492362526705267051666531668380010800208002026705391180021109108001010018005020101817132670280000800102670626706267062670626706
8002426705200035258001080010800104000501492362526705267051666531671080078800208002026705391180021109108001010001020502013189142670280000800102670626706267062670626706
8002426705200035258001080010800104000501492362526705267051666531668380010800208002026705391180021109108001010009305020151816172670280000800102670626706267062670626706
80024267052000510258001080010800104000501492362526705267051666531668380010800208002026705391180021109108001010005405020161820152670280000800102670626706267062670626706
8002426705200035258001080010800104000501492362526705267051666531668380010800208002026705391180021109108001010006305020151816132670280000800102670626706267062670626706
8002426705200035258001080010800104000501492362526705267051666531668380010800208002026705391180021109108001010006605020151816132670280000800102670626706267062670626706
8002426705200035258001080010800104000501492362526705267511666531668380010800208002026705391180021109108001010009305020111814142670280000800102670626706267062670626706
8002426705200035258001080010800104000501492362526705267051666531668380010800208002026705391180021109108001010006005020161815112670280000800102670626706267062670626706