Firestorm: MSR (NZCV) measurements

Code:

  msr nzcv, x0

Initialization

  mrs x0, nzcv

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	l1d tlb miss (a1)	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	f5	f6	f7	f8	fd
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	370	3	388	1000	1000	1000	535	90	1	1	1001	0	0	73	2	21	2	2	529	1000	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	370	3	388	1000	1000	1000	535	90	1	1	1001	0	0	73	2	21	2	2	529	1000	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	370	3	388	1000	1000	1000	535	90	1	1	1001	0	0	73	2	21	2	2	529	1000	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	370	3	388	1000	1000	1000	535	90	1	1	1001	0	0	73	2	21	2	2	529	1000	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	370	3	388	1000	1000	1000	535	90	1	1	1001	0	0	73	2	21	2	2	529	1000	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	370	3	388	1000	1000	1000	535	90	1	1	1001	0	0	73	2	21	2	2	529	1000	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	370	3	388	1000	1000	1000	535	90	1	1	1001	0	0	73	2	21	2	2	529	1000	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	370	3	388	1000	1000	1000	535	90	1	1	1001	0	0	73	2	21	2	2	529	1000	536	536	536	536	536
1004	535	4	0	56	25	1000	1000	1000	5000	1	535	535	370	3	388	1000	1000	1000	535	90	1	1	1001	0	0	73	2	21	2	2	529	1000	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	370	3	388	1000	1000	1000	535	90	1	1	1001	0	0	73	2	21	2	2	529	1000	536	536	536	536	536

Code:

  msr nzcv, x0

Initialization

  mrs x0, nzcv

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 0.5090

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	5137	40	0	0	28	28	10110	10110	10114	50560	1	49	2010	5090	5090	3779	7	3789	10114	10224	10224	5090	90	1	1	10201	100	99	100	100	100	0	0	1	1	1	719	0	16	5087	10010	100	5091	5091	5091	5091	5091
10204	5090	39	0	0	28	28	10110	10110	10114	50560	1	49	2009	5090	5090	3779	7	3789	10114	10224	10224	5090	90	1	1	10201	100	99	100	100	100	0	0	1	1	1	719	0	16	5087	10010	100	5090	5091	5091	5091	5091
10204	5090	40	0	0	28	28	10110	10110	10114	50560	1	49	2010	5090	5090	3779	7	3789	10114	10224	10224	5090	90	1	1	10201	100	99	100	100	100	0	9	1	1	1	719	0	16	5087	10010	100	5091	5091	5091	5091	5091
10204	5090	39	0	0	28	28	10110	10110	10114	50560	1	49	2010	5090	5089	3779	7	3789	10114	10224	10224	5090	90	1	1	10201	100	99	100	100	100	2	0	1	1	1	719	0	16	5087	10010	100	5091	5091	5091	5091	5091
10204	5090	40	0	0	28	28	10110	10110	10114	50560	1	49	2010	5090	5090	3779	7	3789	10114	10224	10224	5090	90	1	1	10201	100	99	100	100	100	0	0	1	1	1	719	0	16	5087	10010	100	5091	5091	5090	5091	5091
10204	5090	39	0	0	28	28	10110	10110	10114	50560	1	49	2010	5090	5090	3779	7	3789	10114	10224	10224	5090	90	1	1	10201	100	99	100	100	100	0	57	1	1	1	719	1	16	5087	10010	100	5091	5091	5091	5091	5091
10204	5090	39	0	0	28	28	10110	10110	10114	50560	1	49	2010	5090	5090	3779	7	3789	10114	10224	10224	5090	90	1	1	10201	100	99	100	100	100	0	0	1	1	1	719	0	16	5087	10010	100	5091	5091	5091	5091	5091
10204	5090	39	0	0	28	28	10110	10110	10114	50560	1	49	2010	5090	5090	3779	7	3789	10114	10224	10224	5090	90	1	1	10201	100	99	100	100	100	0	0	1	1	1	719	0	16	5087	10010	100	5091	5091	5091	5090	5090
10204	5090	40	0	0	28	28	10110	10110	10114	50560	1	49	2010	5090	5090	3779	7	3789	10114	10224	10224	5090	90	1	1	10201	100	99	100	100	100	0	0	1	1	1	719	0	16	5087	10010	100	5091	5091	5091	5091	5091
10204	5090	39	0	0	112	28	10110	10110	10114	50560	1	49	2010	5090	5090	3779	7	3789	10114	10224	10224	5090	90	1	1	10201	100	99	100	100	100	0	0	1	1	1	719	0	16	5087	10010	100	5091	5091	5091	5091	5091

1000 unrolls and 10 iterations

Result (median cycles for code): 0.5040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	5044	39	12	140	25	10010	10010	10010	50050	49	1960	5040	5040	3748	3	3766	10010	10020	10020	5040	90	1	1	10021	10	9	10	10	10	0	0	0	0	640	4	20	4	3	5036	10000	10	5041	5041	5041	5041	5041
10024	5040	39	12	35	25	10010	10010	10010	50050	49	2006	5125	5086	3748	3	3766	10010	10020	10020	5040	90	1	1	10021	10	9	10	10	10	0	0	0	0	640	4	20	4	3	5036	10000	10	5041	5041	5041	5041	5041
10024	5040	39	0	35	25	10010	10010	10010	50050	49	1960	5040	5040	3748	3	3766	10010	10020	10020	5040	90	1	1	10021	10	9	10	10	10	0	0	0	0	640	3	20	3	1	5036	10000	10	5041	5041	5041	5041	5041
10024	5040	39	0	35	25	10010	10010	10010	50050	49	1960	5040	5040	3748	3	3766	10010	10020	10020	5040	90	1	1	10021	10	9	10	10	10	0	0	0	3	640	3	20	3	3	5036	10000	10	5041	5041	5041	5041	5041
10024	5040	39	0	35	25	10010	10010	10010	50050	49	1960	5040	5040	3748	3	3766	10010	10020	10020	5040	90	1	1	10021	10	9	10	10	10	0	0	0	0	640	3	20	2	3	5036	10000	10	5041	5041	5041	5041	5041
10024	5040	39	0	58	25	10010	10010	10010	50050	49	1960	5040	5040	3748	3	3766	10010	10020	10020	5040	90	1	1	10021	10	9	10	10	10	0	0	0	0	640	4	20	4	3	5036	10000	10	5041	5041	5041	5041	5041
10024	5040	39	0	35	25	10010	10010	10010	50050	49	1960	5040	5040	3748	3	3766	10010	10020	10020	5040	90	1	1	10021	10	9	10	10	10	0	0	0	0	640	4	20	4	3	5036	10000	10	5041	5041	5041	5041	5041
10024	5040	39	0	56	25	10010	10010	10010	50050	49	1960	5040	5040	3748	3	3766	10010	10020	10020	5040	90	1	1	10021	10	9	10	10	10	0	0	0	0	640	4	20	3	4	5036	10000	10	5041	5041	5041	5041	5041
10024	5040	39	0	35	25	10010	10010	10010	50050	49	1960	5040	5040	3748	3	3766	10010	10020	10020	5040	90	1	1	10021	10	9	10	10	10	0	0	1	0	640	4	20	4	4	5036	10000	10	5041	5041	5041	5041	5041
10024	5040	39	0	35	25	10010	10010	10010	50050	49	1960	5040	5040	3748	3	3766	10010	10020	10020	5040	90	1	1	10021	10	9	10	10	10	0	0	0	3	640	4	20	4	3	5036	10000	10	5041	5041	5041	5041	5041

MSR (NZCV)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations