Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SUBS (register, lsr, 64-bit)

Test 1: uops

Code:

  subs x0, x0, x1, lsr #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100420351506110001862252000200010001262351203520351729318661000100020002035411110011000000731431119202000100020362036203620362036
100420351506110001862252000200010001262351203520351729318661000100020002035411110011000000731431119202000100020362036203620362036
1004203515606110001862252000200010001262350203520351729318661000100020002035411110011000000731431119202000100020362036203620362036
100420351606110001862252000200010001262351203520351729318661000100020002035411110011000000731431119202000100020362036203620362036
100420351596110001862252000200010001262351203520351729318661000100020002035411110011000000731431119202000100020362036203620362036
100420351506110001862252000200010001262351203520351729318661000100020002035411110011000000731431119202000100020362036203620362036
100420351506110001862252000200010001262350203520351729318661000100020002035411110011000000731431119202000100020362036203620362082
100420351506110001862252000200010001262351203520351729318661000100020002035411110011000000731431119202000100020362036203620362036
1004203515015610001862252000200010001262351203520351729318661000100020002035411110011000000731431119202000100020362036203620362036
100420351506110001862252000200010001262351203520351729318661000100020002035411110011000000731431119202000100020362036203620362036

Test 2: Latency 1->2

Code:

  subs x0, x0, x1, lsr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e3f4c4d5051schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9facc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204200351491561100001986202520100201001010013051214916955200352003518581031872010100102002020020035411110201100991001010010000710239221992220000101002003620036200362003620036
102042003515005931000019862200192520100201001010013051214916955200352003518581031872010100102002020020035411110201100991001010010030710239221992220000101002003620036200362003620036
10204200351500166100001986202520100201001010013051214916955200352003518581031872010100102002020020035411110201100991001010010000710239221992220000101002003620036200362003620036
10204200351500187100001986202520100201001010013051214916955200352003518581031872010100102002020020035411110201100991001010010000729239221992220000101002003620036200362003620036
1020420035149061100001986202520100201001010013051214916955200352003518581031872010100102002020020035411110201100991001010010000710239221992520000101002003620036200362003620036
1020420035150061100001986202520100201001010013051214916955200352003518581331872010100102002020020035411110201100991001010010000710239221992220000101002003620036200362003620036
10204200351500166100001986202520100201001010013051214916955200352003518581031872010100102002020020035411110201100991001010010000710239221992220000101002003620036200362003620036
10204200351500145100001986202520100201001010013051214916955200352003518581031872010100102002020020035411110201100991001010010000710239221992220000101002003620036200362003620036
1020420035150061100001986202520100201001033413051214916955200352003518581031872010100102002020020035411110201100991001010010000710239221992220000101002003620036200362003620036
1020420035150061100001986202520100201001010013051214916955200352003518581031872010100102002020020035411110201100991001010010000710239221992220000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024200351490061100001986225200102001010010130522904916955200352003518603318740100101002020020200354121100211091010010100000640241221993020000100102003620036200362003620036
10024200351500061100001986225200102001010010130522914916955200352003518603318740100101002020020200354111100211091010010100000640241221993020000100102003620036200362003620036
10024200351500061100001986225200102001010010130522904916955200352003518603318740100101002020020200354111100211091010010100000640241221993020000100102003620036200362003620036
10024200351500061100001986225200102001010010130522914916955200352003518603318740100101002020020200354111100211091010010100000640241221993020000100102003620036200362003620036
10024200351500061100001986225200122001210010130522914916955200352003518603318740100101002020020200354111100211091010010100000640241221993020002100102003620036200362003620036
10024200351490061100001986225200122001210012130522914916955200352003518603318740100101002020020200354111100211091010010100000640241221993020000100102003620036200362003620036
10024200351500061100001986225200102001010010130522904916955200352003518603318740100101002020020200354111100211091010010100000640241221993020000100102003620036200362003620036
10024200351500061100001986225200102001010010130522904916955200352003518603318740100101002020020200354111100211091010010100000640241221993020000100102003620036200362003620036
10024200351500061100001986225200102001010010130522904916955200352003518603318740100101002020020200354111100211091010010100700640241221993020000100102003620036200362003620036
10024200351500061100001986225200102001010010130522914916955200712003518603318740100101002020020200354111100211091010010100030640241221993020000100102003620036200362003620036

Test 3: Latency 1->3

Code:

  subs x0, x1, x0, lsr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)0318191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)c2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102042003515000006110000198622520100201001010013051214916955200352003518581318720101001020020200200354111102011009910010100100000007100139111992220000101002003620036200362003620036
102042003515000006110000198622520100201001010013051214916955200352003518581318720101001020020200200354111102011009910010100100000007100139111992220000101002003620036200362003620036
102042003515000006110000198622520100201001010013051214916955200352003518581318720101001020020200200354111102011009910010100100000007100139111992220000101002003620036200362003620036
102042003515000006110000198622520100201001010013051214916955200352003518581318720101001020020200200354111102011009910010100100000007100139111992220000101002003620036200362003620036
102042003515000008210000198622520100201001010013051214916955200352003518581318720101001020020200200354111102011009910010100100000007100139111992220000101002003620036200362003620036
102042003515000006110000198622520100201001010013051214916955200352003518581318720101001020020200200354111102011009910010100100000007100161111992220000101002003620036200362003620036
102042003515000006110000198622520100201001010013051214916955200352003518581318720101001020020898200354111102011009910010100100000107100139111992220000101002003620036200362003620036
10204200351500015906110000198622520100201001010013051214916955200352003518581318720101001020020200200354111102011009910010100100000007100139111992220000101002003620036200362003620036
102042003515000006110000198622520100201001010013051214916955200352003518581318720101001020020200200354111102011009910010100100000007100139111992220000101002003620036200362003620036
1020420035150000016810000198622520100201251010013051214916955200352003518581318720101001020020200200354111102011009910010100100000007100139111992220000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)1e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024200351500000611000019862252001020010100101305229049169552003520035186033187401001010020200202003541111002110910100101013640241221993020000100102003620036200362003620036
10024200351500000611000019862252001020010100101305229049169552003520035186033187401001010020200202003541111002110910100101010640241221993020000100102003620036200362003620036
10024200351500000611000019862252001020010100101305229049169552003520035186033187401001010020200202003541111002110910100101000640241221993020000100102003620036200362003620036
10024200351500000611000019862252001020010100101305229149169552003520035186033187401001010020200202003541111002110910100101010640241221993020000100102003620036200362003620036
10024200351500000611000019862252001020010100101305229049169552003520035186033187401001010020200202003541111002110910100101000640241221993020000100102003620036200362003620036
10024200351500000611000019862252001020010100101305229049169552003520035186033187401001010020200202003541111002110910100101010640241221993020000100102003620036200362003620036
10024200351500000611000019862252001020010100101305229049169552003520035186033187401001010020200202003541111002110910100101003640241221993020000100102003620036200362003620036
10024200351500000611000019862252001020010100101305229049169552003520035186033187401001010020200202003541111002110910100101000640241221993020000100102003620036200362003620036
10024200351500000611000019862252001020010100101305229049169552003520035186033187401001010020200202003541111002110910100101000640241221993020000100102003620036200362003620036
10024200351500000611000019862252001020010100101305229049169552003520035186033187401001010020200202003541111002110910100101023640241331993020000100102003620036200362003620036

Test 4: Latency 4->2

Chain cycles: 1

Code:

  subs x0, x1, x2, lsr #17
  cset x1, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20204300352250000039006110000298992530100301002010719562401492695530035300352739172748620107202243023630035851120201100991002010010100000000001111321016232998330000201003003630036300363003630036
20204300352250000000044110000298992530100301002010719562401492695530035300672739182748620107202243023630035851120201100991002010010100000000001111320116132998330000201003003630036300363003630036
2020430035225000000006110000298992530100301002010719562401492695530035300352739172748520107202243023630035851120201100991002010010100000000001111319316122998330000201003003630036300363003630036
2020430035225000000006110000298992530100301002010719562401492695530035300352739182748520107202243023630035851120201100991002010010100000000001111321016012998230000201003003630036300363003630036
2020430035225000000006110000298992530100301002010719562401492695530035300352739182748620107202243023630035851120201100991002010010100000000001111321316132998230000201003003630036300363003630036
2020430035225000000006110000298992530100301002010719562401492695530035300352739172748520107202243023630035851120201100991002010010100000000001111319216312998230000201003003630036300363003630036
2020430035225000000006110000298992530100301002010719562401492695530035300352739172748620107202243023630035851120201100991002010010100000000301111321316302998230000201003003630036300363003630036
2020430035225000000006110000298992530100301002010719562401492695530035300352739182748620107202243023630035851120201100991002010010100000000001111322016332998230000201003003630036300363003630036
2020430035225000000006110000298992530100301002010719562401492695530035300352739172748620107202243023630035851120201100991002010010100000000001111321316012998230000201003003630036300363003630036
2020430035225000000006110000298992530100301002010719562401492695530035300352739172748620107202243023630035851120201100991002010010100000000001111322316132998230000201003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)091e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)a9cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2002430035225100061100002989125300103001020010195628904926955300353003527391327498200102002030020300358511200211091020010100100001290733442995930000200103003630036300363003630036
2002430035225000061100002989125300103001020010195628904926955300353003527391327498200102002030020300358511200211091020010100100001270333442995930000200103003630036300363017530036
2002430035225000061100002989125300103001020010195628904926955300353003527391327498200102002030020300358511200211091020010100100001270433442995930000200103003630036300363003630036
2002430035225001061100002989125300103001020010195628914926955300353003527391327498200102002030020300358511200211091020010100100001270433442995930000200103003630036300363003630036
2002430035225000061100002989125300103001020010195628904926955300353003527391327498200102002030020300358511200211091020010100100001270433432995930000200103003630036300363003630036
2002430035225000061100002989125300103001020010195628904926955300353003527391327498200102002030020300358511200211091020010100100001270333442995930000200103003630036300363003630036
2002430035225000061100002989125300103001020010195628904926955300353003527391327498200102002030020300358511200211091020010100100001270433442995930000200103003630216300363003630036
2002430035225000061100002989125300103001020010195628914926955300353003527391327498200102002030020300358511200211091020010100100001270433432995930000200103003630036300363003630036
2002430035225000061100002989125300103001020010195628904926955300353003527391327498200102002030020300358511200211091020010100100001270433452995930000200103003630036300363003630036
2002430035225000061100002989125300103001020010195628904926955300353003527391327498200102002030020300358511200211091020010100100001270433542995930000200103003630036300363003630036

Test 5: Latency 4->3

Chain cycles: 1

Code:

  subs x0, x1, x2, lsr #17
  cset x2, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
202043003522506110000298992530100301002010719562401492695530035300352739182748520107202243023630035851120201100991002010010100001111320162998330000201003003630036300363003630036
202043003522506110000298992530100301002010719562400492695530035300352739182748520107202243023630035851120201100991002010010100001111320162998230000201003003630036300363003630036
202043003522506110000298992530100301002010719562400492695530035300352739182748520107202243023630035851120201100991002010010100001111319162998230000201003003630036300363003630036
202043003522506110000298992530100301002010719562400492695530035300352739172748620107202243023630035851120201100991002010010100001111319162998330000201003003630036300363003630036
202043003522506110000298992530100301002010719562400492695530035300352739172748520107202243023630035851120201100991002010010100301111320162998330000201003003630036300363003630036
202043003522506110000298992530100301002010719562400492695530035300352739182748620107202243023630035851120201100991002010010100001111320162998230000201003003630036300363003630036
202043003522506110000298992530100301002010719562400492695530035300352739182748520107202243023630035851120201100991002010010100001111320162998330000201003003630036300363003630036
202043003522506110000298992530100301002010719562400492695530035300352739182748520107202243023630035851120201100991002010010100001111319162998330000201003003630036300363003630036
202043003522506110000298992530100301002010719562400492695530035300352739182748520107202243023630035851120201100991002010010100001111320162998230000201003003630067300363003630036
202043003522506110000298992530100301002010719562400492695530035300352739182748520107202243023630035851120201100991002010010100001111320162998330000201003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)0318191e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2002430035225000611000029891253001030010200101956289049269553003530035273913274982001020020300203003585112002110910200101001000001270333222995930000200103003630036300363003630036
20024300352250006311000029891253001030010200101956289049269553003530035273913274982001020020300203003585112002110910200101001000001270233222995930000200103003630036300363003630036
2002430035225000611000029891253001030010200101957059049269553003530035273913274982001020020300203003585112002110910200101001000001270233222995930000200103003630036300363003630036
2002430035225000611000029891253001030010200101956289049269553003530035273913274982001020020300203003585112002110910200101001000001270233222995930000200103003630036300363003630036
2002430035225000611000029891253001030010200101956289049269553003530035273913274982001020020300203003585112002110910200101001000001270233222995930000200103003630036300363003630036
2002430035225000611000029891253001030010200101956289049269553003530035273913274982001020020300203003585112002110910200101001000001270333222995930000200103003630036300363003630036
2002430035225000611000029891253001030010200101956289049269553003530035273913274982001020020300203003585112002110910200101001000001270233222995930000200103003630036300363003630036
2002430035225000611000029891253001030010200101956289049269553003530035273913274982001020020300203003585112002110910200101001000001270233222995930000200103003630036300363003630036
2002430035225000611000029891253001030010200101956289049269553003530035273913274982001020020300203003585112002110910200101001000001270217222995930000200103003630036300363003630036
20024300352240007261000029891253001030010200101956289049269553003530035273913274982001020020300203003585112002110910200101001000001270233222995930000200103003630036300363003630036

Test 6: throughput

Count: 8

Code:

  subs x0, x8, x9, lsr #17
  subs x1, x8, x9, lsr #17
  subs x2, x8, x9, lsr #17
  subs x3, x8, x9, lsr #17
  subs x4, x8, x9, lsr #17
  subs x5, x8, x9, lsr #17
  subs x6, x8, x9, lsr #17
  subs x7, x8, x9, lsr #17
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80204534504000000933006180000487412516010016010080100344000549503305341053410432982909343360801008020016020053410391180201100991008010010000000000051101241153390160000801005341153411534115341153411
80204534104000000750006180000487412516010016010080100344000549503305341053410432982909343360801008020016020053410391180201100991008010010000000000051101241153390160000801005341153411534115341153411
80204534104000000732006180000487412516010016010080100344000549503305341053410432983024343360801008020016020053410391180201100991008010010000000000051101241153390160000801005341153411534115341153411
8020453410400010057006180000487412516010016010080100344000549503305341053410432983024343360801008020016020053410391180201100991008010010000000000051101241153390160000801005341153411534115341153411
80204534104000000837006180000487412516010016010080100344000549503305341053410432983024343360801008020016020053410391180201100991008010010000000000051101241153390160000801005341153411534115341153411
80204534104000000765006180000487412516010016010080100344000549503305341053410432983024343360801008020016020053410391180201100991008010010000000000051101241153390160000801005341153411534115341153411
802045341040000007800025180000487412516010016010080100344000549503305341053410432983024343360801008020016020053410391180201100991008010010000000000051101241153390160000801005341153411534115341153411
80204534104000000816006180000487412516010016010080100344000549503305341053410432982909343360801008020016020053410391180201100991008010010000201000051101241153390160000801005341153411534115341153411
8020453410400000063006180000487412516010016010080100344000549503305341053410432982909343360801008020016020053410391180201100991008010010000000000051101241153390160000801005341153411534115341153411
802045341040000000006180000487412516010016010080100344000549503305341053410432983024343360801008020016020053410391180201100991008010010000000000051101241153390160000801005341153411534115341153411

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6673

retire uop (01)cycle (02)03191e1f3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)st unit uop (a7)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)d9ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8002453401400000061800004794625160010160010800103438130049503000533805338043290293634335280010800201600205338039118002110910800101000000005020192407553360160000800105338153381533815338153381
800245338040000006180000479462516001016001080010343813004950300053380533804329027493433528001080020160020533803911800211091080010100000000502082409453360160000800105338153381533815338153381
8002453380400000061800004794625160010160010800103438130049503000533805338043290274934335280010800201600205338039118002110910800101000000005020102408653360160000800105338153381533815338153381
800245338040000016180000479462516001016001080010343813004950300053380533804329029363433528001080020160020533803911800211091080010100000000502072408953360160000800105338153381533815338153381
80024533804000000618000047946251600101600108001034381300495030005338053380432902749343352800108002016002053380391180021109108001010000000050201024081153360160000800105338153381533815338153381
8002453380399000095800004794625160010160010800103438130049503000533805338043290274934335280010800201600205338039118002110910800101000000005020524018853360160000800105338153381533815338153381
800245338039900006180000479462516001016001080010343813004950300053380533804329032513433528001080020160020533803911800211091080010100000000502072406453360160000800105338153381533815338153381
80024533804000000618000047946251600101600108001034381300495030005338053380432903251343352800108002016002053380391180021109108001010000000050201024010753360160000800105338153381533815338153381
8002453380399024006180000479462516001016001080010343813004950300053380533804329029363433528001080020160020533803911800211091080010100000000502052408653360160000800105338153381533815338153381
8002453380400000061800004794625160010160010800103438130049503000533805338043290325134335280010800201600205338039118002110910800101000000005020724081053360160000800105338153381533815338153381