Firestorm: LDRSH (unsigned offset, 32-bit) measurements

Code:

  ldrsh w0, [x6, #8]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	399	2	1	1	1	1	0	0	65	1	0	3	383	2	18	18	17	25	1000	1000	1000	15334	1	398	399	221	3	256	1000	1000	1000	399	81	1	1	1001	1000	1000	1	1019	20	42	1057	1	0	0	59	1038	6	1	57	42	19	2	73	3	16	2	2	396	9	9	2	1000	399	400	401	399	400
1004	399	3	1	1	0	1	1	0	65	1	0	3	383	2	18	18	15	25	1000	1000	1000	15357	0	399	399	221	3	257	1000	1000	1000	399	81	1	1	1001	1000	1000	1	1020	20	42	1057	0	0	0	59	1038	6	1	57	42	19	1	73	2	16	2	2	396	9	9	2	1000	399	400	400	399	403
1004	399	3	1	0	1	0	1	0	65	0	0	3	384	2	18	18	15	25	1000	1000	1000	15334	0	398	399	221	3	257	1000	1000	1000	399	81	1	1	1001	1000	1000	1	1020	20	42	1057	1	0	0	59	1037	6	1	57	42	19	0	73	2	16	3	3	396	9	9	2	1000	399	400	400	400	400
1004	399	3	1	1	1	0	0	0	65	0	0	3	384	2	18	18	16	25	1000	1000	1000	15375	0	399	399	221	3	257	1000	1000	1000	399	81	1	1	1001	1000	1000	1	1020	20	42	1057	1	14	1	58	1038	6	1	57	41	19	2	73	2	16	2	2	396	9	9	2	1000	400	399	400	400	399
1004	398	3	1	0	0	1	0	0	65	0	0	3	384	2	18	18	16	25	1000	1000	1000	15375	0	399	398	221	3	257	1000	1000	1000	399	82	1	1	1001	1000	1000	1	1020	19	42	1057	0	0	0	59	1038	6	1	57	42	19	1	73	2	16	2	2	396	9	9	2	1000	400	400	400	400	400
1004	399	3	1	0	0	1	0	0	65	0	0	2	384	2	18	18	15	25	1000	1000	1178	15334	0	399	398	221	3	257	1000	1000	1000	398	81	1	1	1001	1000	1000	0	1020	19	42	1057	1	0	1	59	1039	6	1	57	42	19	2	73	2	16	2	2	395	9	9	2	1000	400	400	400	399	400
1004	399	2	1	1	0	1	0	0	65	0	0	2	384	2	18	18	16	25	1000	1000	1000	15362	1	399	399	224	3	256	1000	1000	1000	399	81	1	1	1001	1000	1000	1	1021	19	42	1057	1	0	0	59	1038	6	1	57	42	19	2	73	2	16	2	2	396	9	9	2	1000	399	400	400	399	400
1004	399	2	1	1	0	1	0	0	65	0	0	3	384	2	18	18	16	25	1000	1000	1000	15318	0	399	399	221	3	256	1000	1000	1000	399	82	1	1	1001	1000	1000	0	1020	19	42	1057	1	2	1	59	1038	6	1	57	42	19	1	73	2	16	2	2	396	9	9	2	1000	400	400	399	400	399
1004	399	3	1	1	1	0	0	0	65	0	0	3	384	2	18	18	16	25	1000	1000	1000	15362	0	399	399	222	3	256	1000	1000	1000	399	81	1	1	1001	1000	1000	1	1021	20	40	1057	0	0	1	59	1038	6	1	57	42	19	0	73	2	16	2	2	396	9	9	2	1000	400	399	400	400	400
1004	399	3	1	1	1	0	0	0	65	0	0	3	384	2	18	18	16	25	1000	1000	1000	15334	1	399	399	222	3	256	1000	1000	1000	399	81	1	1	1001	1000	1000	0	1019	21	42	1058	0	0	1	59	1038	6	1	57	42	18	1	73	2	16	2	2	396	9	9	2	1000	400	400	399	400	399

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh w0, [x6, #8]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70057	525	0	1	0	0	0	0	0	0	0	1	0	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616041	3342398	49	66971	70051	70051	64650	3	64954	40100	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	2610	2	71	1	1	69817	30003	10	10	10	10000	30100	70056	70054	70055	70055	70036
40204	70035	526	0	0	0	1	1	0	0	1	0	0	0	0	70039	69764	59739	25	40104	30103	10000	30100	10000	616175	3342398	49	66971	70035	70051	64631	3	64954	40100	30200	10000	60534	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	0	10000	1	0	0	0	2610	1	71	1	1	69817	30003	13	13	13	10000	30100	70055	70055	70055	70052	70036
40204	70054	525	0	0	0	0	0	0	0	1	0	0	0	0	70020	69764	59713	25	40100	30103	10000	30100	10000	616041	3342398	49	66974	70054	70054	64650	3	64938	40100	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	10000	1	1	0	0	2610	1	71	1	1	69895	30000	13	13	13	10000	30100	70036	70055	70055	70052	70055
40204	70054	525	0	0	0	0	0	0	0	1	0	1	0	0	70020	69764	59713	25	40104	30100	10001	30100	10000	616041	3342398	49	66971	70054	70054	64647	3	64957	40100	30200	10000	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	2610	1	71	1	1	69798	30003	10	10	13	10000	30100	70057	70055	70037	70058	70055
40205	70038	525	0	0	0	0	0	0	0	1	0	0	0	0	70039	69782	59710	25	40104	30100	10001	30100	10000	616041	3342398	49	66971	70051	70054	64647	3	64957	40100	30200	10067	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	1	0	0	10000	1	0	0	0	2610	1	71	1	1	69798	30003	0	10	0	10000	30100	70052	70055	70052	70036	70055
40204	70054	525	0	0	0	0	0	0	0	0	0	0	0	0	70036	69720	59718	25	40100	30100	10000	30100	10000	616175	3341470	49	66974	70054	70054	64631	3	64938	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	0	10000	0	1	0	0	2610	1	71	1	1	69817	30003	13	10	13	10000	30100	70036	70055	70055	70036	70055
40204	70054	524	0	0	0	0	0	0	0	0	0	1	0	0	70039	69782	59713	25	40100	30103	10001	30100	10000	616041	3342254	49	66971	70035	70054	64647	12	64954	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	0	10000	0	0	0	0	2610	1	71	1	1	69817	30003	0	13	0	10000	30100	70036	70055	70036	70055	70055
40204	70054	525	0	0	0	1	1	0	0	1	0	0	0	0	70039	69785	59695	25	40100	30103	10001	30100	10000	616014	3341470	49	66974	70054	70051	64650	3	64957	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	2610	1	71	1	1	69817	30003	13	10	13	10000	30100	70055	70055	70036	70052	70055
40204	70054	525	0	0	0	0	0	0	0	1	0	0	0	0	70039	69785	59713	25	40100	30103	10000	30100	10000	616041	3342398	49	66974	70054	70051	64650	3	64957	40100	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	2610	1	71	1	1	69817	30003	0	10	10	10000	30100	70036	70036	70052	70039	70055
40204	70054	524	0	0	0	0	0	0	0	0	0	0	0	0	70089	69847	59714	25	40104	30112	10001	30100	10000	616014	3342254	49	66974	70035	70035	64650	3	64957	40100	30200	10000	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	10000	1	1	0	0	2610	1	71	1	1	69817	30003	13	10	10	10000	30100	70036	70055	70052	70052	70055

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0060

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70060	525	1	1	1	0	0	0	2	0	0	0	0	70088	69866	59708	25	40018	30016	10002	30010	10000	617068	3342398	0	49	66971	70054	70035	64653	3	64982	40010	30020	10000	60020	10000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	3	10000	1	1	1	1	1	2520	11	71	0	12	12	69804	30003	13	10	13	10000	30010	70088	70116	70058	70088	70042
40024	70060	524	1	0	0	1	0	0	1	0	0	0	1	70045	69783	59725	25	40018	30013	10002	30010	10000	616995	3341769	0	49	66961	70041	70060	64659	3	64985	40010	30020	10000	60020	10000	70060	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	4	1	10002	0	0	1	10000	1	1	1	1	0	2520	7	71	0	13	6	69823	30006	0	13	10	10000	30010	70042	70139	70135	70061	70061
40024	70057	524	1	0	0	0	1	0	1	0	0	0	1	70042	69752	59721	25	40018	30013	10002	30010	10000	617072	3341769	0	49	66980	70041	70060	64678	3	64985	40010	30020	10000	60020	10000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	0	10002	0	0	1	10000	1	1	0	1	1	2520	22	128	0	13	12	69823	30006	13	0	13	10000	30010	70061	70161	70101	70059	70058
40024	70057	525	1	0	1	1	0	0	2	0	0	0	0	70045	69839	59719	25	40014	30016	10001	30010	10000	617072	3341769	1	49	66977	70064	70057	64678	3	64982	40010	30020	10000	60020	10000	70060	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	3	1	10002	0	0	1	10000	1	1	0	1	1	2520	13	71	0	13	13	69820	30006	10	0	0	10000	30010	70058	70145	70114	70062	70058
40024	70060	524	1	0	0	1	0	0	2	0	1	0	0	70045	69792	59726	25	40018	30016	10002	30010	10000	616995	3342686	1	49	66961	70041	70060	64678	3	64982	40010	30020	10000	60346	10055	70060	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	0	10002	0	1	1	10000	1	1	1	1	1	2520	11	71	0	13	11	69804	30006	13	0	10	10000	30010	70058	70128	70086	70060	70042
40024	70060	525	1	0	0	1	0	0	1	0	0	0	0	70045	69742	59723	25	40018	30013	10002	30010	10000	616995	3342686	0	49	66980	70060	70041	64678	3	64982	40010	30020	10000	60020	10000	70060	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10004	2	0	10001	0	1	221	10000	1	1	1	1	1	2520	13	71	0	13	13	69823	30006	0	13	13	10000	30010	70071	70109	70109	70065	70495
40024	70043	524	1	0	1	1	0	0	10	0	1	0	1	70026	69822	59773	25	40018	30016	10002	30010	10000	617045	3342686	1	49	66961	70060	70057	64659	3	64985	40010	30020	10000	60020	10000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	3	1	10003	0	0	1	10000	0	1	1	1	1	2520	12	71	0	5	13	69823	30006	10	0	13	10000	30010	70150	70079	70067	70046	70042
40024	70057	524	1	0	1	0	0	0	7	0	0	0	1	70042	69816	59722	25	40014	30016	10002	30010	10000	616995	3341769	0	49	66961	70057	70041	64659	3	64966	40010	30020	10000	60020	10000	70060	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	3	1	10001	0	0	1	10000	1	1	0	1	2	2520	13	71	0	13	13	69823	30006	13	0	0	10000	30010	70061	70120	70080	70060	70058
40024	70060	524	1	1	0	1	0	0	2	0	0	0	0	70045	69832	59726	25	40014	30016	10002	30010	10000	617072	3342686	0	49	66980	70060	70041	64678	3	64966	40010	30020	10000	60020	10000	70060	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	0	10002	0	1	4	10000	1	1	0	1	0	2520	13	71	0	11	13	69823	30006	13	0	13	10000	30010	70061	70061	70101	70098	70061
40024	70060	525	1	0	0	1	0	0	2	0	1	0	0	70042	69783	59703	25	40018	30016	10002	30010	10000	617072	3341769	0	49	66977	70041	70057	64678	3	64982	40010	30020	10000	60356	10000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	1	10002	1	1	1	10000	1	1	1	1	1	2520	12	71	0	12	13	69804	30006	13	10	10	10000	30010	70152	70076	70061	70069	70061

Test 3: throughput

Count: 8

Code:

  ldrsh w0, [x6, #8]
  ldrsh w0, [x6, #8]
  ldrsh w0, [x6, #8]
  ldrsh w0, [x6, #8]
  ldrsh w0, [x6, #8]
  ldrsh w0, [x6, #8]
  ldrsh w0, [x6, #8]
  ldrsh w0, [x6, #8]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	0e	0f	18	19	1e	1f	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26728	200	0	0	0	0	0	45	88	1	1	26712	2	12	0	24	25	80100	100	80000	100	80000	500	1167231	0	49	23627	26727	26727	16650	3	16809	80100	200	80000	200	80000	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	0	0	80039	6	1	39	43	0	5110	1	16	1	3	26724	10	10	4	80000	100	26728	26728	26708	26728	26728
80204	26707	200	0	0	0	0	0	45	0	1	0	26712	2	12	0	16	25	80100	100	80000	100	80000	500	1167231	0	49	23647	26727	26707	16650	15	16685	80100	200	80000	200	80000	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	0	38	80000	6	1	39	43	0	5110	3	16	3	1	26704	10	10	4	80000	100	26730	26708	26728	26728	26728
80204	26727	200	0	1	0	0	0	45	0	1	1	26712	2	12	12	16	25	80100	100	80000	100	80000	500	1166525	0	49	23647	26727	26727	16650	3	16685	80100	200	80000	200	80000	26727	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80000	0	39	80039	6	1	39	43	0	5110	2	16	1	3	26724	10	10	4	80000	100	26708	26728	26728	26708	26728
80204	26707	200	0	1	0	0	0	44	0	1	0	26692	2	0	12	16	25	80100	100	80000	100	80000	500	1167127	0	49	23647	26727	26727	16650	3	16685	80100	200	80000	200	80000	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80038	0	39	80000	6	0	39	43	0	5110	2	16	1	3	26724	10	10	4	80000	100	26732	26728	26728	26708	26732
80204	26727	200	0	0	0	0	0	45	0	1	1	26712	0	12	0	16	25	80100	100	80000	100	80000	500	1177038	0	49	23627	26727	26707	16630	3	16685	80100	200	80000	200	80000	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	0	39	80039	6	1	39	0	0	5110	4	16	3	2	26724	0	10	4	80000	100	26708	26728	26732	26708	26728
80204	26727	200	0	0	0	0	0	45	0	1	1	26719	2	12	12	0	25	80100	100	80000	100	80000	500	1177038	0	49	23627	26727	26707	16650	3	16685	80100	200	80000	200	80000	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80060	0	39	80039	6	1	39	43	0	5110	3	16	3	2	26724	0	10	5	80000	100	26708	26728	26728	26708	26708
80204	26727	200	0	0	1	0	0	44	0	1	1	26712	2	1	12	16	25	80100	100	80000	100	80000	500	1167231	0	49	23647	26727	26727	16650	3	16685	80100	200	80000	200	80000	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	0	39	80039	6	0	39	0	0	5110	3	16	3	2	26724	0	10	4	80000	100	26728	26728	26732	26708	26729
80204	26727	200	0	0	0	0	0	45	0	0	1	26712	0	0	12	16	25	80100	100	80000	100	80000	500	1167231	0	49	23627	26727	26707	16650	3	16685	80100	200	80000	200	80000	26727	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80000	0	0	80041	6	1	39	43	0	5110	4	16	5	2	26724	10	10	4	80000	100	26728	26728	26728	26708	26728
80204	26727	200	0	0	0	0	0	0	0	0	1	26692	2	12	12	16	25	80100	100	80000	100	80000	500	1177038	1	49	23627	26727	26707	16654	3	16685	80100	200	80000	200	80000	26707	77	1	1	80201	100	99	100	80000	100	80000	1	100	80000	43	80039	0	39	80039	6	0	39	43	0	5110	4	16	4	3	26724	0	10	4	80000	100	26732	26708	26708	26728	26728
80204	26731	200	0	0	0	0	0	45	0	0	1	26712	2	12	12	16	25	80100	100	80000	100	80000	500	1165789	0	49	23647	26727	26727	16630	3	16685	80100	200	80000	200	80000	26707	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	0	0	80039	6	0	0	43	0	5110	5	16	4	2	26724	10	10	4	80000	100	26708	26728	26708	26728	26728

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26735	200	1	0	0	0	0	0	41	0	0	2	26707	2	18	18	22	25	80010	10	80000	10	80000	50	1166993	0	49	23642	26722	26708	16652	3	16707	80010	20	80000	20	80000	26722	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	19	39	80036	0	1	0	39	80039	6	1	35	39	5020	0	10	16	7	4	26719	6	6	2	80000	10	26874	26818	26727	26723	26731
80024	26708	200	0	0	0	0	0	0	45	0	0	1	26693	0	18	12	14	25	80010	10	80000	10	80000	50	1167605	0	49	23642	26722	26722	16652	3	16688	80010	20	80000	20	80000	26722	71	1	1	80021	10	9	10	80000	10	80000	1	10	80000	21	0	80035	0	0	0	35	80039	6	1	35	39	5020	0	4	16	2	4	26719	10	6	4	80000	10	26865	26846	26735	26754	26723
80024	26722	200	0	0	0	0	0	0	41	1	0	1	26707	2	18	18	13	25	80010	10	80000	10	80000	50	1166750	0	49	23642	26727	26728	16652	3	16711	80010	20	80000	20	80000	26727	71	1	1	80021	10	9	10	80000	10	80000	0	10	80019	19	42	80057	0	0	0	39	80169	6	1	0	0	5020	0	2	16	4	4	26725	10	0	2	80000	10	26896	26758	26733	26859	26723
80024	26722	200	0	0	0	0	0	0	41	1	0	1	26693	2	18	15	16	25	80010	10	80000	10	80000	50	1166750	0	49	23642	26708	26708	16667	3	16702	80010	20	80000	20	80000	26722	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	19	0	80035	0	0	0	41	80035	0	1	35	39	5020	0	4	16	2	4	26705	6	6	2	80000	10	26986	26750	26736	26804	26728
80024	26722	200	0	0	0	0	0	0	45	0	0	1	26693	0	18	12	14	25	80010	10	80000	10	80000	50	1172240	0	49	23628	26722	26722	16667	3	16702	80010	20	80000	20	80000	26722	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	21	0	80035	0	6	0	35	80039	6	0	35	39	5020	0	4	16	2	4	26725	6	0	4	80000	10	26723	26802	26819	26742	26742
80024	26732	200	1	0	1	0	0	0	45	0	0	1	26707	2	18	18	18	119	80010	10	80000	10	80000	50	1168327	0	49	23642	26708	26725	16672	3	16707	80010	20	80000	20	80000	26722	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	21	39	80035	0	0	0	35	80035	0	0	35	39	5020	0	4	16	4	4	26719	10	6	4	80000	10	26723	26801	26827	26738	26737
80024	26722	200	0	0	0	0	0	0	41	0	0	1	26707	2	18	18	2	25	80010	10	80000	10	80195	50	1167605	0	49	23628	26722	26722	16667	3	16688	80010	20	80000	20	80000	26722	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	20	39	80035	0	3	0	39	80000	6	0	0	0	5020	0	2	16	2	4	26725	10	6	4	80000	10	26723	26788	26838	26729	26742
80024	26708	200	0	0	0	0	0	0	41	0	0	1	26693	2	18	18	18	25	80010	10	80000	10	80000	50	1168843	0	49	23642	26722	26722	16672	3	16708	80010	20	80000	20	80000	26727	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	21	39	80035	0	2	0	39	80035	0	1	35	39	5020	0	3	16	2	4	26724	6	6	2	80000	10	26723	26784	26828	26730	26728
80024	26722	200	0	0	0	0	0	0	0	1	0	1	26693	0	12	18	15	25	80010	10	80000	10	80000	50	1167605	0	49	23647	26722	26722	16667	3	16702	80010	20	80000	20	80000	26722	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	20	0	80000	0	3	0	35	80035	6	1	35	39	5020	0	4	16	4	2	26705	10	10	2	80000	10	26878	26763	26790	26736	26757
80024	26708	201	0	0	0	0	0	1	41	0	0	0	26715	0	0	18	55	25	80010	10	80000	10	80000	50	1167605	0	49	23647	26722	26708	16667	3	16702	80010	20	80000	20	80000	26728	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	21	39	80035	0	4	0	35	80035	0	1	35	43	5020	0	2	16	2	4	26719	10	6	2	80000	10	26723	26783	26834	26714	26736

LDRSH (unsigned offset, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations