Firestorm: ORN (register, ror, 32-bit) measurements

Code:

  orn w0, w0, w1, ror #17

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	1e	3a	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	2035	15	0	0	3	145	1000	1735	25	2000	2000	1000	32570	1	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	4	0	79	4	67	4	4	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	1	0	3	82	1000	1735	25	2000	2000	1000	32570	1	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	0	0	79	4	67	4	4	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	1	0	3	82	1000	1735	25	2000	2000	1000	32570	1	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	0	0	79	4	67	4	4	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	1	0	3	82	1000	1735	25	2000	2000	1000	32570	1	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	0	0	79	4	67	4	4	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	1	0	3	82	1000	1735	25	2000	2000	1000	32570	0	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	0	0	79	4	67	4	4	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	1	0	3	82	1000	1735	25	2000	2000	1000	32570	1	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	0	0	79	4	67	4	4	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	1	0	3	281	1000	1735	25	2000	2000	1000	32570	1	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	0	0	79	4	67	4	4	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	1	0	3	103	1000	1735	25	2000	2000	1000	32570	1	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	0	0	79	4	67	4	4	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	1	0	3	124	1000	1735	25	2000	2000	1000	32570	0	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	0	0	79	4	67	4	4	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	1	0	3	82	1000	1735	25	2000	2000	1000	32570	1	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	1	9	79	4	67	4	4	1781	2000	1000	2036	2036	2036	2036	2036

Test 2: Latency 1->2

Code:

  orn w0, w0, w1, ror #17

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3a	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? int retires (ef)	f5	f6	f7	f8	fd
10204	20035	155	1	1	1	0	0	61	10000	19803	25	20100	20100	10100	185316	0	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	10	0	0	710	1	59	1	1	19791	20000	0	0	10100	20036	20036	20036	20036	20036
10204	20035	155	0	1	1	0	0	61	10000	19803	25	20125	20100	10125	185316	0	49	16955	20035	20035	18429	3	18700	10125	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	1	0	0	710	5	59	1	1	19791	20000	0	0	10100	20036	20036	20036	20036	20036
10204	20035	155	0	0	0	0	2	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	5	0	0	710	1	59	1	1	19791	20000	0	0	10100	20036	20036	20036	20036	20036
10204	20035	155	0	0	0	0	0	61	10000	19797	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	5	3	0	710	5	59	2	5	19792	20025	0	0	10100	20036	20036	20036	20036	20036
10204	20035	155	0	0	0	0	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18435	3	18700	10125	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	1	63	0	710	1	59	1	1	19791	20000	0	0	10100	20036	20036	20036	20036	20036
10204	20035	156	0	0	0	0	2	68	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10125	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	1	3	0	716	5	59	1	1	19792	20000	0	0	10100	20036	20036	20036	20036	20036
10204	20035	155	0	0	0	0	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	3	0	710	1	59	1	1	19791	20000	0	0	10100	20036	20036	20036	20036	20036
10204	20035	155	0	0	0	0	0	89	10000	19803	25	20100	20100	10100	185316	0	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	1	59	5	2	19792	20000	0	0	10100	20036	20036	20036	20036	20036
10204	20035	156	0	0	0	0	0	68	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	6	3	0	710	1	59	1	1	19791	20000	0	0	10100	20036	20036	20036	20036	20036
10204	20035	156	0	0	0	0	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	44	1	1	10201	100	99	100	10100	100	0	48	0	710	1	59	1	1	19791	20000	0	0	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20035	155	0	126	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	3	0	661	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	155	0	151	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	155	0	61	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	155	0	124	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	155	0	191	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	155	0	126	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	155	0	124	10000	19743	25	20010	20010	10010	185310	1	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	156	0	149	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	155	0	603	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	155	0	61	10000	19743	25	20010	20010	10010	185310	1	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036

Test 3: Latency 1->3

Code:

  orn w0, w1, w0, ror #17

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20035	155	27	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	0	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	156	9	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	0	20035	20035	18429	3	18700	10276	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	3	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	156	24	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	0	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	156	117	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	0	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	0	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	0	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	15	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	0	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	156	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	0	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	18	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	0	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	15	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	0	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20035	155	757	10000	19743	25	20010	20010	10010	185310	0	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	640	0	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	155	944	10000	19743	25	20010	20010	10010	185310	0	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	1	3	640	0	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	155	844	10000	19743	25	20010	20010	10010	185310	0	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	3	0	640	0	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	156	61	10000	19743	25	20010	20010	10010	185310	0	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	6	0	640	0	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	155	82	10000	19743	25	20010	20010	10010	185310	0	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	4	3	640	0	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	155	668	10000	19743	25	20010	20010	10010	185310	0	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	640	0	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	155	976	10000	19743	25	20010	20010	10010	185310	0	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	1	3	640	0	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	155	61	10000	19743	25	20010	20010	10010	185310	0	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	640	0	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	155	61	10000	19743	25	20010	20010	10010	185310	0	0	49	16955	20035	20035	18454	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	640	0	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	155	61	10000	19743	25	20010	20010	10010	185310	0	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	640	0	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036

Test 4: throughput

Count: 8

Code:

  orn w0, w8, w9, ror #17
  orn w1, w8, w9, ror #17
  orn w2, w8, w9, ror #17
  orn w3, w8, w9, ror #17
  orn w4, w8, w9, ror #17
  orn w5, w8, w9, ror #17
  orn w6, w8, w9, ror #17
  orn w7, w8, w9, ror #17

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26768	207	0	12	61	80000	26094	25	160100	160100	80100	164318	0	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	3	22	2	2	26717	160000	80100	26726	26726	26726	26726	26726
80204	26725	207	0	15	89	80000	26094	25	160100	160100	80100	164318	0	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	22	2	2	26717	160000	80100	26726	26726	26726	26726	26726
80204	26725	207	0	33	61	80000	26094	25	160100	160100	80100	164318	0	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	22	2	2	26717	160000	80100	26726	26726	26726	26726	26726
80204	26725	207	0	12	61	80000	26094	25	160100	160100	80100	164318	1	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	22	2	2	26765	160000	80100	26726	26726	26726	26726	26726
80204	26725	207	1	0	61	80000	26094	25	160100	160100	80100	164318	0	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	22	3	2	26717	160000	80100	26726	26726	26726	26726	26726
80204	26725	207	0	0	89	80000	26094	25	160100	160100	80100	164318	0	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	2	0	0	5110	2	22	2	2	26717	160000	80100	26726	26726	26726	26726	26726
80204	26725	207	0	48	61	80000	26094	25	160100	160100	80100	164318	0	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	22	2	2	26717	160000	80100	26726	26726	26726	26726	26726
80204	26725	208	0	0	61	80000	26094	25	160100	160100	80100	164318	0	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	0	3	0	5110	2	22	2	2	26717	160000	80100	26726	26726	26726	26726	26726
80204	26725	208	0	0	61	80000	26094	25	160100	160100	80100	164318	0	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	22	2	2	26717	160000	80100	26726	26726	26726	26726	26726
80204	26725	207	0	24	251	80000	26094	25	160100	160100	80100	164318	0	49	23645	26725	26725	16615	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5112	2	22	2	2	26717	160000	80100	26726	26726	26726	26726	26726

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? int retires (ef)	f5	f6	f7	f8	fd
80024	26717	207	0	0	0	0	0	0	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	3	0	0	5020	4	22	2	4	26704	160000	20	80010	26712	26712	26712	26712	26712
80024	26711	207	0	0	0	0	0	0	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	18	0	0	5020	2	22	4	2	26704	160000	0	80010	26712	26712	26712	26712	26712
80024	26711	207	0	0	0	0	0	0	0	0	61	80000	21280	25	160010	160010	80010	163142	1	49	23631	26711	26711	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	156	0	0	5020	4	22	4	2	26704	160000	0	80010	26712	26712	26712	26712	26712
80024	26711	207	0	0	0	0	0	0	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	21	0	0	5020	4	22	4	2	26704	160000	0	80010	26712	26712	26712	26712	26712
80024	26711	207	0	0	0	0	0	0	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	12	0	0	5020	4	22	4	2	26704	160000	0	80010	26712	26712	26712	26712	26712
80024	26711	207	0	0	0	0	0	0	0	0	82	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	160020	26768	39	1	1	80021	10	9	10	80010	10	0	0	0	6	0	0	5020	2	22	2	4	26704	160000	0	80010	26712	26712	26712	26712	26712
80024	26711	207	0	0	0	0	0	0	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	141	0	0	5020	4	22	4	2	26704	160000	0	80010	26712	26712	26712	26712	26712
80024	26711	207	0	0	0	0	0	0	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	29	0	0	0	0	5020	4	22	4	2	26704	160000	0	80010	26712	26712	26712	26712	26741
80024	26711	207	0	0	0	0	0	0	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	4	0	156	0	0	5020	4	22	4	2	26704	160000	0	80010	26712	26712	26712	26712	26712
80024	26711	207	0	0	0	0	0	0	0	0	89	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	9	0	0	5020	2	22	4	2	26704	160000	0	80010	26712	26712	26712	26712	26712

ORN (register, ror, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations