Firestorm: PRFM (register, PLIL1KEEP) measurements

Code:

  prfm plil1keep, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	1618	12	29	15	30	2388	1590	928	25	1000	1000	1000	69366	1589	1618	1304	3	1473	1000	1000	1000	1570	1583	1	1	1001	252	2207	2230	3237	0	0	2400	2214	1000	73	1	16	1	1	1504	1000	1603	1589	1615	1593	1619
1004	1627	12	30	14	30	2379	1607	876	25	1000	1000	1000	69376	1598	1616	1301	3	1472	1000	1000	1000	1599	1597	1	1	1001	205	2221	2233	3208	0	0	2407	2231	1000	73	1	16	1	1	1497	1000	1593	1618	1619	1598	1603
1004	1600	12	29	14	30	2404	1556	881	25	1000	1000	1000	69954	1609	1591	1308	3	1459	1000	1000	1000	1593	1586	1	1	1001	261	2231	2232	3232	0	0	2376	2215	1000	73	1	16	1	1	1539	1000	1594	1599	1608	1592	1613
1004	1604	12	28	15	30	2394	1608	914	25	1000	1000	1000	69386	1612	1611	1291	3	1450	1000	1000	1000	1587	1576	1	1	1001	212	2242	2221	3249	0	0	2400	2228	1000	73	1	16	1	1	1495	1000	1619	1603	1617	1625	1635
1004	1564	12	30	15	30	2365	1599	926	25	1000	1000	1000	70363	1597	1636	1303	3	1446	1000	1000	1000	1578	1587	1	1	1001	248	2214	2225	3218	0	0	2388	2216	1000	73	1	16	1	1	1507	1000	1624	1620	1614	1623	1620
1004	1626	12	30	15	30	2401	1592	863	25	1000	1000	1000	69334	1578	1605	1309	3	1479	1000	1000	1000	1589	1576	1	1	1001	242	2236	2231	3227	0	0	2375	2241	1000	73	1	16	1	1	1533	1000	1624	1563	1615	1633	1591
1004	1587	13	30	15	30	2380	1590	920	25	1000	1000	1000	70812	1576	1604	1309	3	1486	1000	1000	1000	1609	1588	1	1	1001	231	2228	2221	3215	0	0	2386	2250	1000	73	1	16	1	1	1494	1000	1602	1592	1592	1603	1589
1004	1626	12	30	15	30	2395	1623	884	25	1000	1000	1000	69835	1613	1598	1299	3	1447	1000	1000	1000	1583	1588	1	1	1001	239	2211	2215	3221	0	0	2371	2231	1000	73	1	16	1	1	1500	1000	1579	1568	1615	1613	1588
1004	1620	12	30	15	30	2384	1601	892	25	1000	1000	1000	69713	1616	1570	1287	3	1465	1000	1000	1000	1605	1592	1	1	1001	230	2214	2251	3217	1	2	2405	2188	1000	73	1	16	1	1	1514	1000	1617	1614	1601	1610	1596
1004	1619	12	30	15	31	2360	1579	888	25	1000	1000	1000	69851	1584	1597	1300	3	1450	1000	1000	1000	1595	1595	1	1	1001	233	2213	2205	3204	0	0	2381	2236	1000	73	1	16	1	1	1513	1000	1612	1602	1599	1619	1572

Test 2: throughput

Code:

  prfm plil1keep, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5754

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	67	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	15678	118	348	188	344	24360	1	15635	9832	25	20220	10211	10000	10100	10000	130793	735888	29	49	12692	0	15660	15665	12936	3	13220	20100	10200	10000	10200	10000	15697	155	1	1	20201	100	99	2353	100	10100	100	22779	22626	32698	0	24369	22874	10000	1313	3	16	3	3	15591	10108	10000	10100	15620	15718	15696	15697	15790
20204	15699	118	341	183	341	24525	1	15712	9606	25	20217	10208	10000	10100	10000	131915	737085	38	49	12603	0	15761	15709	13108	3	13164	20100	10200	10000	10200	10000	15661	154	1	1	20201	100	99	2425	100	10100	100	22840	22812	32751	0	24400	22783	10000	1312	2	16	3	2	15619	10111	10000	10100	15800	15735	15772	15654	15624
20204	15739	118	343	185	345	24505	1	15759	9731	25	20238	10226	10000	10100	10000	133914	731861	37	49	12593	0	15794	15702	12937	3	13280	20100	10200	10000	10200	10000	15724	156	1	1	20201	100	99	2354	100	10100	100	22856	22757	32733	0	24441	22703	10000	1312	3	16	2	3	15587	10150	10000	10100	15843	15690	15745	15682	15732
20204	15741	118	344	189	345	24404	1	15696	9844	25	20239	10184	10000	10100	10000	131447	736667	40	49	12659	0	15694	15675	12925	3	13148	20100	10200	10000	10200	10000	15661	164	1	1	20201	100	99	2435	100	10100	100	22655	22775	32648	1	24456	22765	10000	1312	3	16	3	3	15609	10144	10000	10100	15652	15848	15738	15591	15695
20204	15704	118	344	182	345	24477	1	15702	9947	25	20196	10205	10000	10100	10000	133464	732899	41	49	12506	0	15682	15781	12903	3	13044	20100	10200	10000	10200	10000	15643	155	1	1	20201	100	99	2522	100	10100	100	22781	22651	32754	0	24463	22666	10000	1312	2	17	3	2	15574	10105	10000	10100	15801	15773	15707	15649	15737
20204	15701	118	344	178	336	24607	1	15769	9744	25	20205	10235	10000	10100	10000	131505	744104	38	49	12604	0	15680	15900	13002	3	13396	20100	10200	10000	10200	10000	15698	154	1	1	20201	100	99	2437	100	10100	100	22804	22670	32663	0	24622	22672	10000	1312	3	17	2	3	15698	10096	10000	10100	15763	15726	15728	15838	15700
20204	15755	118	338	184	345	24427	1	15716	9651	25	20197	10199	10000	10100	10000	132544	738277	24	49	12650	0	15722	15763	12967	3	13161	20100	10200	10000	10200	10000	15857	156	1	1	20201	100	99	2406	100	10100	100	22623	22581	32700	1	24587	22810	10000	1312	2	16	2	3	15530	10099	10000	10100	15748	15794	15672	15809	15752
20204	15814	118	344	181	339	24499	1	15652	9888	25	20208	10196	10000	10100	10000	132414	731080	42	49	12667	0	15656	15793	13151	3	13236	20100	10200	10000	10200	10000	15704	156	1	1	20201	100	99	2473	100	10100	100	22730	22854	32842	18	24256	22750	10000	1312	3	16	2	3	15571	10102	10000	10100	15839	15716	15699	15679	15780
20204	15725	117	342	185	337	24427	1	15699	9726	25	20226	10199	10000	10100	10000	132470	740044	37	49	12647	0	15717	15752	13032	3	13167	20100	10200	10000	10200	10000	15779	156	1	1	20201	100	99	2432	100	10100	100	22670	22907	32636	0	24525	22714	10000	1312	3	16	3	3	15620	10093	10000	10100	15636	15646	15728	15673	15913
20204	15758	117	343	187	343	24435	1	15792	9591	25	20223	10226	10000	10100	10000	133412	737014	31	49	12663	0	15801	15766	13116	3	13161	20100	10200	10000	10200	10000	15743	154	1	1	20201	100	99	2555	100	10100	100	22784	22696	32736	0	24480	22812	10000	1312	3	17	3	3	15661	10108	10000	10100	15783	15820	15835	15820	15772

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5760

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	15851	117	340	178	339	24440	15830	9734	25	20148	10151	10000	10010	10000	133952	734857	0	42	49	12702	15681	15712	13056	3	13221	20010	10020	10000	10020	10000	15656	143	1	1	20021	10	9	2587	10	10010	10	22722	22657	32730	0	24490	22668	10000	1270	8	16	5	5	15628	10138	10000	10010	15840	15749	15774	15736	15788
20024	15836	118	333	178	343	24229	15794	9792	25	20163	10172	10000	10010	10000	132228	736189	0	50	49	12514	15845	15658	13001	3	13354	20010	10020	10000	10020	10000	15758	142	1	1	20021	10	9	2539	10	10010	10	22675	22802	32591	0	24355	22833	10000	1270	5	16	5	5	15726	10126	10000	10010	15751	15833	15764	15722	15743
20024	15700	118	344	180	339	24235	15813	9695	25	20118	10178	10000	10010	10000	132748	737883	0	34	49	12632	15778	15737	13138	3	13242	20010	10020	10000	10020	10000	15683	146	1	1	20021	10	9	2481	10	10010	10	22711	22719	32651	0	24335	22603	10000	1270	6	16	5	5	15581	10132	10000	10010	15778	15641	15836	15721	15744
20024	15801	118	342	178	345	24384	15675	9926	25	20154	10133	10000	10010	10000	133321	736702	0	45	49	12559	15813	15729	13043	3	13214	20010	10020	10000	10020	10000	15731	158	1	1	20021	10	9	2577	10	10010	10	22680	22621	32527	0	24416	22874	10000	1272	5	16	5	5	15736	10126	10000	10010	15739	15783	15732	15870	15804
20024	15777	118	340	182	334	24478	15689	9780	25	20160	10163	10000	10010	10000	133534	739192	0	51	49	12682	15807	15704	12972	3	13319	20010	10020	10000	10020	10000	15820	156	1	1	20021	10	9	2313	10	10010	10	22747	22762	32692	0	24475	22605	10000	1270	5	16	5	5	15509	10087	10000	10010	15723	15726	15687	15825	15771
20024	15814	118	334	183	339	24407	15755	9746	25	20124	10115	10000	10010	10000	133430	733457	0	47	49	12622	15727	15779	13089	3	13263	20010	10020	10000	10020	10000	15771	155	1	1	20021	10	9	2421	10	10010	10	22645	22827	32779	2	24390	22592	10000	1271	5	16	5	5	15651	10090	10000	10010	15825	15912	15933	15670	15739
20024	15887	118	339	181	334	24418	15683	9811	25	20130	10127	10000	10010	10000	133366	736570	0	39	49	12743	15747	15764	13094	3	13209	20010	10020	10000	10020	10000	15707	143	1	1	20021	10	9	2646	10	10010	10	22741	22798	32707	0	24636	22581	10000	1271	5	16	5	5	15674	10150	10000	10010	15783	15869	15889	15697	15869
20024	15710	118	343	181	342	24383	15863	9819	25	20181	10115	10000	10010	10000	133094	738606	0	43	49	12714	16002	15741	13083	3	13168	20010	10020	10000	10020	10000	15724	157	1	1	20021	10	9	2413	10	10010	10	22761	22618	32703	0	24433	22622	10000	1270	5	16	5	4	15735	10141	10000	10010	15841	15923	15726	15692	15767
20024	15709	118	335	178	340	24485	15782	9698	25	20133	10130	10000	10010	10000	134935	741354	0	51	49	12632	15776	15852	13042	3	13185	20010	10020	10000	10020	10000	15720	158	1	1	20021	10	9	2346	10	10010	10	22614	22734	32771	0	24519	22673	10000	1273	6	16	4	7	15574	10123	10000	10010	15792	15736	15778	15746	15825
20024	15699	118	342	176	336	24440	15956	9791	25	20136	10142	10000	10010	10000	134640	742312	0	47	49	12753	15761	15691	13103	3	13320	20010	10020	10000	10020	10000	15702	149	1	1	20021	10	9	2506	10	10010	10	22749	22724	32682	0	24487	22604	10000	1270	5	16	5	5	15636	10132	10000	10010	15884	15917	15701	15813	15658

Test 3: throughput

Code:

  prfm plil1keep, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5415

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	bb	l1d tlb miss nonspec (c1)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10204	15397	115	331	171	328	3	0	24451	0	15348	9437	25	10100	100	10000	100	10000	500	718798	0	49	12285	0	15407	15416	14000	7	14073	10106	200	10016	200	10008	15421	12185	1	1	10201	100	99	2569	100	100	100	22844	22839	32820	0	1	0	24530	22738	10000	1	1	1	719	0	16	0	0	15310	0	0	10000	100	15427	15390	15513	15419	15437
10204	15453	115	329	170	332	0	0	24674	0	15382	9467	25	10100	100	10000	100	10006	500	720435	0	49	12385	0	15415	15462	14016	6	14067	10103	200	10016	200	10016	15383	12197	1	1	10201	100	99	2553	100	100	100	22899	22775	33318	0	1	0	24577	22747	10000	1	1	1	718	0	16	0	0	15352	0	0	10000	100	15521	15389	15451	15333	15415
10204	15445	115	325	172	333	0	0	24558	0	15439	9473	25	10100	100	10000	100	10008	500	719731	0	49	12334	0	15465	15394	13991	6	14123	10100	200	10008	200	10008	15390	12210	1	1	10201	100	99	2594	100	100	100	22826	22915	32784	0	1	0	24571	22689	10000	1	1	1	718	0	16	0	0	15263	0	0	10000	100	15462	15477	15389	15379	15346
10204	15425	114	329	170	332	0	0	25108	0	15311	9469	25	10100	100	10000	100	10003	500	721131	0	49	12251	0	15385	15370	13911	7	14050	10100	200	10008	200	10016	15433	12184	1	1	10201	100	99	2559	100	100	100	22767	22773	32720	0	0	0	24629	22717	10000	1	1	1	717	0	16	0	0	15285	0	0	10000	100	15601	15395	15351	15370	15438
10204	15415	115	328	167	331	0	0	24485	0	15354	9381	25	10100	100	10000	100	10000	500	722533	0	49	12363	0	15383	15364	13996	6	14152	10100	200	10024	200	10008	15350	12143	1	1	10201	100	99	2514	100	100	100	22799	22764	32676	0	0	0	24468	22776	10000	1	1	1	717	0	16	0	0	15370	0	0	10000	100	15543	15453	15344	15336	15407
10204	15465	115	326	172	332	0	0	24538	0	15323	9478	25	10100	100	10000	100	10006	500	722321	0	49	12297	0	15329	15381	13972	7	14078	10100	200	10016	200	10008	15372	12130	1	1	10201	100	99	2570	100	100	100	22723	22836	32765	0	0	0	24593	22752	10000	1	1	1	717	0	16	0	0	15350	0	1	10000	100	15398	15412	15366	15420	15446
10204	15498	115	328	170	331	0	0	24540	0	15458	9434	25	10100	100	10000	100	10000	500	724678	0	49	12390	0	15356	15337	14004	6	14168	10100	200	10008	200	10008	15385	12187	1	1	10201	100	99	2522	100	100	100	22790	22708	32700	2	0	0	24589	22819	10000	1	1	1	717	0	16	0	0	15311	0	0	10000	100	15483	15373	15426	15382	15423
10204	15400	115	327	171	332	0	0	24677	0	15429	9476	25	10100	100	10000	100	10000	500	718887	0	49	12384	0	15421	15338	13981	7	14120	10100	200	10016	200	10008	15382	12239	1	1	10201	100	99	2577	100	100	100	22767	22813	32774	0	0	0	24559	22706	10000	1	1	1	718	0	16	0	0	15296	0	0	10000	100	15345	15492	15446	15391	15384
10204	15415	116	327	171	327	0	0	24596	0	15375	9474	25	10100	100	10000	100	10000	500	721968	0	49	12414	0	15398	15392	13994	7	14142	10100	200	10016	200	10008	15398	12210	1	1	10201	100	99	2519	100	100	100	22805	22833	32696	0	0	0	24606	22662	10000	1	1	1	717	0	16	0	0	15329	0	0	10000	100	15448	15432	15429	15427	15319
10204	15384	116	330	177	331	0	0	24502	0	15303	9464	25	10100	100	10000	100	10002	500	715842	0	49	12343	0	15446	15415	13885	7	14201	10100	200	10008	200	10024	15292	12219	1	1	10201	100	99	2528	100	100	100	22776	22732	33387	0	1	0	24546	22788	10000	1	1	1	717	0	16	0	0	15305	0	0	10000	100	15400	15415	15343	15459	15384

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5574

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10024	15555	117	290	149	295	23951	15530	9719	25	10010	10	10000	10	10000	50	730600	49	12521	15525	15547	14171	3	14271	10010	20	10000	20	10000	15505	15454	1	1	10021	10	9	2670	10	10	10	22379	22256	32305	0	23971	22273	10000	0	640	2	16	2	2	15375	10000	10	15544	15595	15618	15567	15522
10024	15578	117	295	148	294	24039	15597	9664	25	10010	10	10000	10	10000	50	728963	49	12468	15519	15562	14186	3	14398	10010	20	10000	20	10000	15619	15502	1	1	10021	10	9	2610	10	10	10	22275	22305	32285	0	23989	22271	10000	0	640	2	16	2	2	15448	10000	10	15699	15632	15592	15555	15600
10024	15583	117	298	147	295	24037	15576	9630	25	10010	10	10000	10	10000	50	731659	49	12463	15557	15476	14135	3	14310	10010	20	10000	20	10000	15522	15544	1	1	10021	10	9	2704	10	10	10	22278	22288	32265	0	24086	22245	10000	0	640	2	16	2	2	15375	10000	10	15597	15586	15561	15588	15597
10024	15496	117	296	148	294	24013	15625	9625	25	10010	10	10000	10	10000	50	730184	49	12461	15585	15583	14096	3	14226	10010	20	10000	20	10121	15503	15517	1	1	10021	10	9	2750	10	10	10	22378	22281	32241	0	24030	22363	10000	0	640	2	16	2	2	15430	10000	10	15559	15591	15553	15547	15542
10024	15579	116	296	147	293	23986	15624	9711	25	10010	10	10000	10	10000	50	730221	49	12530	15587	15593	14142	3	14320	10010	20	10000	20	10000	15406	15488	1	1	10021	10	9	2644	10	10	10	22294	22322	32251	0	23961	22270	10000	0	640	2	16	2	2	15435	10000	10	15578	15513	15553	15515	15612
10024	15574	117	293	148	299	23947	15519	9653	25	10010	10	10000	10	10000	50	730560	49	12501	15605	15612	14071	3	14283	10010	20	10000	20	10000	15534	15604	1	1	10021	10	9	2705	10	10	10	22351	22324	32283	0	24000	22302	10000	0	640	2	16	2	2	15476	10000	10	15547	15587	15551	15572	15609
10024	15530	117	299	146	298	24005	15518	9581	25	10010	10	10000	10	10000	50	729952	49	12484	15517	15602	14126	3	14317	10010	20	10000	20	10000	15512	15487	1	1	10021	10	9	2651	10	10	10	22317	22257	32251	0	24014	22273	10000	0	640	2	16	2	2	15458	10000	10	15570	15602	15517	15518	15616
10024	15566	117	296	147	298	23998	15567	9626	36	10010	10	10000	10	10000	50	728714	49	12493	15603	15599	14145	3	14326	10010	20	10000	20	10000	15626	15484	1	1	10021	10	9	2710	10	10	10	22495	22295	32347	31	24025	22366	10000	0	640	2	16	2	2	15408	10000	10	15591	15544	15559	15554	15504
10024	15635	117	292	148	295	24005	15676	9585	25	10010	10	10000	10	10000	50	724876	49	12443	15527	15462	14057	3	14374	10010	20	10000	20	10000	15579	15427	1	1	10021	10	9	2659	10	10	10	22362	22334	32320	0	24017	22275	10000	0	640	2	16	2	2	15426	10000	10	15729	15589	15565	15538	15516
10024	15476	116	295	147	294	24003	15524	9533	25	10010	10	10000	10	10000	50	725296	49	12372	15553	15500	14120	3	14363	10010	20	10000	20	10000	15563	15474	1	1	10021	10	9	2655	10	10	10	22366	22252	32237	0	23994	22345	10000	0	640	2	16	2	2	15399	10000	10	15670	15518	15566	15557	15541

PRFM (register, PLIL1KEEP)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations