Firestorm: LDRSB (32-bit) measurements

Code:

  ldrsb w0, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	403	3	1	1	1	1	1	67	1	2	388	3	7	7	19	25	1000	1000	1000	15509	0	403	403	204	3	262	1000	1000	1000	403	86	1	1	1001	0	1000	1000	1	1020	20	43	1059	0	0	1	60	1040	6	1	61	43	19	1	73	3	16	3	3	400	13	13	5	1000	404	404	404	404	403
1004	403	3	1	1	1	0	0	69	0	2	388	3	7	7	19	25	1000	1000	1000	15531	1	403	403	225	3	261	1000	1000	1000	413	85	1	1	1001	0	1000	1000	1	1020	21	43	1059	0	0	0	59	1040	6	1	59	43	19	1	73	3	16	3	3	400	13	13	5	1000	404	407	404	403	404
1004	403	3	1	1	1	0	0	66	0	3	388	3	7	7	20	25	1000	1000	1000	15555	1	402	403	225	3	261	1000	1000	1000	403	85	1	1	1001	0	1000	1000	0	1020	20	43	1059	0	0	0	61	1039	6	1	59	43	19	0	73	3	16	3	3	400	13	13	5	1000	404	404	404	403	404
1004	403	3	1	0	0	0	0	67	0	3	388	3	7	7	19	25	1000	1000	1000	15526	1	402	403	225	3	261	1000	1000	1000	404	85	1	1	1001	0	1000	1000	0	1019	19	43	1058	1	0	0	61	1040	6	1	59	45	19	0	73	3	16	3	3	400	13	13	5	1000	404	404	403	403	404
1004	403	3	1	1	1	1	1	67	0	3	388	3	7	7	21	25	1000	1000	1000	15526	1	402	403	225	3	261	1000	1000	1000	403	85	1	1	1001	0	1000	1000	1	1019	19	43	1058	1	0	1	59	1040	6	1	59	43	19	1	73	3	16	3	3	400	13	13	5	1000	404	404	404	403	404
1004	403	3	1	0	0	0	0	66	0	3	388	3	7	7	18	25	1000	1000	1000	15555	1	402	403	225	3	261	1000	1000	1000	403	85	1	1	1001	0	1000	1000	0	1021	20	43	1059	0	0	0	61	1039	6	1	59	43	19	1	73	3	16	3	3	399	13	13	5	1000	403	404	404	404	404
1004	402	3	1	1	1	0	0	66	1	2	387	2	7	7	19	25	1000	1000	1000	15526	1	403	403	225	3	261	1000	1000	1000	403	86	1	1	1001	0	1000	1000	0	1019	19	43	1059	1	0	2	60	1040	6	1	59	43	19	1	73	3	16	3	3	400	13	13	5	1000	404	403	403	404	404
1004	403	3	1	1	0	0	0	69	0	3	388	3	7	7	20	25	1000	1000	1000	15548	1	403	403	225	3	261	1000	1000	1000	403	85	1	1	1001	0	1000	1000	0	1019	19	43	1058	0	0	2	61	1040	6	1	58	43	19	0	73	3	16	3	3	400	13	13	5	1000	404	404	404	403	403
1004	403	3	1	0	1	0	0	67	0	3	387	3	7	7	20	25	1000	1000	1000	15480	1	403	402	225	3	261	1000	1000	1000	403	85	1	1	1001	0	1000	1000	0	1020	21	43	1059	0	0	2	60	1040	6	1	59	43	19	2	73	3	16	3	3	400	13	13	5	1000	404	404	404	404	404
1004	403	3	1	0	1	0	0	67	0	3	388	2	7	7	20	25	1000	1000	1000	15480	1	403	403	225	3	261	1000	1000	1000	403	85	1	1	1001	0	1000	1000	1	1020	19	43	1060	1	0	1	61	1040	6	1	58	43	19	1	73	3	16	3	3	400	13	13	5	1000	404	404	404	404	403

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb w0, [x6]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0121

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70060	525	1	1	1	1	2	0	0	0	2	0	0	0	0	70026	69787	59701	25	40104	30106	10002	30100	10000	616059	3342638	1	49	66976	70056	70056	64637	3	64944	40100	30399	10000	60200	10000	70041	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10002	2	0	10002	0	0	1	40	10000	1	1	0	1	1	0	2610	4	71	1	1	69816	30006	6	0	9	10000	30100	70095	70042	70057	70042	70042
40204	70124	525	1	0	1	1	0	0	0	0	2	0	1	0	0	70038	69702	59715	25	40108	30106	10001	30100	10000	616041	3342830	1	49	66976	70056	70053	64637	3	64956	40100	30200	10000	60200	10000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10006	0	0	1	31	10000	1	1	0	1	0	0	2610	1	71	1	1	69804	30006	0	6	9	10000	30100	70057	70057	70042	70057	70057
40204	70141	524	1	1	1	0	0	0	0	0	1	0	0	1	0	70026	69702	59715	25	40108	30103	10002	30100	10000	616086	3342590	1	49	66961	70053	70056	64637	3	64959	40100	30200	10000	60200	10000	70053	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	1	10002	0	0	3	133	10000	1	1	1	1	1	0	2610	1	71	1	1	69819	30006	0	9	9	10000	30100	70057	70042	70057	70042	70057
40204	70151	525	1	1	0	1	0	0	0	0	1	0	0	1	1	70041	69702	59701	25	40108	30106	10001	30100	10000	616077	3342542	1	49	66973	70056	70056	64652	3	64944	40100	30200	10000	60200	10000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	1	10001	0	1	1	4	10000	0	1	1	1	0	0	2610	1	71	1	1	69804	30003	9	6	0	10000	30100	70057	70057	70057	70042	70042
40204	70146	525	1	1	0	1	1	0	0	0	2	0	0	1	0	70041	69787	59715	25	40104	30106	10002	30100	10000	616050	3343022	1	49	66976	70056	70056	64637	3	64959	40100	30200	10000	60200	10000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	1	10003	0	0	1	130	10000	0	1	1	1	0	0	2610	1	71	1	1	69819	30006	9	0	0	10000	30100	70042	70054	70054	70042	70057
40204	70126	525	1	0	1	0	1	0	0	0	1	0	0	0	0	70041	69702	59715	25	40108	30106	10002	30100	10000	616041	3342494	1	49	66976	70056	70041	64637	3	64956	40100	30200	10000	60200	10000	70056	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10001	1	1	10003	0	0	2	172	10000	1	1	0	1	1	1	2610	1	71	1	1	69819	30006	0	0	9	10000	30100	70042	70042	70057	70057	70050
40204	70142	525	1	1	0	0	0	0	0	0	2	0	0	0	0	70041	69787	59718	25	40108	30103	10002	30100	10000	616068	3342590	0	49	66973	70053	70053	64649	3	64959	40100	30200	10000	60200	10000	70053	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10001	1	1	10001	0	0	1	250	10000	1	1	1	1	0	0	2610	1	71	1	1	69816	30006	0	9	0	10000	30100	70042	70042	70057	70057	70057
40204	70094	524	1	0	1	1	0	0	0	0	2	0	0	0	0	70041	69702	59715	25	40108	30106	10002	30100	10000	616050	3342686	0	49	63927	70056	70041	64652	3	64959	40100	30200	10000	60200	10000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10001	0	1	0	232	10000	1	1	1	1	1	0	2610	1	71	1	1	69804	30006	9	9	9	10000	30100	70057	70057	70057	70042	70042
40204	70126	525	1	0	1	0	0	0	0	0	2	0	0	1	0	70041	69702	59715	25	40108	30106	10002	30100	10000	616059	3342446	0	49	66976	70053	70053	64652	3	64959	40100	30200	10000	60200	10000	70056	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10003	1	0	10001	0	0	1	238	10000	1	1	1	1	1	0	2610	1	71	1	1	69819	30003	9	0	6	10000	30100	70054	70054	70054	70054	70054
40204	70058	525	1	1	1	0	0	0	0	0	1	0	0	1	0	70041	69787	59701	25	40108	30103	10002	30100	10000	616086	3342830	1	49	66961	70056	70056	64652	3	64956	40100	30200	10000	60200	10000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	3	1	10001	1	1	0	226	10000	1	1	1	1	2	0	2610	1	71	1	1	69804	30006	9	0	6	10000	30100	70054	70057	70054	70057	70042

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0053

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	524	0	0	1	0	0	1	0	0	0	0	1	0	0	70032	1	69743	59695	25	40014	30013	10013	30010	10000	616952	3341470	1	49	66967	70047	70035	64653	3	64960	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10014	0	0	0	10000	1	0	1	0	0	2521	2	71	2	3	69810	30003	6	6	6	10000	30010	70048	70048	70048	70036	70048
40024	70035	525	0	0	0	0	0	0	0	0	1	0	0	0	0	70032	0	69728	59706	25	40014	30013	10001	30010	10000	616952	3342062	1	49	66967	70047	70035	64665	3	64972	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10003	2	1	10002	0	1	4	10000	1	1	0	1	1	2521	2	71	2	2	69816	30006	0	6	6	10000	30010	70061	70054	70042	70064	70054
40024	70053	525	1	1	1	1	1	0	0	0	2	0	1	0	1	70038	0	69702	59712	25	40018	30016	10002	30010	10000	616995	3342350	1	49	66973	70056	70418	64671	3	64978	40010	30020	10000	60020	10000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10001	1	0	16	10000	1	1	1	1	0	2545	2	71	2	2	69816	30006	6	0	0	10000	30010	70057	70148	70138	70061	70054
40024	70053	525	1	0	1	1	0	0	0	0	2	0	1	0	0	70038	0	69702	59712	25	40014	30013	10002	30010	10000	617009	3342350	1	49	66973	70047	70235	64676	3	64966	40010	30020	10000	60020	10000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10003	2	1	10002	2	1	1	10000	1	1	0	1	1	2521	2	71	2	3	69816	30006	6	6	0	10000	30010	70042	70054	70054	70054	70372
40024	70053	525	1	0	1	0	0	0	0	0	1	0	1	0	1	70038	0	69777	59701	25	40018	30016	10002	30586	10000	617009	3342350	1	49	66961	70053	70041	64807	3	64978	40010	30020	10000	60020	10000	70041	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10003	3	1	10002	0	1	4	10000	1	1	1	1	0	2521	2	71	2	2	69816	30003	6	6	6	10000	30010	70042	70042	70057	70042	70054
40024	70041	525	1	1	1	1	0	0	0	0	2	0	1	0	0	70038	0	69779	59715	25	40014	30016	10002	30010	10000	617009	3342350	1	49	66973	70053	70053	64671	3	64977	40010	30020	10000	60020	10000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	3	1	10003	0	2	1	10000	1	1	0	1	2	2521	2	71	2	2	69804	30006	0	6	6	10000	30010	70042	70054	70054	70054	70054
40024	70053	524	1	1	0	2	0	0	0	0	49	264	1	0	1	70038	0	69777	59712	25	40018	30016	10001	30010	10000	617009	3342350	1	49	66961	70423	70061	64659	3	64978	40010	30020	10000	60020	10000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	3	1	10003	2	1	1	10000	1	1	1	1	1	2521	3	71	2	2	69816	30003	6	6	0	10000	30010	70054	70054	70054	70057	70417
40024	70041	525	1	1	1	0	0	0	0	0	2	0	0	0	1	70041	0	69777	59712	25	40018	30016	10002	30010	10000	616995	3342350	1	49	66973	70053	70053	64659	3	64978	40010	30020	10000	60020	10000	70041	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10002	2	1	10001	0	0	1	10000	1	1	1	1	0	2521	2	71	2	2	69804	30006	6	6	6	10000	30010	70054	70042	70054	70042	70054
40024	70053	525	1	1	0	1	0	0	0	0	1	0	1	0	1	70026	0	69777	59701	25	40018	30016	10002	30010	10000	617009	3342350	1	49	66978	70053	70053	64671	3	64978	40010	30020	10000	60020	10000	70041	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10002	1	0	10003	0	2	1	10006	1	1	1	1	0	2521	2	71	2	2	69816	30003	6	6	6	10000	30010	70054	70054	70054	70054	70054
40024	70053	524	1	1	1	0	1	0	0	0	2	0	1	0	1	70038	0	69777	59712	25	40018	30016	10002	30010	10000	617009	3341769	1	49	66973	70053	70053	64671	3	64978	40010	30020	10000	60020	10000	70053	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10002	1	1	10003	0	2	1	10000	1	1	1	1	0	2521	2	71	2	2	69816	30003	6	0	6	10000	30010	70054	70054	70054	70054	70054

Test 3: throughput

Count: 8

Code:

  ldrsb w0, [x6]
  ldrsb w0, [x6]
  ldrsb w0, [x6]
  ldrsb w0, [x6]
  ldrsb w0, [x6]
  ldrsb w0, [x6]
  ldrsb w0, [x6]
  ldrsb w0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	19	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26737	200	1	0	1	0	0	0	67	0	0	2	26895	2	7	7	19	25	80100	100	80000	100	80013	500	1166590	49	23656	26736	26736	16663	6	16688	80112	200	80024	200	80024	26736	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80021	19	43	0	80059	0	1	2	61	80040	6	1	58	43	19	2	1	1	1	5118	2	16	2	2	26733	0	0	5	80000	100	26737	26737	26737	26737	26715
80204	26714	200	1	0	1	0	0	0	69	0	0	1	26865	3	7	7	19	25	80100	100	80000	100	80013	500	1166590	49	23656	26736	26714	16663	6	16689	80114	200	80024	200	80024	26736	64	1	1	80201	100	99	0	100	80000	100	80000	0	100	80019	20	43	0	80059	1	0	0	21	80039	6	1	19	43	19	1	1	1	1	5118	2	16	2	2	26735	13	13	0	80000	100	26737	26715	26737	26737	26737
80204	26877	200	1	1	0	0	0	0	67	0	0	3	26868	0	0	7	20	25	80100	100	80000	100	80017	500	1167215	49	23634	26736	26736	16664	6	16666	80117	200	80024	200	80024	26736	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80020	19	43	0	80058	0	0	1	60	80040	0	0	58	43	19	2	1	1	1	5118	2	16	2	2	26734	0	13	0	80000	100	26715	26738	26737	26737	26737
80204	26736	200	1	0	0	0	0	0	67	0	0	2	26854	3	7	7	20	25	80100	100	80000	100	80016	500	1169949	49	23657	26736	26714	16663	6	16666	80115	200	80024	200	80024	26736	86	1	1	80201	100	99	0	100	80000	100	80000	1	100	80019	19	43	0	80059	0	0	1	61	80040	0	1	19	43	19	1	1	1	1	5118	2	16	3	2	26733	0	13	5	80000	100	26738	26715	26715	26737	26737
80204	26737	200	1	1	1	1	1	0	24	1	0	2	26913	2	7	0	0	25	80100	100	80000	100	80015	500	1167628	49	23656	26714	26736	16642	6	16688	80116	200	80024	200	80024	26737	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80021	19	43	0	80058	0	0	0	61	80040	6	0	58	43	19	1	1	1	1	5118	2	16	2	2	26734	13	0	5	80000	100	26715	26738	26737	26737	26737
80204	26736	200	1	0	0	0	0	0	21	0	0	3	26897	3	0	7	20	25	80100	100	80000	100	80015	500	1167761	49	23634	26736	26736	16642	6	16688	80115	200	80024	200	80024	26736	64	1	1	80201	100	99	0	100	80000	100	80000	0	100	80019	19	0	0	80059	1	1	0	21	80039	6	1	58	43	19	0	1	1	1	5118	2	16	2	2	26734	13	13	5	80000	100	26715	26737	26738	26737	26737
80204	26715	200	1	1	1	0	0	0	67	1	0	2	26868	3	0	0	20	25	80100	100	80000	100	80015	500	1166501	49	23656	26737	26714	16664	6	16688	80116	200	80024	200	80024	26714	64	1	1	80201	100	99	0	100	80000	100	80000	1	100	80019	19	43	0	80059	0	0	0	61	80040	0	1	59	43	19	1	1	1	1	5118	2	16	2	2	26711	13	0	5	80000	100	26715	26737	26715	26737	26720
80204	26736	200	1	0	1	0	0	0	67	1	0	0	26851	3	9	7	0	25	80100	100	80000	100	80016	500	1167628	49	23634	26736	26736	16664	6	16666	80116	200	80024	200	80024	26736	85	1	1	80201	100	99	0	100	80000	100	80000	1	100	80019	19	43	0	80019	1	0	0	23	80039	0	1	59	43	19	0	1	1	1	5118	2	16	2	2	26711	13	13	0	80000	100	26737	26715	26737	26737	26715
80204	26714	200	1	0	1	0	0	0	69	0	0	3	26722	3	7	0	20	25	80100	100	80000	100	80016	500	1167584	49	23657	26736	26738	16664	6	16666	80115	200	80024	200	80024	26714	86	1	1	80201	100	99	0	100	80000	100	80000	1	100	80020	19	43	0	80058	0	0	0	21	80040	6	1	59	43	19	1	1	1	1	5118	2	16	2	2	26733	13	0	0	80000	100	26737	26715	26738	26715	26737
80204	26895	200	1	1	0	0	0	0	21	1	0	2	26721	2	7	7	1	25	80100	100	80000	100	80013	500	1166590	49	23656	26714	26737	16663	6	16688	80115	200	80024	200	80024	26714	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80019	19	43	0	80019	0	0	0	61	80041	6	1	59	0	19	0	1	1	1	5118	2	16	2	2	26733	0	0	0	80000	100	26737	26737	26737	26715	26715

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26727	200	0	0	44	1	0	1	26712	2	1	12	16	25	80010	10	80000	10	80000	50	1166886	1	49	23647	26731	26731	16676	3	16711	80010	20	80000	20	80000	26731	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80038	0	38	80038	6	1	39	44	1	5020	7	16	0	10	12	26731	0	10	0	80000	10	26729	26729	26732	26709	26709
80024	26727	200	0	0	44	1	0	1	26712	2	1	12	0	25	80010	10	80000	10	80000	50	1166125	1	49	23631	26739	26735	16680	3	16691	80010	20	80000	20	80000	26742	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80000	1	38	80038	6	1	39	43	0	5020	10	16	0	9	9	26728	10	0	7	80000	10	26732	26750	26729	26729	26709
80024	26731	201	0	0	0	0	0	1	26712	2	1	0	0	25	80010	10	80000	10	80000	50	1167124	1	49	23648	26731	26708	16676	3	16711	80010	20	80000	20	80000	26727	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80039	0	38	80038	6	0	38	44	0	5020	7	16	4	6	8	26726	10	10	7	80000	10	26727	26728	26732	26729	26732
80024	26727	200	0	0	44	1	0	1	26712	3	1	12	19	25	80010	10	80000	10	80000	50	1167501	0	49	23648	26708	26731	16652	3	16711	80010	20	80000	20	80000	26727	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80039	1	41	80038	6	1	39	44	0	5020	11	16	0	9	10	26728	10	0	7	80000	10	26728	26732	26709	26732	26717
80024	26731	200	1	0	44	1	0	1	26712	2	12	12	16	25	80010	10	80000	10	80000	50	1167124	1	49	23651	26731	26731	16672	3	16708	80010	20	80000	20	80000	26731	77	1	1	80021	10	9	10	80000	10	80000	1	10	80132	43	80039	1	0	80038	0	1	38	44	0	5020	9	16	0	10	12	26705	0	0	7	80000	10	26733	26754	26752	26728	26709
80024	26731	200	0	0	0	1	0	1	26712	2	1	0	0	25	80010	10	80000	10	80000	50	1166750	0	49	23647	26731	26731	16676	3	16711	80010	20	80000	20	80000	26728	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80039	0	41	80038	6	1	39	0	0	5020	8	16	0	9	9	26728	10	14	0	80000	10	26709	26732	26732	26732	26732
80024	26731	200	0	0	44	0	0	1	26713	0	12	1	19	25	80010	10	80000	10	80000	50	1166750	0	49	23651	26732	26708	16676	3	16688	80010	20	80000	20	80000	26727	77	1	1	80021	10	9	10	80000	10	80000	1	10	80000	43	80038	0	0	80000	6	1	38	43	0	5020	9	16	2	6	9	26728	0	10	0	80000	10	26732	26709	26709	26709	26732
80024	26727	200	0	0	44	1	0	1	26712	2	1	1	19	25	80010	10	80000	10	80000	50	1166750	1	49	23628	26731	26731	16676	3	16707	80010	20	80000	20	80000	26731	56	1	1	80021	10	9	10	80000	10	80000	1	10	80000	43	80039	0	0	80000	0	1	38	44	0	5020	9	16	0	9	8	26705	0	0	7	80000	10	26732	26709	26732	26732	26732
80024	26731	200	0	0	44	0	0	0	26712	0	12	12	19	25	80010	10	80000	10	80000	50	1166750	0	49	23651	26731	26731	16652	3	16707	80010	20	80000	20	80000	26708	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80038	0	0	80038	6	1	0	44	0	5020	9	16	0	11	7	26705	10	10	4	80000	10	26729	26728	26709	26728	26732
80024	26731	200	0	0	44	1	0	1	26712	3	12	1	19	25	80010	10	80000	10	80000	50	1166750	0	49	23651	26731	26708	16676	3	16688	80010	20	80000	20	80000	26731	77	1	1	80021	10	9	10	80000	10	80000	1	10	80000	43	80039	0	38	80038	0	1	38	44	0	5020	10	16	0	10	14	26725	0	10	4	80000	10	26773	26761	26709	26732	26709

LDRSB (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations