Firestorm: LDURSH (64-bit) measurements

Code:

  ldursh x0, [x6, #1]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	394	3	1	0	0	45	1	0	1	379	2	12	12	16	25	1000	1000	1000	15037	0	394	394	216	3	252	1000	1000	1000	396	77	1	1	1001	1000	1000	1000	43	1039	0	39	1039	6	1	39	43	73	1	16	1	1	391	10	10	4	1000	395	395	395	395	395
1004	394	3	0	0	0	45	0	0	1	379	2	12	12	16	25	1000	1000	1000	15018	0	394	394	217	3	252	1000	1000	1000	394	77	1	1	1001	1000	1000	1000	43	1039	0	39	1039	6	1	39	43	73	1	16	1	1	391	10	10	4	1000	395	395	395	399	399
1004	398	3	0	1	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15208	0	398	398	221	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	1000	44	1038	0	38	1038	6	1	39	44	73	1	16	1	1	395	14	14	7	1000	399	399	399	399	399
1004	398	3	0	1	1	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15208	0	398	394	216	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	1000	43	1038	0	45	1038	6	1	39	44	73	1	16	1	1	395	14	14	7	1000	399	399	399	399	399
1004	398	3	0	0	0	44	0	0	1	379	2	1	12	19	25	1000	1000	1000	15274	0	398	398	221	3	256	1000	1000	1000	394	77	1	1	1001	1000	1000	1000	43	1038	0	38	1038	6	1	39	44	73	1	16	1	1	395	14	10	4	1000	395	399	399	399	399
1004	398	3	0	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15265	0	394	398	221	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	1000	43	1038	0	38	1038	6	1	39	43	73	1	16	1	1	395	14	14	7	1000	399	399	399	399	399
1004	398	2	0	0	0	44	0	0	1	383	2	1	12	19	25	1000	1000	1000	15276	0	398	398	221	3	286	1000	1000	1000	398	77	1	1	1001	1000	1000	1000	44	1038	0	38	1038	6	1	38	44	73	1	16	1	1	395	14	14	4	1000	399	402	399	399	399
1004	398	3	0	0	0	44	1	0	1	383	2	1	12	16	25	1000	1000	1000	15267	0	398	398	221	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	1000	43	1038	0	38	1038	6	1	39	44	73	1	16	1	1	391	10	10	4	1000	395	395	395	395	395
1004	394	3	0	1	0	45	0	0	1	383	2	1	1	19	25	1000	1000	1000	15267	0	394	394	217	3	252	1000	1000	1000	394	77	1	1	1001	1000	1000	1000	43	1039	0	38	1038	6	1	39	44	73	1	16	1	1	391	14	14	7	1000	399	395	395	399	399
1004	398	3	0	1	0	44	0	0	1	379	2	1	12	19	25	1000	1000	1000	15267	0	398	398	221	3	256	1000	1000	1000	399	77	1	1	1001	1000	1000	1000	43	1038	0	38	1038	6	1	39	44	73	1	16	1	1	395	14	10	7	1000	399	399	399	399	399

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldursh x0, [x6, #1]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	18	19	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70047	524	1	1	0	0	0	1	0	0	0	70032	69764	59698	25	40100	30103	10001	30100	10000	616005	3342552	1	49	66967	70035	70047	64631	3	64950	40100	30200	10000	60200	10000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	0	0	0	2610	3	71	1	1	69803	30003	9	6	9	10000	30100	70051	70036	70051	70036	70048
40204	70047	525	0	1	1	0	0	0	0	1	0	70035	69735	59709	25	40104	30103	10000	30100	10000	616005	3342206	1	49	66955	70050	70050	64646	3	64953	40100	30200	10000	60200	10000	70050	35	1	1	40202	100	99	100	10000	30100	10000	0	100	10000	1	10000	1	0	10000	0	1	0	0	2610	1	71	1	1	69798	30000	0	0	9	10000	30100	70051	70036	70036	70036	70036
40204	70050	524	0	0	0	0	0	1	0	0	0	70035	69781	59709	25	40104	30103	10001	30100	10000	616005	3342206	1	49	66967	70050	70050	64646	3	64950	40100	30200	10000	60200	10000	70050	35	1	1	40202	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	1	0	0	2610	1	71	1	1	69813	30003	0	6	9	10000	30100	70036	70051	70036	70036	70036
40204	70050	524	0	0	0	0	0	1	0	0	0	70032	69764	59695	25	40104	30100	10001	30100	10000	616175	3342206	1	49	66975	70050	70050	64646	3	64950	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	0	2610	1	71	1	1	69813	30003	6	0	9	10000	30100	70051	70036	70036	70051	70051
40204	70050	525	0	0	0	0	0	1	0	0	0	70032	69781	59709	25	40104	30100	10000	30100	10000	616005	3341470	1	49	66955	70050	70047	64631	3	64953	40100	30200	10000	60200	10000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	0	0	0	2610	1	71	1	1	69798	30003	9	0	9	10000	30100	70036	70051	70051	70048	70051
40204	70035	525	0	0	0	0	0	1	0	0	0	70032	69764	59709	25	40104	30100	10001	30100	10000	616005	3342206	1	49	66967	70035	70050	64646	3	64953	40100	30200	10000	60200	10000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	0	2610	1	71	1	3	69828	30000	0	6	6	10000	30100	70048	70051	70051	70051	70036
40204	70047	525	0	0	1	0	0	0	0	0	1	70035	69781	59695	25	40104	30100	10001	30100	10000	616005	3341470	1	49	66955	70050	70035	64631	3	64953	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	0	2610	1	71	1	1	69813	30003	9	6	6	10000	30100	70051	70051	70036	70051	70051
40204	70050	525	0	0	0	0	0	1	0	0	1	70035	69764	59706	25	40104	30103	10001	30100	10000	616005	3342062	1	49	66970	70035	70050	64631	3	64953	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	0	0	0	0	2610	1	71	1	1	69798	30003	9	0	9	10000	30100	70099	70061	70051	70051	70051
40204	70074	525	0	1	0	0	0	1	0	0	0	70040	69781	59695	25	40100	30100	10001	30100	10000	616005	3342206	1	49	66955	70035	70035	64643	3	64953	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	1	0	10000	0	1	0	0	2610	1	71	1	1	69813	30000	9	6	9	10000	30100	70051	70036	70051	70051	70051
40204	70047	524	0	0	0	0	0	6	0	0	1	70020	69764	59709	25	40100	30103	10001	30100	10000	616005	3341470	1	49	66970	70035	70035	64648	3	64938	40100	30200	10000	60200	10000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	0	0	0	2610	1	71	1	1	69798	30000	0	9	0	10000	30100	70051	70051	70036	70036	70051

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0081

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70051	524	1	0	1	1	0	0	0	7	0	1	0	0	1	70042	69781	59716	25	40018	30016	10002	30010	10000	617198	3341961	49	67348	70057	70057	64675	3	64982	40010	30020	10000	60020	10000	70051	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	1	88	10000	1	1	0	1	1	0	2520	6	71	5	3	69820	30003	10	10	10	10000	30010	70058	70058	70042	70058	70058
40024	70088	524	1	0	1	1	0	0	0	2	0	0	0	0	1	70042	69781	59716	25	40018	30016	10008	30010	10000	617045	3342542	49	66977	70057	70060	64666	3	64982	40010	30020	10000	60020	10000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10001	40	0	3	10000	1	0	1	0	0	0	2520	3	71	3	5	69821	30006	10	10	10	10000	30010	70058	70058	70058	70058	70058
40024	70096	525	1	0	0	1	0	0	0	2	0	1	0	0	0	70042	69781	59717	25	40066	30016	10001	30010	10000	616991	3342254	49	66971	70051	70051	64669	3	64976	40010	30020	10000	60020	10000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	4	6	91	10000	0	1	1	1	1	0	2520	3	71	3	5	69823	30006	0	10	10	10000	30010	70042	70058	70058	70042	70147
40024	70057	525	1	0	1	0	0	0	0	2	0	1	0	0	0	70042	69781	59716	25	40018	30016	10010	30010	10000	617045	3342542	49	66977	70041	70064	64675	3	64982	40010	30020	10000	60020	10000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10001	0	3	127	10000	1	1	1	1	1	0	2520	4	71	4	2	69821	30006	10	10	10	10000	30010	70058	70058	70058	70042	70058
40024	70063	525	0	0	0	0	0	0	0	1	0	1	0	0	0	70020	69775	59710	25	40014	30016	10002	30010	10000	617045	3342542	49	66977	70057	70057	64675	3	64982	40010	30020	10000	60020	10000	70044	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	0	10002	0	2	97	10000	1	1	1	1	0	0	2520	4	71	4	3	69820	30006	10	10	10	10000	30010	70060	70058	70058	70058	70058
40024	70108	525	0	0	1	0	0	0	0	2	0	1	0	0	0	70042	69781	59716	25	40018	30016	10002	30010	10000	617045	3342542	49	66977	70057	70062	64678	3	64982	40010	30020	10000	60020	10000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	3	1	10002	1	0	147	10000	0	0	1	0	0	0	2520	5	71	3	4	69814	30000	10	0	10	10000	30010	70052	70052	70052	70052	70145
40024	70057	524	1	0	0	1	1	0	0	2	0	1	0	0	1	70042	69781	59716	25	40018	30016	10002	30010	10000	617045	3342542	49	66977	70057	70057	64675	3	64982	40010	30020	10000	60020	10000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	3	1	10002	0	3	16	10000	1	1	1	1	2	0	2520	4	71	2	4	69804	30006	10	10	0	10000	30010	70058	70058	70058	70058	70152
40024	70057	525	1	0	0	0	0	0	0	7	0	1	0	0	1	70045	69702	59701	25	40018	30016	10001	30010	10000	617027	3342350	49	66971	70035	70051	64653	3	64976	40010	30020	10000	60020	10000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	84	2	1	10000	1	1	1	1	2	0	2520	4	71	3	5	69823	30006	10	0	10	10000	30010	70058	70042	70058	70058	70058
40024	70093	525	0	0	0	0	0	0	0	52	352	1	0	0	0	70036	69702	59716	25	40018	30016	10001	30010	10000	616991	3342254	49	66971	70035	70035	64669	3	64976	40010	30020	10220	60020	10000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	2	163	10000	1	1	1	1	1	0	2520	4	71	4	3	69820	30003	0	10	10	10000	30010	70042	70042	70058	70058	70058
40024	70078	527	0	0	0	0	0	0	0	565	0	1	0	0	0	70036	69775	59710	25	40014	30016	10002	30010	10000	617045	3342542	49	66977	70057	70057	64678	3	64966	40010	30020	10000	60020	10000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	1	10002	19	0	3	10000	0	0	1	0	0	0	2520	5	71	2	4	69822	30003	10	10	10	10000	30010	70058	70058	70042	70058	70058

Test 3: throughput

Count: 8

Code:

  ldursh x0, [x6, #1]
  ldursh x0, [x6, #1]
  ldursh x0, [x6, #1]
  ldursh x0, [x6, #1]
  ldursh x0, [x6, #1]
  ldursh x0, [x6, #1]
  ldursh x0, [x6, #1]
  ldursh x0, [x6, #1]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	19	1e	1f	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26723	200	0	0	0	41	0	0	0	1	26692	2	18	0	0	25	80100	100	80000	100	80015	500	1177116	49	23642	0	26727	26727	16650	3	16685	80100	200	80000	200	80000	26736	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80039	0	39	80039	6	1	35	39	0	5110	1	16	1	1	26724	0	10	6	0	80000	100	26728	26728	26728	26728	26728
80204	26722	200	0	1	0	0	0	0	0	2	26707	3	0	18	12	25	80100	100	80000	100	80000	500	1167808	49	23647	0	26727	26727	16650	3	16686	80100	200	80000	200	80000	26714	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80039	1	35	80169	6	1	35	43	0	5110	1	16	1	1	26724	0	0	6	2	80000	100	26728	26728	26708	26723	26728
80204	26727	200	0	0	0	0	0	1	0	2	26712	0	12	12	11	25	80100	100	80000	100	80000	500	1167231	49	23647	0	26707	26727	16650	3	16665	80100	200	80000	200	80000	26727	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80039	0	39	80039	6	0	35	43	0	5110	1	16	1	1	26724	0	0	10	0	80000	100	26728	26723	26728	26723	26723
80204	26727	200	0	0	0	41	0	1	0	2	26712	2	12	12	16	25	80100	100	80000	100	80000	500	1166525	49	23647	0	26707	26727	16650	3	16685	80100	200	80000	200	80000	26739	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80039	3	35	80039	0	1	0	43	0	5110	1	16	1	1	26724	0	6	6	0	80000	100	26728	26728	26728	26728	26728
80204	26707	200	0	0	0	45	0	0	0	1	26722	2	12	18	16	25	80100	100	80000	100	80000	500	1165789	49	23642	0	26727	26722	16650	3	16727	80100	200	80000	200	80000	26741	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80039	0	39	80039	6	1	35	43	0	5110	4	16	1	1	26724	0	10	6	4	80000	100	26728	26728	26723	26723	26723
80204	26722	200	0	0	0	45	0	0	0	1	26712	2	12	12	16	25	80100	100	80000	100	80000	500	1159747	49	23647	0	26707	26727	16630	3	16741	80100	200	80000	200	80000	26727	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80035	0	39	80035	6	1	36	43	0	5110	2	16	1	1	26724	0	10	0	2	80000	100	26708	26728	26708	26728	26728
80204	26727	200	0	0	0	45	0	0	0	0	26707	2	12	12	0	25	80100	100	80000	100	80000	500	1165789	49	23647	0	26727	26727	16630	3	16685	80100	200	80000	200	80000	26722	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80035	0	39	80039	6	1	39	39	0	5110	1	16	1	1	26724	0	10	0	4	80000	100	26728	26728	26728	26728	26728
80204	26727	200	0	0	0	45	0	0	0	1	26712	0	12	12	16	25	80100	100	80000	100	80000	500	1167231	49	23647	0	26707	26727	16630	3	16685	80100	200	80000	200	80000	26735	72	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80039	0	39	80035	6	1	0	43	0	5110	1	16	1	1	26704	0	6	10	4	80000	100	26728	26728	26723	26728	26728
80204	26727	200	0	0	0	45	0	0	0	2	26712	2	0	0	11	25	80100	100	80000	100	80000	500	1167231	49	23627	0	26722	26722	16645	3	16685	80100	200	80000	200	80000	26729	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80000	0	35	80035	6	1	35	39	0	5110	1	16	1	1	26724	0	10	6	4	80000	100	26728	26728	26728	26728	26708
80204	26727	200	0	0	0	45	0	0	0	2	26692	2	12	0	12	25	80100	100	80000	100	80000	500	1167231	49	23647	0	26727	26727	16650	3	16685	80100	200	80000	200	80000	26736	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	80035	0	39	80000	0	1	39	43	0	5110	1	16	1	1	26724	0	10	6	4	80000	100	26708	26708	26728	26708	26728

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	0e	0f	1e	1f	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26737	200	0	0	0	1	0	44	0	1	1	26693	2	0	1	16	25	80010	10	80000	10	80000	50	1168322	0	49	23651	0	26708	26731	16652	3	16711	80010	20	80000	20	80000	26731	77	1	1	80021	10	9	10	80000	10	80000	1	10	80000	0	0	0	80038	1	0	41	80000	6	1	39	0	0	0	5020	21	16	17	17	26728	0	0	10	7	80000	10	26732	26732	26709	26732	26709
80024	26739	200	0	0	0	1	0	44	0	1	1	26724	0	1	0	16	25	80010	10	80000	10	80000	50	1167501	0	49	23651	0	26731	26708	16676	3	16688	80010	20	80000	20	80000	26708	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	0	80038	1	0	50	80000	6	1	39	44	0	0	5020	16	17	17	16	26728	0	14	10	7	80000	10	26732	26709	26709	26714	26731
80024	26708	200	0	0	0	0	0	44	0	1	0	26693	2	1	1	19	25	80010	10	80000	10	80000	50	1169737	0	49	23651	0	26733	26708	16676	3	16688	80010	20	80000	20	80000	26731	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80038	0	0	6	80038	6	0	39	44	0	0	5020	16	16	17	16	26724	0	14	10	7	80000	10	26732	26732	26732	26729	26732
80024	26749	201	0	0	0	0	0	45	0	0	1	26716	0	12	0	0	25	80010	10	80000	10	80000	50	1167124	0	49	23651	0	26708	26731	16676	3	16688	80010	20	80000	20	80000	26708	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	44	0	80000	1	0	48	80038	6	0	39	44	0	0	5020	17	16	17	17	26705	0	14	14	7	80000	10	26822	26716	26709	26729	26741
80024	26740	200	0	0	0	0	0	0	0	0	1	26716	0	1	1	88	25	80010	10	80000	10	80000	50	1168843	1	49	23628	0	26728	26727	16652	3	16711	80010	20	80000	20	80000	26731	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80000	0	0	44	80038	6	1	39	44	0	0	5020	19	16	17	17	26728	1	0	10	4	80000	10	26732	26729	26709	26709	26728
80024	26715	201	0	0	0	0	0	44	0	0	0	26720	2	0	1	16	25	80010	10	80000	10	80000	50	1167124	1	49	23651	3	26732	26735	16676	3	16688	80010	20	80000	20	80000	26708	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	0	80000	1	0	56	80038	6	1	39	0	0	0	5020	17	16	17	17	26728	0	14	0	0	80000	10	26732	26709	26729	26732	26732
80024	26721	200	0	0	0	0	0	0	0	1	1	26693	0	12	7	21	25	80010	10	80000	10	80000	50	1167124	0	49	23651	0	26731	26727	16676	3	16708	80010	20	80000	20	80000	26728	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	44	0	80039	1	0	57	80000	0	1	0	0	0	0	5020	17	16	18	17	26728	0	14	14	7	80000	10	26732	26732	26709	26732	26728
80024	26743	201	0	0	0	1	0	45	0	0	0	26713	2	12	1	16	25	80010	10	80000	10	80000	50	1168843	0	49	23628	0	26731	26731	16676	3	16711	80010	20	80000	20	80000	26731	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	0	80038	2	0	41	80000	6	1	0	44	0	0	5020	18	16	17	17	26728	0	14	14	7	80000	10	26732	26732	26732	26709	26729
80024	26737	201	0	0	0	0	0	0	0	0	0	26716	2	0	0	16	25	80010	10	80000	10	80000	50	1166886	0	49	23628	0	26731	26708	16676	3	16688	80010	20	80000	20	80000	26731	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80039	1	0	45	80000	6	1	39	44	0	0	5020	19	16	21	19	26705	0	0	10	7	80000	10	26732	26728	26732	26709	26714
80024	26727	200	0	0	0	1	0	45	0	1	1	26716	2	1	1	0	25	80010	10	80000	10	80000	50	1167201	1	49	23628	0	26731	26708	16676	3	16711	80010	20	80000	20	80000	26708	56	1	1	80021	10	9	10	80000	10	80000	1	10	80000	0	43	0	80000	2	0	15	80039	0	1	39	43	0	0	5020	12	16	18	17	26728	0	0	14	7	80000	10	26732	26731	26709	26732	26713

LDURSH (64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations