Firestorm: ROR (immediate, 64-bit) measurements

Code:

  ror x0, x0, #17

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	1e	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1035	8	1	1	1	0	3	68	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	0	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	1	0	1	0	3	68	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	0	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	1	0	1	0	3	68	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	0	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	1	0	1	0	3	68	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	12	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	1	0	1	0	3	68	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	0	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	1	0	1	0	3	68	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	0	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	1	0	1	9	3	68	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	15	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	1	0	1	0	3	68	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	0	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	1	0	1	0	3	68	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	15	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	1	0	1	0	3	68	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	15	79	4	41	4	4	937	1000	1000	1036	1036	1036	1036	1036

Test 2: Latency 1->2

Code:

  ror x0, x0, #17

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	103	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	10200	10035	41	1	1	10201	100	99	100	10100	100	0	6	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	10200	10035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	82	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	10200	10035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	10200	10035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	10200	10035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	10200	10035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	10200	10035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	10200	10035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	10200	10035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	10200	10035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	61	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10165	10191	10020	10080	41	1	1	10021	10	9	10	10010	10	1	9	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	82	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10035	41	1	1	10021	10	9	10	10010	10	3	60	640	2	41	2	2	9940	10000	10010	10036	10174	10036	10036	10036
10024	10035	75	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10035	41	1	1	10021	10	9	10	10010	10	0	3	640	3	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10035	41	1	1	10021	10	9	10	10010	10	1	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10035	41	1	1	10021	10	9	10	10010	10	0	0	671	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	82	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10035	41	1	1	10021	10	9	10	10010	10	1	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036

Test 3: throughput

Count: 8

Code:

  ror x0, x8, #17
  ror x1, x8, #17
  ror x2, x8, #17
  ror x3, x8, #17
  ror x4, x8, #17
  ror x5, x8, #17
  ror x6, x8, #17
  ror x7, x8, #17

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.1674

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	13415	100	0	28	27	80136	80136	80148	400710	0	49	10310	13390	13390	3326	6	3336	80148	80264	80264	13390	39	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5119	16	0	0	13387	80036	80100	13391	13391	13682	13391	13391
80204	13390	101	21	28	27	80136	80136	80148	400710	1	49	10310	13390	13390	3326	6	3336	80148	80264	80264	13390	39	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5119	16	0	0	13387	80036	80100	13391	13391	13391	13391	13391
80204	13390	101	0	28	27	80136	80136	80148	400710	1	49	10310	13390	13390	3326	6	4970	80148	80264	80264	13390	39	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5119	16	0	0	13387	80036	80100	13391	13391	13391	13391	13391
80204	13390	101	0	91	27	80136	80136	80148	400710	0	49	10310	13390	13390	3327	6	3336	80148	80264	80264	13390	39	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5119	16	0	0	13387	80036	80100	13391	13391	13391	13391	13391
80204	13390	100	0	28	27	80136	80136	80148	400710	0	49	10310	13390	13390	3326	6	3336	80148	80264	80264	13390	39	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5119	16	0	0	13387	80036	80100	13391	13391	13391	13391	13391
80204	13390	100	0	28	27	80136	80136	80148	400710	0	49	10310	13390	13390	3326	6	3336	80148	80264	80264	13390	39	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5119	16	0	0	13387	80036	80100	13391	13391	13391	13391	13391
80204	13390	100	0	28	27	80136	80136	80148	400710	0	49	10310	13390	13390	3326	6	3336	80148	80264	80264	13390	39	1	1	80202	100	99	100	80100	100	0	0	1	1	1	5121	16	0	0	13387	80036	80100	13391	13391	13391	13391	13391
80204	13390	101	0	28	27	80136	80136	80148	400710	0	49	10310	13390	13390	3326	6	3336	80148	80264	80264	13390	39	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5119	16	0	0	13387	80036	80100	13391	13391	13391	13391	13391
80204	13390	100	0	28	27	80136	80136	80148	400710	0	49	10310	13390	13390	3326	6	3336	80148	80264	80264	13390	39	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5119	16	0	0	13387	80036	80100	13391	13391	13391	13391	13391
80204	13390	100	0	70	27	80136	80136	80148	400710	0	49	10310	13390	13390	3326	6	3336	80148	80264	80264	13390	39	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5119	16	0	0	13387	80036	80100	13391	13391	13391	13391	13391

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.1671

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? int retires (ef)	f5	f6	f7	f8	fd
80024	13377	100	0	35	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	0	3	3348	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	0	0	5022	0	11	19	0	0	0	7	4	13368	80000	74	0	80010	13372	13372	13372	13372	13372
80024	13371	100	0	35	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	0	3	3348	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	0	0	5021	0	4	19	0	0	0	6	4	13368	80000	57	0	80010	13372	13372	13372	13372	13372
80024	13371	100	0	35	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	0	3	3348	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	1	0	5021	0	4	19	0	0	0	4	6	13368	80000	74	0	80010	13372	13372	13372	13372	13372
80024	13371	100	0	35	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	0	3	3348	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	1	0	5022	0	4	19	0	0	0	6	4	13368	80000	88	0	80010	13372	13372	13372	13372	13372
80024	13371	101	0	41	25	80010	80010	80010	400050	1	49	10291	13371	13371	3330	0	3	3348	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	0	3	5023	0	6	19	0	0	0	6	4	13368	80000	57	0	80010	13372	13372	13372	13372	13372
80024	13371	100	0	35	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	0	3	3348	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	0	0	5023	1	5	19	0	0	0	7	7	13368	80000	58	2	80010	13372	13372	13372	13372	13372
80024	13371	100	0	41	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	0	3	3348	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	0	0	5022	0	6	19	0	0	0	4	6	13368	80000	57	0	80010	13372	13372	13372	13372	13372
80024	13371	100	0	35	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	0	3	3348	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	0	0	5022	0	6	19	0	0	0	6	4	13368	80000	58	0	80010	13372	13372	13372	13372	13372
80024	13371	100	0	35	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	0	3	3348	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	1	0	5022	0	6	19	0	0	0	6	4	13368	80000	57	0	80010	13372	13372	13372	13372	13372
80024	13371	100	0	35	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	0	3	3348	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	0	0	5022	0	8	19	0	0	0	6	4	13368	80000	58	0	80010	13372	13372	13372	13372	13372

ROR (immediate, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations