Firestorm: PRFM (register, PSTL1STRM) measurements

Code:

  prfm pstl1strm, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3a	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	1595	12	33	19	34	2480	139	1597	873	25	1000	1000	1000	69552	1	1573	1601	1305	3	1460	1000	1000	1000	1570	1573	1	1	1001	271	2266	2262	3266	0	2464	2283	1000	73	1	16	1	1	1518	1000	1625	1600	1591	1596	1573
1004	1635	12	34	16	34	2479	118	1544	916	25	1000	1000	1000	68225	0	1580	1606	1318	3	1451	1000	1000	1000	1601	1579	1	1	1001	269	2262	2262	3261	0	2461	2260	1000	73	1	16	1	1	1485	1000	1574	1579	1565	1615	1596
1004	1595	12	34	17	33	2449	131	1559	879	25	1000	1000	1000	68937	0	1584	1592	1292	3	1475	1000	1000	1000	1569	1570	1	1	1001	250	2268	2259	3299	0	2460	2270	1000	73	1	16	1	1	1495	1000	1593	1631	1582	1590	1617
1004	1613	12	33	17	33	2471	126	1558	866	25	1000	1000	1000	69231	0	1542	1574	1286	3	1427	1000	1000	1000	1596	1558	1	1	1001	238	2290	2303	3286	0	2445	2279	1000	73	1	16	1	1	1513	1000	1578	1610	1571	1602	1575
1004	1598	12	32	18	33	2460	121	1585	902	25	1000	1000	1000	69538	1	1592	1602	1325	3	1459	1000	1000	1000	1567	1595	1	1	1001	259	2259	2290	3264	0	2478	2257	1000	73	1	16	1	1	1486	1000	1594	1569	1587	1627	1618
1004	1629	12	34	16	35	2439	118	1585	870	25	1000	1000	1000	70239	1	1600	1617	1282	3	1432	1000	1000	1000	1577	1569	1	1	1001	258	2265	2265	3236	0	2441	2266	1000	73	1	16	1	1	1498	1000	1627	1592	1572	1580	1574
1004	1571	12	33	16	33	2446	131	1602	862	25	1000	1000	1000	70698	1	1603	1581	1301	3	1444	1000	1000	1000	1582	1601	1	1	1001	263	2278	2280	3267	0	2468	2276	1000	73	1	16	1	1	1507	1000	1570	1580	1577	1587	1587
1004	1610	12	33	16	32	2456	120	1578	872	25	1000	1000	1000	69264	1	1590	1602	1281	3	1472	1000	1000	1000	1608	1613	1	1	1001	247	2281	2255	3266	0	2455	2273	1000	73	1	16	1	1	1485	1000	1577	1626	1584	1616	1618
1004	1606	12	34	18	34	2448	122	1588	882	25	1000	1000	1000	68915	1	1575	1592	1278	3	1475	1000	1000	1000	1573	1602	1	1	1001	247	2305	2231	3271	0	2446	2280	1000	73	1	16	1	1	1504	1000	1573	1572	1594	1590	1634
1004	1610	12	32	17	32	2453	141	1575	912	25	1000	1000	1000	70304	1	1589	1599	1285	3	1452	1000	1000	1000	1585	1590	1	1	1001	259	2285	2300	3235	0	2443	2262	1000	73	1	16	1	1	1530	1000	1571	1573	1629	1573	1614

Test 2: throughput

Code:

  prfm pstl1strm, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5777

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	15774	118	335	184	337	24279	9824	15685	9786	48	20218	10208	10000	10100	10114	135076	743293	42	49	12780	15797	15880	13143	7	13256	20104	10220	10016	10208	10016	15728	155	1	1	20201	100	99	2594	100	10100	100	22633	22495	32440	0	24367	22732	10000	1	1	1	1317	0	16	0	0	15717	10111	10000	10100	15764	15732	15857	15819	15904
20204	15920	119	337	181	334	24256	9800	15936	9899	25	20208	10184	10000	10116	10000	132735	733561	32	49	12755	15752	15886	13141	6	13249	20104	10216	10008	10204	10008	15833	156	1	1	20201	100	99	2427	100	10100	100	22586	22485	32526	0	24144	22636	10000	1	1	1	1317	0	16	0	0	15702	10102	10000	10100	15885	15828	15847	15950	15725
20204	15819	119	333	178	330	24416	9865	15845	9821	25	20205	10214	10000	10100	10000	133105	736935	34	49	12717	15669	15923	13096	3	13312	20100	10200	10000	10200	10000	15827	163	1	1	20201	100	99	2481	100	10100	100	22654	22658	32604	0	24139	22700	10000	0	0	0	1310	1	16	1	1	15782	10135	10000	10100	15755	15799	15748	15828	15786
20204	15758	118	331	179	337	24146	9831	15651	9787	25	20208	10208	10000	10100	10000	132265	741237	33	49	12735	15753	15788	13170	3	13179	20100	10200	10000	10200	10000	15774	157	1	1	20201	100	99	2565	100	10100	100	22542	22650	32569	1	24323	22642	10000	0	0	0	1310	1	16	1	1	15635	10356	10000	10100	15765	15792	15819	15803	15840
20204	15787	119	330	181	334	24383	9806	15707	9881	25	20211	10214	10000	10100	10000	133785	743560	47	49	12677	15682	15738	13003	3	13339	20100	10200	10000	10200	10000	15647	156	1	1	20201	100	99	2621	100	10100	100	22565	22592	32587	1	24173	22638	10000	0	0	0	1310	1	17	1	1	15587	10114	10000	10100	15810	15795	15737	15700	15796
20204	15763	118	330	183	334	24349	9808	15748	9872	25	20199	10172	10000	10100	10000	132080	739048	34	49	12663	15723	15725	13138	3	13315	20100	10200	10000	10200	10000	15753	157	1	1	20201	100	99	2481	100	10100	100	22512	22623	32606	0	24211	22596	10000	0	0	0	1310	1	16	1	1	15736	10105	10000	10100	15788	15803	15746	15725	15807
20204	15806	119	338	181	331	24210	9802	15729	9780	25	20208	10196	10000	10100	10000	131883	741969	31	49	12689	15702	15850	13244	3	13285	20100	10200	10000	10200	10000	15825	156	1	1	20201	100	99	2509	100	10100	100	22689	22666	32421	0	24380	22582	10000	0	0	0	1310	1	16	1	1	15668	10093	10000	10100	15792	15803	15766	15729	15783
20204	15673	119	335	183	331	24287	9887	15770	9840	25	20241	10196	10000	10100	10000	132909	742520	34	49	12594	15814	15782	13069	3	13407	20100	10200	10000	10200	10000	15676	156	1	1	20201	100	99	2547	100	10100	100	22553	22619	32565	0	24319	22603	10000	0	0	0	1310	1	16	1	1	15601	10099	10000	10100	15921	15895	15748	15705	15851
20204	15778	119	329	180	334	24304	9809	15698	9889	25	20190	10211	10000	10100	10000	133390	739927	38	49	12658	15741	15791	13072	3	13250	20100	10200	10000	10200	10000	15706	162	1	1	20201	100	99	2628	100	10100	100	22663	22465	32556	0	24362	22559	10000	0	0	0	1310	1	17	1	1	15694	10562	10000	10100	15771	15820	15863	15761	15772
20204	15842	118	338	180	332	24164	9751	15836	9831	25	20214	10199	10000	10100	10000	134198	740413	35	49	12676	15656	15662	13216	3	13260	20100	10200	10000	10200	10000	15878	155	1	1	20201	100	99	2551	100	10100	100	22642	22617	32613	0	24379	22502	10000	0	0	0	1310	1	16	1	1	15754	10102	10000	10100	15803	15688	15797	15778	15816

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5698

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	15675	117	354	182	354	24646	9916	15670	9866	25	20151	10166	10000	10010	10000	133613	732507	0	50	49	12670	15753	15668	12901	3	13125	20010	10020	10000	10020	10000	15844	165	1	1	20021	10	9	2450	10	10010	10	22993	22785	32845	0	24501	22798	10000	1270	2	16	2	1	15513	10150	10000	10010	15729	15821	15781	15746	15870
20024	15792	118	345	179	342	24660	9889	15608	9578	25	20124	10157	10000	10010	10000	131321	735992	0	43	49	12549	15593	15803	13173	3	13151	20010	10020	10000	10020	10000	15786	166	1	1	20021	10	9	2327	10	10010	10	22937	22997	32585	0	24383	22792	10000	1270	1	16	1	1	15599	10159	10000	10010	15788	15669	15738	15897	15711
20024	15730	118	349	183	347	24513	9988	15827	9866	25	20166	10157	10000	10010	10000	130992	734124	0	42	49	12605	15685	15715	12867	3	13378	20010	10020	10000	10020	10000	15835	156	1	1	20021	10	9	2383	10	10010	10	23031	22898	32928	0	24494	22818	10000	1270	1	16	2	1	15595	10135	10000	10010	15804	15578	15667	15585	15807
20024	15793	118	344	191	352	24516	9938	15794	9661	25	20121	10124	10000	10010	10000	133793	731330	0	43	49	12655	15672	15660	12986	3	13198	20010	10020	10000	10020	10000	15640	155	1	1	20021	10	9	2410	10	10010	10	22798	22964	32738	0	24618	22973	10000	1270	1	16	2	1	15520	10075	10000	10010	15734	15797	15658	15807	15839
20024	15668	118	359	177	354	24506	9901	15775	9606	25	20160	10157	10000	10010	10000	131737	738187	0	40	49	12593	15727	15739	13033	3	13146	20010	10020	10000	10020	10000	15678	155	1	1	20021	10	9	2317	10	10010	10	22756	22971	32748	0	24535	22878	10000	1270	1	16	1	1	15588	10114	10000	10010	15678	15559	16154	15732	15771
20024	15807	117	347	185	352	24371	9904	15594	9767	25	20109	10142	10000	10010	10000	133032	734920	0	38	49	12613	15671	15757	13168	3	13418	20010	10020	10000	10020	10000	15721	155	1	1	20021	10	9	2391	10	10010	10	22786	22627	32923	0	24516	22886	10000	1270	1	16	1	1	15551	10132	10000	10010	15781	15761	15693	15674	15812
20024	15693	117	352	184	345	24659	9908	15694	9690	25	20163	10142	10000	10010	10000	131769	733410	0	44	49	12802	15681	15720	13045	3	13198	20010	10020	10000	10020	10000	15648	154	1	1	20021	10	9	2345	10	10010	10	22785	22648	33107	0	24696	22887	10000	1271	1	15	1	1	15657	10141	10000	10010	15694	15597	15701	15731	15601
20024	15643	117	353	185	343	24603	9855	15564	9748	25	20169	10169	10000	10010	10000	132057	735628	0	34	49	12712	15629	15702	13038	3	13210	20010	10020	10000	10020	10000	15792	147	1	1	20021	10	9	2314	10	10010	10	22872	22940	32932	0	24477	22765	10000	1270	1	16	1	1	15676	10159	10000	10010	15831	15669	15738	15681	15851
20024	15748	118	349	188	347	24513	9861	15712	9712	25	20136	10151	10000	10010	10000	132860	741735	0	59	49	12572	15777	15761	12979	3	13066	20010	10020	10000	10020	10000	15609	154	1	1	20021	10	9	2279	10	10010	10	22717	22764	32736	0	24432	22889	10000	1270	1	16	1	1	15480	10153	10000	10010	15732	15709	15569	15676	15762
20024	15726	117	358	181	353	24495	9898	15654	9700	25	20112	10124	10000	10010	10000	131163	735967	0	40	49	12771	15651	15896	12986	3	13147	20010	10020	10000	10020	10000	15693	156	1	1	20021	10	9	2270	10	10010	10	22801	22981	32867	0	24713	22992	10000	1270	1	16	1	1	15681	10144	10000	10010	15790	15682	15642	15784	15727

Test 3: throughput

Code:

  prfm pstl1strm, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5536

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	ac	bb	l1d tlb miss nonspec (c1)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10204	15529	116	288	143	285	23952	1355	15498	9591	25	10100	100	10000	100	10005	500	728799	0	49	12419	15431	15563	14080	7	14227	10104	200	10008	200	10016	15460	12256	1	1	10201	100	99	2685	100	100	100	22210	22241	32265	23959	22164	10000	1	1	1	717	0	24	0	0	15440	10000	100	15564	15527	15589	15502	15550
10204	15536	116	290	143	289	23954	1343	15513	9568	25	10100	100	10000	100	10001	500	725947	0	49	12412	15496	15518	14033	6	14215	10100	200	10008	200	10008	15478	12204	1	1	10201	100	99	2729	100	100	100	22170	22266	32250	24034	22229	10000	1	1	1	719	0	16	0	0	15403	10000	100	15438	15635	15565	15607	15565
10204	15570	117	288	145	290	23959	1328	15503	9540	25	10100	100	10000	100	10000	500	728471	0	49	12379	15642	15569	14105	6	14272	10100	200	10008	200	10016	15434	12339	1	1	10201	100	99	2782	100	100	100	22195	22238	32215	24021	22262	10000	1	1	1	718	0	16	0	0	15345	10000	100	15568	15499	15555	15494	15563
10204	15489	117	288	146	285	23972	1390	15438	9540	25	10100	100	10000	100	10000	500	727801	0	49	12337	15483	15523	14097	6	14193	10100	200	10016	200	10016	15434	12339	1	1	10201	100	99	2668	100	100	100	22248	22204	32129	23994	22200	10000	1	1	1	717	0	16	0	0	15371	10000	100	15438	15498	15565	15581	15512
10204	15526	116	288	144	290	23994	1356	15621	9542	25	10100	100	10000	100	10000	500	729813	0	49	12337	15483	15523	14095	7	14272	10100	200	10008	200	10016	15434	12253	1	1	10201	100	99	2728	100	100	100	22240	22204	32166	23966	22240	10000	1	1	1	719	0	16	0	0	15390	10000	100	15549	15558	15520	15546	15472
10204	15520	116	287	143	286	24010	1310	15536	9604	25	10100	100	10000	100	10000	500	726869	0	49	12474	15479	15646	14118	7	14224	10100	200	10016	200	10008	15455	12218	1	1	10201	100	99	2689	100	100	100	22239	22260	32180	23926	22280	10000	1	1	1	717	0	16	0	0	15359	10000	100	15610	15629	15540	15575	15579
10204	15583	116	292	144	289	23911	1348	15443	9694	25	10100	100	10000	100	10000	500	721356	0	49	12426	15498	15493	14094	6	14219	10104	200	10008	200	10016	15415	12217	1	1	10201	100	99	2725	100	100	100	22220	22227	32199	23911	22164	10000	1	1	1	717	0	16	0	0	15421	10000	100	15430	15549	15474	15550	15518
10204	15524	116	290	142	290	23996	1311	15547	9617	25	10100	100	10000	100	10000	500	728532	0	49	12383	15541	15587	14056	6	14232	10101	200	10016	200	10008	15608	12296	1	1	10201	100	99	2714	100	100	100	22277	22213	32236	23898	22238	10000	1	1	1	719	0	16	0	0	15453	10000	100	15557	15536	15532	15538	15600
10204	15523	116	290	143	288	23933	1290	15394	9643	25	10100	100	10000	100	10000	500	725708	0	49	12507	15569	15571	14021	6	14263	10100	200	10016	200	10008	15458	12206	1	1	10201	100	99	2639	100	100	100	22210	22240	32255	23953	22149	10000	1	1	1	717	0	16	0	0	15403	10000	100	15637	15503	15470	15511	15518
10204	15609	116	288	144	288	24018	1342	15513	9649	25	10100	100	10000	100	10000	500	723573	0	49	12409	15554	15398	13972	6	14214	10100	200	10016	200	10016	15437	12260	1	1	10201	100	99	2696	100	100	100	22184	22275	32177	23937	22187	10000	1	1	1	717	0	16	0	0	15430	10000	100	15586	15533	15489	15526	15495

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5528

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10024	15491	117	293	147	290	23965	1338	15545	9580	25	10010	10	10000	10	10000	50	725467	0	49	12484	15498	15655	14113	3	14369	10010	20	10000	20	10000	15462	15466	1	1	10021	10	9	2640	10	10	10	22238	22349	32227	0	23952	22284	10000	644	8	16	11	10	15466	10000	10	15495	15557	15487	15593	15687
10024	15633	117	291	147	296	23956	1341	15480	9632	25	10010	10	10000	10	10000	50	726839	0	49	12592	15555	15633	14076	3	14198	10010	20	10000	20	10000	15522	15466	1	1	10021	10	9	2742	10	10	10	22251	22256	32230	0	23983	22300	10000	644	10	16	10	17	15455	10000	10	15387	15584	15477	15488	15516
10024	15606	117	295	145	288	24067	1315	15490	9659	25	10010	10	10000	10	10000	50	722790	1	49	12475	15623	15566	14138	3	14313	10010	20	10000	20	10000	15541	15709	1	1	10021	10	9	2709	10	10	10	22234	22261	32381	0	23965	22284	10000	644	10	16	10	10	15442	10000	10	15505	15609	15532	15567	15658
10024	15644	116	294	148	293	24074	1350	15562	9648	25	10010	10	10000	10	10000	50	726939	1	49	12516	15473	15546	14117	3	14217	10010	20	10000	20	10000	15542	15578	1	1	10021	10	9	2653	10	10	10	22253	22277	32231	0	24025	22342	10000	644	10	16	10	10	15422	10000	10	15569	15527	15533	15521	15505
10024	15464	116	294	145	296	24001	1320	15515	9593	25	10010	10	10000	10	10000	50	729019	1	49	12398	15529	15536	14113	3	14264	10010	20	10000	20	10000	15451	15476	1	1	10021	10	9	2722	10	10	10	22295	22233	32280	0	24031	22205	10000	644	8	16	8	8	15441	10000	10	15548	15475	15532	15602	15624
10024	15609	117	292	148	293	24008	1343	15551	9563	25	10010	10	10000	10	10000	50	731254	1	49	12445	15554	15579	14147	3	14261	10010	20	10000	20	10000	15453	15523	1	1	10021	10	9	2719	10	10	10	22245	22287	32271	0	24003	22217	10000	644	8	16	6	11	15463	10000	10	15546	15639	15640	15617	15628
10024	15574	117	292	146	296	23899	1344	15486	9539	25	10010	10	10000	10	10000	50	723327	1	49	12480	15533	15473	14106	3	14414	10010	20	10000	20	10000	15535	15510	1	1	10021	10	9	2753	10	10	10	22235	22265	32240	0	23956	22269	10000	644	11	16	10	5	15418	10000	10	15511	15457	15583	15522	15387
10024	15617	117	295	147	295	24005	1366	15563	9713	25	10010	10	10000	10	10000	50	729176	1	49	12499	15436	15531	14132	3	14258	10010	20	10000	20	10000	15503	15525	1	1	10021	10	9	2668	10	10	10	22208	22316	32226	0	24026	22333	10000	644	10	16	10	10	15460	10000	10	15568	15502	15571	15549	15503
10024	15474	116	296	147	293	24008	1353	15520	9632	25	10010	10	10000	10	10000	50	728528	1	49	12597	15512	15563	14150	3	14192	10010	20	10000	20	10000	15474	15451	1	1	10021	10	9	2737	10	10	10	22273	22193	32222	0	24045	22336	10000	644	5	16	11	11	15372	10000	10	15571	15500	15453	15514	15480
10024	15587	117	290	145	293	23991	1355	15541	9551	25	10010	10	10000	10	10000	50	726169	1	49	12502	15513	15534	14155	3	14187	10010	20	10000	20	10000	15443	15412	1	1	10021	10	9	2638	10	10	10	22240	22219	32250	0	23970	22279	10000	644	10	16	10	10	15559	10000	10	15512	15525	15558	15507	15674

PRFM (register, PSTL1STRM)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations