Firestorm: LDRSH (64-bit) measurements

Code:

  ldrsh x0, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	403	2	1	1	0	0	0	0	379	0	12	12	16	25	1000	1000	1000	15018	1	397	394	217	3	252	1000	1000	1000	394	77	1	1	1001	1000	1000	0	1000	0	1039	0	0	1039	6	1	0	0	73	1	16	1	1	391	10	10	0	1000	375	395	395	395	395
1004	394	2	0	0	45	1	0	1	359	0	12	0	16	25	1000	1000	1000	14060	1	394	394	197	3	252	1000	1000	1000	374	77	1	1	1001	1000	1000	1	1000	0	1000	0	0	1039	6	1	0	0	73	1	16	1	1	395	10	0	4	1000	395	401	375	375	399
1004	398	3	0	0	44	0	0	0	379	2	0	1	0	25	1000	1000	1000	15208	1	379	374	198	3	232	1000	1000	1000	374	77	1	1	1001	1000	1000	0	1000	43	1039	0	38	1039	6	0	0	44	73	1	16	1	1	371	14	14	0	1000	399	399	399	375	399
1004	374	2	0	0	44	1	0	1	383	2	12	1	19	25	1000	1000	1000	15018	1	398	398	197	3	256	1000	1000	1000	398	56	1	1	1001	1000	1000	0	1000	43	1038	0	41	1038	6	1	38	44	73	1	16	1	1	395	0	0	4	1000	399	395	395	375	399
1004	398	3	0	0	44	1	0	0	383	2	1	1	0	25	1000	1000	1000	14060	1	398	374	197	3	232	1000	1000	1000	394	77	1	1	1001	1000	1000	0	1000	43	1038	0	38	1039	6	1	39	43	73	1	16	1	1	391	14	10	0	1000	395	375	399	375	375
1004	398	3	0	0	44	0	0	1	359	2	0	0	0	25	1000	1000	1000	15274	1	374	398	221	3	256	1000	1000	1000	374	56	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	6	0	39	44	73	1	16	1	1	391	14	14	0	1000	395	399	399	399	399
1004	394	3	1	1	44	0	0	1	383	2	0	12	19	25	1000	1000	1000	15274	1	374	398	221	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	44	1038	0	38	1038	0	1	39	43	73	1	16	1	1	395	0	0	7	1000	399	375	375	399	375
1004	374	3	0	0	0	1	0	0	383	2	1	12	0	25	1000	1000	1000	15267	1	398	398	221	3	256	1000	1000	1000	394	77	1	1	1001	1000	1000	0	1000	43	1000	0	38	1000	6	1	38	44	73	1	16	1	1	395	14	10	0	1000	399	399	399	375	399
1004	374	3	1	0	0	0	0	1	379	2	1	12	19	25	1000	1000	1000	14060	1	398	395	197	3	232	1000	1000	1000	394	56	1	1	1001	1000	1000	0	1000	0	1039	1	38	1000	0	0	39	0	73	1	16	1	1	395	10	0	0	1000	399	399	399	395	375
1004	398	3	0	1	0	0	0	1	383	2	0	0	0	25	1000	1000	1000	14060	1	374	394	197	3	232	1000	1000	1000	398	77	1	1	1001	1000	1000	1	1000	0	1038	0	38	1038	6	1	39	44	73	1	16	1	1	371	14	14	7	1000	375	399	399	399	399

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh x0, [x6]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70047	524	0	1	1	0	0	70035	69781	59709	25	40104	30103	10001	30100	10000	616175	3342206	1	49	66967	70050	70035	64646	3	64938	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	0	1	0	0	0	2610	2	71	1	1	69798	30003	6	6	0	10000	30100	70051	70051	70051	70051	70051
40204	70050	524	0	0	1	0	0	70032	69735	59695	25	40100	30100	10000	30245	10000	618383	3342770	1	49	66970	70035	70050	64643	3	64938	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	0	0	0	0	0	0	2610	1	71	1	1	69813	30003	9	9	9	10000	30100	70051	70051	70036	70051	70051
40204	70035	524	0	0	1	0	0	70035	69781	59706	25	40104	30103	10000	30100	10000	616015	3342062	1	49	66970	70050	70050	64646	3	64953	40100	30200	10218	60200	10000	70037	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10003	1	0	1	0	0	0	2610	1	71	1	1	69810	30000	0	0	0	10000	30100	70051	70036	70051	70051	70036
40204	70035	524	0	0	1	1	0	70035	69735	59709	25	40104	30100	10001	30100	10000	616005	3342062	1	49	66970	70050	70050	64631	3	64954	40100	30200	10000	60200	10000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69813	30003	6	0	9	10000	30100	70036	70051	70036	70051	70051
40204	70035	525	1	0	1	0	0	70035	69735	59695	25	40104	30100	10001	30100	10000	616015	3341470	1	49	66970	70050	70035	64631	3	64950	40100	30200	10000	60200	10000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	0	1	1	0	0	0	2610	1	71	1	1	69813	30000	9	0	0	10000	30100	70051	70051	70048	70051	70051
40204	70035	525	0	0	1	1	0	70026	69764	59695	25	40100	30103	10001	30100	10000	616175	3342206	1	49	63906	70050	70050	64646	3	64938	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	0	0	0	0	0	0	2610	1	71	1	1	69810	30003	6	9	0	10000	30100	70048	70051	70036	70051	70051
40204	70050	524	0	0	61	1	0	70035	69781	59695	25	40104	30100	10001	30100	10000	616005	3342206	1	49	66955	70035	70050	64631	3	64938	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69798	30003	0	9	9	10000	30100	70036	70051	70036	70036	70036
40204	70035	524	0	0	0	1	0	70020	69764	59709	25	40104	30100	10001	30100	10000	616175	3342206	1	49	66970	70035	70035	64646	3	64953	40100	30200	10216	60200	10000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10003	1	10000	0	2336	10000	1	0	1	0	0	0	2610	1	71	1	1	69813	30003	9	9	9	10000	30100	70048	70051	70036	70096	70036
40204	70047	524	0	0	1	1	0	70020	69764	59709	25	40104	30114	10001	30100	10000	616041	3342206	1	49	66970	70050	70050	64643	3	64938	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	3	10000	1	0	1	0	0	0	2610	1	71	1	1	69813	30003	0	9	6	10000	30100	70056	70056	70051	70036	70051
40204	70050	525	0	0	0	0	0	70020	69786	59709	25	40108	30100	10001	30100	10000	616175	3342206	1	49	66970	70050	70050	64631	3	64953	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	3	10000	0	0	0	0	0	0	2610	1	71	1	1	69798	30003	6	0	9	10000	30100	70051	70036	70051	70048	70051

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d2	d5	map dispatch bubble (d6)	d9	da	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	524	0	0	1	0	0	1	0	1	0	0	0	0	70035	69760	59834	25	40018	30016	10002	30010	10000	616982	3341470	49	66955	70035	70035	64668	3	64978	40010	30020	10000	60020	10000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	1	1	1	2520	0	3	71	0	0	3	3	69814	30003	0	6	18	10000	30010	70051	70036	70036	70082	70084
40024	70035	525	0	0	0	0	0	0	0	1	1	0	0	0	70035	69743	59796	25	40014	30013	10000	30010	10000	616982	3342206	49	66970	70050	70050	64668	20	64960	40010	30020	10000	60020	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10002	0	0	1	10000	1	1	1	1	1	2520	0	5	71	0	0	4	2	69816	30006	9	9	0	10000	30010	70042	70057	70062	70057	70055
40024	70056	525	1	0	1	1	0	0	0	1	0	0	0	0	70041	69702	59796	25	40014	30013	10000	30010	10000	616982	3341470	49	66970	70050	70050	64653	3	64975	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	2520	0	6	71	0	0	6	3	69798	30003	9	6	0	10000	30010	70052	70050	70051	70398	70048
40024	70050	525	0	0	0	0	0	0	0	1	0	0	0	0	70211	69728	59709	25	40010	30049	10001	30010	10000	617086	3342206	49	66955	70047	70047	64653	3	64960	40010	30020	10000	60020	10000	70047	35	3	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10002	0	1	1	10000	1	1	1	1	2	2520	0	3	151	0	0	2	3	69819	30003	9	9	9	10000	30010	70042	70042	70057	70130	70036
40024	70035	524	0	0	0	0	0	0	0	16	1	0	0	0	70020	69760	59794	25	40014	30010	10000	30010	10000	617068	3342206	49	66967	70050	70035	64668	3	64975	40010	30020	10000	60020	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	67	0	3	10003	1	0	1	0	0	2520	0	3	71	0	0	3	3	69844	30000	9	6	9	10000	30010	70036	70051	70051	70054	70061
40024	70056	525	1	0	0	1	0	0	0	13	0	0	0	0	70038	69777	59706	25	40014	30010	10001	30010	10000	616970	3342206	49	66955	70050	70050	64653	3	64980	40010	30020	10000	60020	10000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	1	0	2230	10003	1	0	1	0	0	2520	0	3	71	0	0	6	5	69813	30012	9	0	9	10000	30010	70151	70036	70240	70127	70036
40024	70050	525	0	0	0	0	0	0	0	12	0	0	0	0	70032	69708	59706	25	40014	30013	10001	30010	10000	616979	3342062	49	66970	70035	70035	64669	3	64960	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	3	0	3	10000	1	0	1	0	0	2520	0	3	71	0	0	5	6	69801	30000	9	6	9	10000	30010	70036	70054	70051	70144	70054
40024	70053	525	1	0	0	1	0	0	0	557	1	0	0	1	70043	69705	59748	25	40014	30013	10001	30010	10000	616982	3341470	49	66955	70050	70047	64668	3	64960	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	2520	0	5	71	0	0	6	5	69813	30003	9	0	6	10000	30010	70036	70060	70057	70073	70046
40024	70056	525	1	0	1	0	0	0	0	2	1	0	0	0	70026	69702	59792	122	40014	30010	10001	30010	10000	616982	3342206	49	66955	70050	70050	64668	3	64975	40010	30020	10000	60020	10056	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	0	0	1	0	0	2520	0	6	71	0	0	3	7	69798	30009	6	6	9	10000	30010	70051	70036	70051	70048	70036
40024	70050	525	0	0	0	0	1	1	0	1	1	0	0	0	70032	69760	59782	25	40018	30016	10001	30010	10000	616995	3342494	49	66976	70056	70056	64674	3	64981	40010	30020	10000	60020	10000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10002	0	1	1	10000	0	1	0	1	1	2520	0	7	71	0	0	6	6	69819	30006	9	9	9	10000	30010	70057	70057	70057	70057	70042

Test 3: throughput

Count: 8

Code:

  ldrsh x0, [x6]
  ldrsh x0, [x6]
  ldrsh x0, [x6]
  ldrsh x0, [x6]
  ldrsh x0, [x6]
  ldrsh x0, [x6]
  ldrsh x0, [x6]
  ldrsh x0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26728	200	0	0	0	0	0	0	0	1	0	0	26712	0	12	12	16	25	80100	100	80000	100	80015	500	1167303	1	49	23647	26727	26727	16635	6	16679	80116	200	80024	200	80024	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	0	80039	0	0	39	80039	6	1	39	43	0	1	1	1	5118	1	16	1	1	26729	0	10	10	4	80000	100	26728	26708	26728	26728	26728
80204	26727	200	0	1	1	0	0	69	0	0	0	1	26712	0	12	12	0	25	80100	100	80000	100	80015	500	1177116	1	49	23647	26727	26727	16655	6	16679	80115	200	80024	200	80024	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	0	80039	0	0	39	80039	0	0	39	43	0	1	1	1	5118	1	16	1	1	26725	0	0	10	4	80000	100	26728	26728	26728	26708	26728
80204	26707	200	0	0	0	0	0	45	0	0	0	0	26712	2	12	12	16	25	80100	100	80000	100	80015	500	1167303	1	49	23647	26727	26727	16655	6	16679	80114	200	80024	200	80024	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	0	80039	0	0	0	80000	6	1	39	43	0	1	1	1	5118	1	16	1	1	26739	0	10	10	4	80000	100	26731	26728	26728	26728	26728
80204	26727	200	0	0	0	0	0	45	0	0	0	1	26712	2	0	0	16	25	80100	100	80000	100	80015	500	1167303	1	49	23647	26727	26727	16655	6	16679	80115	200	80024	200	80024	26707	59	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	0	80039	0	0	42	80039	6	1	39	0	0	1	1	1	5118	1	16	1	1	26730	0	10	10	4	80000	100	26728	26708	26728	26708	26708
80204	26727	200	0	0	0	0	0	45	0	1	0	1	26724	2	12	12	0	25	80100	100	80000	100	80016	500	1165952	1	49	24220	26738	26727	16655	6	16681	80115	200	80024	200	80024	26729	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	0	80039	0	0	39	80000	6	1	40	43	0	1	1	1	5118	1	16	1	1	26724	0	10	10	0	80000	100	26752	26744	26730	26728	26730
80204	26732	200	0	0	0	0	0	51	0	1	0	1	26712	2	12	12	16	35	80100	100	80000	100	80014	500	1167560	1	49	23627	26727	26727	16666	6	16721	80115	200	80024	200	80024	26739	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	0	80039	0	0	39	80039	6	1	39	43	0	1	1	1	5141	1	16	1	1	26724	0	10	0	4	80000	100	26728	26821	26728	26728	26708
80204	26727	200	0	0	0	0	0	45	0	1	0	1	26712	2	0	12	16	25	80100	100	80000	100	80014	500	1167303	1	49	23647	26727	26817	16673	6	16679	80115	200	80024	200	80024	26789	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	0	80039	0	0	39	80039	6	0	39	0	0	1	1	1	5118	1	16	1	1	26719	0	10	10	0	80000	100	26708	26728	26737	26708	26711
80204	26727	200	0	0	0	0	0	45	0	0	0	1	26692	2	0	0	16	25	80100	100	80000	100	80015	500	1167303	1	49	23627	26859	27026	16655	6	16893	80115	200	80024	200	80024	26727	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	0	80039	1	0	0	80039	6	1	39	43	0	1	1	1	5118	1	16	1	1	26732	0	10	10	4	80000	100	26731	27631	27460	27626	26887
80204	26731	200	0	0	0	5	5	708	440	1	0	1	27662	0	0	0	300	167	80882	104	80780	101	81268	522	1203837	1	49	24674	27628	27734	17356	58	17383	81190	204	81375	208	81185	27759	56	8	1	80201	100	99	100	80000	100	80000	0	100	81042	4	0	191	80951	1	0	4782	80819	6	1	39	43	0	1	1	1	5142	1	16	1	1	26710	0	10	10	4	80000	100	26728	26708	26728	26728	27727
80204	27580	204	0	1	0	0	0	327	0	0	0	1	27460	0	12	12	16	173	80884	102	80780	104	81082	500	1199626	1	49	24649	27620	27737	17331	51	17384	81369	206	81374	204	81185	27751	77	8	1	80201	100	99	100	80000	100	80000	1	100	80782	2	43	239	80760	1	2	5568	80949	0	1	39	43	4	0	0	0	5267	2	64	2	2	27535	2	10	10	0	80000	100	27625	27637	27031	27178	27733

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	d9	da	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26736	200	1	1	0	1	0	0	0	0	67	0	1	0	3	26721	2	7	9	19	25	80010	10	80000	10	80000	50	1173916	0	49	23634	26736	26715	16682	3	16688	80010	20	80000	20	80000	26714	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	19	43	0	80018	1	0	2	61	80040	6	1	59	0	19	0	0	5020	5	16	0	0	3	6	26733	13	0	5	80000	10	26737	26737	26716	26715	26737
80024	26736	200	1	0	1	0	0	0	0	0	67	0	1	0	2	26721	3	7	0	19	25	80010	10	80000	10	80000	50	1166780	0	49	23656	26736	26737	16681	3	16716	80010	20	80000	20	80000	26715	85	1	1	80021	10	9	0	10	80000	10	80000	1	10	80019	20	43	0	80058	0	0	2	64	80040	6	1	59	45	19	1	0	5020	5	16	0	0	4	5	26734	0	13	5	80000	10	26738	26738	26715	26737	26738
80024	26714	201	1	0	0	0	0	0	0	0	21	0	1	0	3	26721	3	7	0	0	25	80010	10	80000	10	80000	50	1168394	0	49	23657	26736	26736	16681	3	16694	80010	20	80000	20	80000	26714	86	1	1	80021	10	9	1	10	80000	10	80000	0	10	80020	20	43	0	80058	1	0	1	21	80039	6	0	58	45	19	1	0	5020	5	16	0	0	3	5	26734	0	0	0	80000	10	26715	26737	26738	26716	26737
80024	26716	201	1	1	1	1	0	0	0	0	21	0	0	0	2	26721	0	7	7	20	25	80010	10	80000	10	80198	50	1173790	0	49	23635	26736	26736	16660	3	16695	80010	20	80000	20	80000	26714	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	19	0	0	80059	2	0	0	21	80040	6	0	19	0	19	1	0	5020	6	16	0	0	5	3	26733	13	13	5	80000	10	26738	26715	26715	26737	26738
80024	26738	200	1	1	0	1	0	0	0	0	21	0	0	0	0	26700	0	7	7	20	25	80010	10	80000	10	80000	50	1168221	0	49	23634	26715	26737	16681	3	16694	80010	20	80000	20	80000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80149	19	0	0	80059	1	0	1	60	80040	6	0	19	43	19	0	0	5020	5	16	0	0	5	3	26733	0	13	0	80000	10	26716	26716	26737	26738	26737
80024	26736	200	1	0	1	0	0	0	0	0	66	0	0	0	1	26721	0	7	7	4	25	80010	10	80000	10	80000	50	1176880	0	49	23657	26736	26737	16681	3	16716	80010	20	80000	20	80000	26739	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	19	44	0	80058	0	0	1	61	80039	6	0	19	43	19	0	0	5020	5	16	0	0	5	3	26733	0	13	5	80000	10	26737	26715	26737	26737	26738
80024	26719	200	1	1	1	0	0	0	0	0	21	0	1	0	3	26699	0	0	7	19	25	80010	10	80000	10	80000	50	1171747	1	49	23635	26736	26736	16775	3	16694	80010	20	80000	20	80000	26736	85	1	1	80021	10	9	1	10	80000	10	80000	0	10	80019	20	0	0	80059	0	0	2	61	80040	6	1	59	43	19	1	0	5020	3	16	0	0	5	3	26712	0	13	5	80000	10	26737	26737	26716	26738	26737
80024	26813	200	1	0	0	1	0	0	0	0	21	0	0	0	3	26721	3	0	7	1	25	80010	10	80000	10	80000	50	1169839	0	49	23702	26736	26736	16681	3	16723	80010	20	80000	20	80000	26881	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80152	21	0	0	80019	2	53	2	66	80040	6	1	59	0	19	1	0	5020	3	16	0	0	3	5	26734	13	13	5	80000	10	26724	26737	26737	26716	26738
80024	26715	200	1	0	1	0	0	0	0	0	21	0	0	0	3	26721	3	7	7	22	25	80010	10	80000	10	80000	50	1167149	0	49	23634	26715	26737	16681	3	16694	80010	20	80000	20	80000	26737	64	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	19	43	0	80019	1	0	2	61	80040	6	1	19	0	19	1	0	5020	3	16	0	0	5	3	26733	0	13	0	80000	10	26716	26716	26737	26738	26738
80024	26747	200	1	1	0	0	1	0	0	0	21	0	1	0	2	26721	3	0	0	19	25	80010	10	80000	10	80000	50	1146275	0	49	23656	26717	26714	16681	3	16695	80010	20	80000	20	80000	26737	64	1	1	80021	10	9	0	10	80000	10	80000	1	10	80019	20	43	0	80060	0	0	2	21	80040	0	1	58	0	19	0	0	5020	4	16	0	0	4	5	26712	13	13	5	80000	10	26738	26716	26738	26738	26737

LDRSH (64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations