Firestorm: LDRSW (register, uxtw) measurements

Code:

  ldrsw x0, [x6, w7, uxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	399	3	0	0	45	0	0	2	379	2	12	12	16	25	1000	1000	1000	15037	1	394	394	217	3	252	1000	1000	2000	395	71	1	1	1001	1000	1000	1000	39	1039	0	35	1040	6	1	35	43	73	3	16	2	2	391	10	6	4	1000	395	395	395	395	395
1004	394	3	0	0	45	0	0	1	379	2	12	12	16	25	1000	1000	1000	15037	1	394	394	217	3	252	1000	1000	2000	399	71	1	1	1001	1000	1000	1000	39	1035	0	39	1040	6	1	35	43	73	2	16	2	2	391	10	10	4	1000	397	395	395	395	395
1004	389	3	0	0	41	0	0	2	379	2	12	12	16	25	1000	1000	1000	14989	1	394	394	217	3	252	1000	1000	2000	400	71	1	1	1001	1000	1000	1000	39	1039	0	39	1039	6	1	35	43	73	2	16	2	2	391	10	6	4	1000	395	395	398	395	395
1004	394	2	0	0	45	0	0	2	379	2	12	12	12	25	1000	1000	1000	15018	1	389	394	217	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	1000	39	1039	0	35	1039	6	1	35	39	73	2	16	2	2	391	10	10	4	1000	395	395	395	395	395
1004	391	2	0	0	45	0	0	2	379	2	12	12	16	25	1000	1000	1000	15037	1	394	394	217	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	1000	39	1039	0	39	1035	6	1	35	43	73	2	16	2	2	388	10	6	4	1000	395	395	390	395	395
1004	389	3	0	0	45	0	0	2	379	2	12	12	16	25	1000	1000	1000	15037	1	394	394	216	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	1000	39	1039	0	39	1035	6	1	35	43	73	2	16	2	2	391	10	10	4	1000	395	395	392	390	395
1004	394	3	0	0	41	0	0	2	379	2	12	12	16	25	1000	1000	1000	14989	1	394	394	217	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	1000	39	1035	0	39	1039	6	1	35	39	73	3	16	2	2	391	10	10	4	1000	395	395	394	395	395
1004	394	2	0	0	45	0	0	2	379	2	12	12	16	25	1000	1000	1000	14989	1	397	394	217	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	1000	39	1039	0	35	1035	6	1	35	43	73	2	16	2	2	386	10	10	2	1000	395	395	395	395	395
1004	394	3	0	0	45	0	0	1	379	2	12	12	16	25	1000	1000	1000	15037	1	394	389	217	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	1000	39	1039	0	39	1039	6	1	35	43	73	2	16	2	2	391	10	6	2	1000	390	392	395	395	395
1004	394	3	0	0	45	0	0	2	379	2	12	12	16	25	1000	1000	1000	15037	1	394	394	216	3	247	1000	1000	2000	394	71	1	1	1001	1000	1000	1000	39	1039	0	39	1039	6	1	35	43	73	2	16	2	2	386	10	6	4	1000	390	395	395	395	395

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsw x0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70051	524	0	1	0	1	1	0	0	6	0	1	0	0	70036	69782	59713	25	40104	30103	10001	30100	10000	616014	3342254	1	49	66971	70051	70051	64647	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	2610	1	71	1	1	69837	30006	10	10	10	10000	30100	70052	70052	70052	70052	70052
40204	70051	525	0	0	0	0	0	0	0	1	0	1	0	0	70036	69782	59710	25	40104	30103	10000	30100	10000	616014	3342254	1	49	66971	70051	70051	64647	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70052	70052	70052	70052	70052
40204	70051	524	0	0	0	0	0	0	0	1	0	1	0	0	70020	69782	59710	25	40104	30103	10001	30100	10000	616014	3341470	0	49	66971	70051	70051	64647	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70052	70052	70036	70052	70052
40204	70051	525	0	0	0	0	0	0	0	1	0	1	0	0	70036	69782	59695	25	40104	30103	10001	30100	10000	616014	3342254	1	49	65821	70059	70051	64647	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	0	0	2610	1	71	1	1	69917	30003	10	10	10	10000	30100	70052	70052	70052	70079	70052
40204	70051	524	0	0	0	0	0	0	0	1	0	0	0	0	70020	69782	59710	25	40104	30103	10001	30100	10000	616014	3342254	1	49	66971	70051	70051	64647	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	2610	1	71	1	1	69814	30000	10	10	10	10000	30100	70052	70052	70052	70052	70036
40204	70051	524	0	0	0	0	0	0	0	1	0	1	0	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616014	3342254	0	49	66971	70051	70051	64647	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70052	70052	70052	70052	70055
40204	70051	525	0	0	0	0	0	0	0	1	0	1	0	0	70036	69800	59715	25	40104	30103	10001	30100	10000	616014	3342254	0	49	66955	70051	70035	64647	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70052	70052	70052	70052	70052
40204	70035	525	0	0	0	0	0	0	0	1	0	0	0	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616014	3342254	0	49	66971	70051	70051	64647	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	10000	1	0	0	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70052	70052	70052	70052	70052
40204	70051	525	0	0	0	0	0	0	0	1	0	1	0	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616014	3342254	1	49	66971	70051	70035	64647	3	64954	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70052	70052	70052	70052	70052
40204	70051	524	0	0	0	0	0	0	0	1	0	1	0	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616014	3342254	1	49	66971	70051	70051	64647	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	0	10000	0	0	0	10000	1	1	0	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70036	70052	70052	70052	70052

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70055	524	1	1	1	0	1	0	0	0	1	0	1	0	0	1	70038	69777	59701	25	40018	30016	10002	30010	10000	616952	3342062	1	49	66967	70047	70047	64665	0	21	64978	40010	30020	10000	61004	20000	70049	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	1	10001	0	2	1	10000	1	0	1	0	0	0	0	2520	0	1	71	0	1	1	69798	30003	6	6	6	10000	30010	70048	70051	70048	70048	70048
40024	70035	525	0	0	0	0	0	0	0	0	6	0	1	0	0	1	70038	69777	59712	25	40014	30013	10001	30010	10000	616952	3342062	0	49	66967	70035	70035	64665	0	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	1	0	0	10000	1	0	1	0	0	0	0	2520	0	1	71	0	1	1	69810	30000	6	0	6	10000	30010	70048	70048	70048	70048	70048
40024	70047	524	0	0	0	0	1	1	0	0	6	0	0	0	0	1	70026	69777	59715	25	40018	30016	10001	30010	10000	617009	3342350	1	49	66973	70053	70053	64671	0	3	64966	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	2520	3	1	71	0	1	1	69804	30006	6	0	6	10000	30010	70054	70054	70054	70054	70054
40024	70041	525	1	1	1	1	0	0	0	0	2	0	1	0	0	0	70032	69728	59706	25	40014	30013	10000	30010	10000	616952	3341470	1	49	66967	70047	70035	64665	0	3	64972	40010	30020	10000	60020	20000	70115	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	1	10002	0	3	1	10006	1	1	0	1	1	0	0	2520	3	1	71	0	1	1	69798	30003	6	6	6	10000	30010	70048	70048	70048	70050	70048
40024	70047	525	0	0	1	1	0	0	0	0	2	0	1	0	0	0	70032	69728	59706	25	40014	30013	10001	30010	10000	616952	3341470	0	49	66967	70047	70047	64665	0	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	1	0	2520	0	2	71	0	1	1	69816	30006	6	6	6	10000	30010	70054	70054	70054	70054	70054
40024	70053	525	1	1	0	0	0	0	0	0	1	0	1	0	0	0	70032	69728	59706	25	40010	30013	10001	30010	10000	616952	3342062	0	49	66955	70047	70035	64665	0	3	64972	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	1	0	0	10003	1	0	1	0	0	0	0	2520	0	1	71	0	1	1	69810	30003	6	6	0	10000	30010	70036	70048	70048	70048	70048
40024	70035	525	0	0	0	0	0	0	0	0	1	0	1	0	0	0	70026	69777	59701	25	40014	30016	10002	30010	10000	617009	3342350	0	49	66961	70053	70053	64671	0	3	64978	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	1	0	0	10000	1	0	1	0	0	0	0	2520	0	2	71	1	1	1	69810	30012	0	6	0	10000	30010	70313	70140	70048	70049	70036
40024	70035	524	0	0	0	0	0	0	0	0	1	0	0	0	0	0	70032	69728	59706	25	40010	30013	10001	30010	10000	616952	3341470	0	49	66967	70047	70035	64665	0	3	64960	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	0	10001	0	0	1	10000	1	1	1	1	1	0	0	2520	0	1	71	0	1	1	69798	30003	6	6	6	10000	30010	70036	70048	70036	70048	70036
40024	70047	524	0	0	0	0	0	0	0	0	6	0	0	0	0	1	70026	69777	59712	25	40018	30016	10002	30010	10000	617009	3341769	0	49	66973	70041	70053	64671	0	3	64978	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	2520	3	1	71	0	1	1	69810	30003	6	6	6	10000	30010	70048	70036	70048	70036	70048
40024	70047	524	0	0	0	0	0	0	0	0	1	0	1	0	0	0	70020	69728	59706	25	40014	30013	10001	30010	10000	617068	3342062	0	49	66967	70047	70047	64653	0	3	64972	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	1	10001	0	0	4	10000	1	1	1	1	1	0	0	2520	0	2	71	0	1	1	69798	30003	0	0	6	10000	30010	70048	70036	70048	70048	70048

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsw x0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0057

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70051	525	1	1	0	0	0	0	0	2	0	0	0	1	70042	69788	59716	25	40108	30106	10002	30100	10000	616068	3341769	1	49	66977	70057	70057	64653	0	3	64960	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	3	1	10002	0	0	0	1	10000	1	1	1	1	1	0	2610	1	71	1	1	69820	30006	13	10	13	10000	30100	70058	70058	70058	70058	70058
40204	70057	524	1	1	1	1	1	0	0	2	0	1	0	1	70042	69788	59716	25	40108	30106	10002	30100	10000	616068	3342542	0	49	66977	70057	70057	64653	7	3	64964	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	1	10001	0	0	3	1	10000	1	1	1	1	0	0	2610	1	71	1	1	69820	30006	10	10	10	10000	30100	70042	70058	70058	70042	70058
40204	70057	524	1	0	1	0	0	0	0	2	0	0	0	1	70042	69788	59716	25	40108	30106	10002	30100	10051	617522	3342542	1	49	66977	70112	70057	64691	0	12	64966	40100	30526	10109	60200	20000	70108	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10001	0	0	1	1	10000	1	1	1	1	1	0	2635	1	72	1	1	70010	30006	10	10	10	10000	30100	70058	70058	70058	70058	70058
40204	70057	524	1	0	0	0	0	0	0	14	0	1	0	1	70045	69788	59716	25	40104	30103	10002	30100	10000	616068	3342542	1	49	66961	70057	70057	64653	0	3	64944	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10001	0	0	0	4	10000	1	1	1	1	1	0	2610	1	71	1	1	69820	30006	10	0	10	10000	30100	70093	70058	70058	70058	70058
40204	70063	525	1	0	2	0	0	1	1	284	192	1	0	2	70042	69788	59701	25	40108	30106	10002	30100	10000	616068	3341769	0	49	66961	70057	70059	64653	0	3	64947	40100	30200	10000	60200	20000	70059	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	3	1	10002	0	1	2	1	10000	1	1	1	1	1	0	2610	1	71	1	1	69820	30006	10	10	10	10000	30100	70058	70058	70058	70058	70061
40204	70057	525	1	1	1	0	0	0	0	14	0	1	0	0	70042	69788	59716	25	40108	30106	10002	30100	10000	618343	3342542	1	49	66981	70057	70137	64653	0	3	64946	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10003	2	1	10002	0	0	2	1	10000	1	1	1	1	1	0	2610	1	71	1	1	69820	30006	10	10	10	10000	30100	70058	70042	70058	70042	70042
40204	70057	525	1	0	1	0	0	0	0	2	0	1	0	1	70042	69788	59716	25	40108	30106	10002	30100	10000	616068	3341769	1	49	66977	70057	70057	64653	0	3	64960	40100	30200	10000	60200	20000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10001	0	0	2	1	10000	1	1	1	1	1	0	2610	1	71	1	1	70082	30006	10	10	0	10000	30100	70058	70058	70058	70100	70058
40204	70057	525	1	1	1	0	0	0	0	2	0	1	0	1	70042	69788	59716	25	40104	30106	10002	30100	10000	616068	3342542	1	49	66961	70057	70057	64653	0	3	64947	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10002	0	0	0	4	10000	1	1	1	1	0	0	2610	1	71	1	1	69917	30006	10	10	10	10000	30100	70058	70058	70058	70058	70058
40204	70057	525	1	1	0	0	0	0	0	2	0	0	0	1	70026	69788	59716	25	40108	30106	10002	30100	10000	616068	3342542	1	49	66977	70057	70057	64653	0	3	64960	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10002	0	0	1	1	10000	1	1	1	1	2	0	2610	1	71	1	1	69820	30003	10	0	0	10000	30100	70042	70101	70058	70058	70058
40204	70057	524	1	1	1	0	0	0	0	2	0	1	0	1	70042	69702	59716	25	40108	30106	10002	30100	10000	616068	3342542	1	49	66977	70057	70057	64653	0	3	64960	40100	30200	10000	60200	20000	70041	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10001	2	1	10001	0	0	1	1	10000	1	1	1	1	0	0	2610	1	71	1	1	69939	30006	0	10	0	10000	30100	70044	70058	70058	70058	70058

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	0e	0f	18	19	1e	22	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70057	525	0	0	0	0	0	0	1	1	70036	69743	59710	25	40014	30013	10001	30010	10000	617068	3342254	0	49	66971	0	70051	70051	64669	3	65055	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	0	10000	1	1	0	2520	1	71	1	1	69814	30003	10	10	10	10000	30010	70052	70053	70054	70052	70052
40024	70051	524	0	0	0	0	0	0	1	1	70036	69775	59710	25	40014	30013	10004	30155	10000	616991	3341470	1	49	66971	0	70051	70051	64669	3	65011	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	0	10000	1	1	0	2520	1	71	1	1	69814	30000	10	0	10	10000	30010	70052	70052	70052	70036	70052
40024	70035	525	0	0	0	0	0	0	0	1	70036	69775	59695	25	40014	30010	10001	30010	10000	616991	3341470	1	49	66971	0	70035	70051	64669	3	65049	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	0	10000	1	1	0	2520	1	71	1	1	69814	30003	10	10	10	10000	30010	70052	70052	70052	70052	70052
40024	70051	525	0	0	0	1	0	0	6	1	70036	69775	59710	25	40014	30013	10001	30010	10000	616991	3342254	1	49	66971	3	70035	70051	64669	3	65046	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	0	10000	1	1	0	2520	1	71	1	1	69814	30003	10	10	10	10000	30010	70052	70037	70094	70052	70052
40024	70051	525	0	0	0	0	0	0	1	1	70036	69775	59710	25	40010	30013	10001	30010	10000	616991	3341470	0	49	66955	0	70051	70051	64669	3	65008	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	0	10000	1	1	0	2520	1	71	1	1	69814	30000	10	10	10	10000	30010	70052	70052	70052	70052	70052
40024	70051	525	0	0	0	0	0	0	6	1	70036	69775	59710	25	40014	30013	10001	30010	10000	616991	3341470	0	49	66971	0	70051	70051	64669	3	65045	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	0	10000	0	1	0	2520	1	71	2	1	69807	30003	10	10	10	10000	30010	70052	70052	70052	70052	70052
40024	70051	524	0	0	0	0	0	0	111	1	70036	69775	59695	25	40014	30013	10001	30010	10000	616991	3341470	0	49	66971	0	70035	70051	64669	3	64985	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	0	10000	1	0	0	2520	1	71	1	1	69814	30003	10	10	10	10000	30010	70052	70052	70036	70036	70036
40024	70051	524	0	0	0	0	0	0	1	1	70036	69775	59710	25	40014	30013	10001	30010	10000	616991	3341470	1	49	66971	0	70051	70035	64669	3	65013	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	0	10000	1	1	0	2520	1	71	1	2	69814	30003	0	10	10	10000	30010	70052	70052	70052	70052	70052
40024	70051	525	0	0	0	0	0	0	1	1	70036	69775	59710	25	40010	30013	10001	30010	10000	616991	3342254	0	49	66955	0	70035	70051	64669	3	65082	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	0	10000	1	1	0	2555	1	71	1	1	69814	30003	10	10	10	10000	30010	70052	70052	70052	70052	70052
40024	70051	525	0	0	0	0	0	0	0	1	70036	69775	59710	25	40010	30013	10001	30010	10000	616991	3341470	0	49	66971	0	70051	70051	64669	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	0	10000	1	0	0	2520	1	71	1	1	69798	30003	10	10	10	10000	30010	70052	70052	70052	70052	70052

Test 4: throughput

Count: 8

Code:

  ldrsw x0, [x6, w7, uxtw]
  ldrsw x0, [x6, w7, uxtw]
  ldrsw x0, [x6, w7, uxtw]
  ldrsw x0, [x6, w7, uxtw]
  ldrsw x0, [x6, w7, uxtw]
  ldrsw x0, [x6, w7, uxtw]
  ldrsw x0, [x6, w7, uxtw]
  ldrsw x0, [x6, w7, uxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26737	201	1	0	0	1	0	0	0	0	67	0	1	0	3	26726	3	7	7	19	25	80100	100	80000	100	80015	500	1169949	1	49	23656	26736	26736	16664	6	16688	80113	200	80024	200	160048	26737	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80020	21	43	80060	1	0	0	63	80039	6	1	58	43	19	0	1	1	1	5118	1	16	0	26735	13	13	5	80000	100	26737	26737	26737	26737	26737
80204	26736	200	1	1	1	1	0	0	0	0	79	0	1	0	3	26721	2	7	7	19	25	80100	100	80000	100	80013	500	1168510	1	49	23656	26736	26736	16663	6	16689	80116	200	80024	200	160048	26736	86	1	1	80201	100	99	0	100	80000	100	80000	0	100	80019	19	43	80059	1	0	2	60	80041	6	1	59	43	19	1	1	1	1	5118	0	16	0	26734	13	13	5	80000	100	26737	26737	26737	26737	26738
80204	26737	200	1	1	1	1	0	0	0	0	66	0	1	0	2	26725	0	7	7	20	25	80100	100	80000	100	80016	500	1167300	1	49	24259	26749	26739	16664	6	16688	80115	200	80024	200	160048	26736	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80020	19	43	80059	0	3	1	61	80040	6	1	58	43	19	1	1	1	1	5118	0	16	0	26740	13	13	5	80000	100	26737	26737	26737	26737	26738
80204	26737	200	1	0	0	1	0	0	0	0	21	0	1	0	3	26721	0	7	7	18	25	80100	100	80000	100	80012	500	1167377	1	49	23656	26736	26736	16663	6	16688	80113	200	80024	200	160048	26736	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80020	19	43	80058	0	0	1	61	80040	6	1	59	43	19	1	1	1	1	5118	0	16	0	26733	13	13	5	80000	100	26737	26737	26738	26738	26909
80204	26736	200	1	1	1	1	0	0	0	0	67	0	1	0	3	26726	3	7	7	19	25	80100	100	80000	100	80015	500	1168754	1	49	23656	26737	26736	16664	6	16688	80113	200	80024	200	160048	26737	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80021	20	43	80058	0	0	1	63	80040	6	1	58	43	19	1	1	1	1	5118	0	16	0	26733	13	13	5	80000	100	26737	26737	26715	26737	26737
80204	26736	200	1	1	0	1	0	0	0	0	67	0	1	0	2	26725	2	7	9	28	123	80100	100	80000	100	80015	500	1169949	1	49	23656	26737	26736	16664	6	16688	80113	200	80024	200	160048	26737	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80020	20	43	80059	1	0	0	61	80040	6	1	59	43	19	0	1	1	1	5118	0	16	0	26734	13	13	5	80000	100	26737	26737	26737	26738	26737
80204	26737	200	1	1	1	1	0	0	0	0	66	0	1	0	3	26739	2	7	7	19	25	80100	100	80000	100	80013	500	1172493	1	49	23656	26736	26736	16663	6	16689	80116	200	80024	200	160048	26736	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80019	19	43	80191	2	0	0	61	80039	6	1	58	43	19	0	1	1	1	5118	0	16	0	26734	13	13	5	80000	100	26737	26737	26737	26715	26738
80204	26737	200	1	0	1	1	0	0	0	0	66	0	1	0	3	26726	2	7	7	19	25	80100	100	80000	100	80015	500	1169949	1	49	23656	26736	26736	16664	6	16688	80116	200	80024	200	160048	26736	86	1	1	80201	100	99	0	100	80000	100	80000	0	100	80019	20	43	80059	0	0	0	61	80040	6	1	59	43	19	0	1	1	1	5118	0	16	0	26734	13	0	5	80000	100	26741	26741	26741	26745	26737
80204	26736	200	1	0	1	0	0	0	0	0	66	0	1	0	1	26729	2	7	7	19	25	80100	100	80000	100	80015	500	1166171	1	49	23657	26736	26736	16664	6	16688	80115	200	80024	200	160048	26736	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80020	20	43	80059	1	0	1	60	80042	6	1	59	43	19	0	1	1	1	5118	0	16	0	26733	13	13	5	80000	100	26737	26744	26737	26737	26738
80204	26737	200	1	1	0	0	0	0	0	0	67	0	0	0	2	26730	0	7	7	22	25	80100	100	80000	100	80014	500	1167655	1	49	23656	26739	26737	16664	6	16688	80115	200	80224	200	160048	26736	85	1	1	80201	100	99	0	100	80000	100	80000	1	100	80019	19	43	80059	0	0	0	61	80040	6	1	59	43	19	1	1	1	1	5118	0	16	0	26734	13	13	5	80000	100	26737	26737	26741	26737	26737

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26736	200	1	0	1	1	0	1	1	0	0	67	0	1	0	2	26721	3	7	0	20	25	80010	10	80000	10	80000	50	1167584	0	0	49	23635	26737	26736	16659	3	16716	80010	20	80000	20	160000	26715	64	1	1	80021	10	9	10	80000	10	80000	1	10	80019	20	43	0	80059	0	0	0	59	80040	6	1	59	43	19	0	5020	5	16	0	3	3	26733	13	13	0	80000	10	26738	26738	26738	26716	26737
80024	26736	201	1	0	1	0	1	0	0	0	0	67	0	0	0	2	26700	0	7	7	20	25	80010	10	80000	10	80000	50	1167946	0	1	49	23657	26736	26715	16682	3	16717	80010	20	80000	20	160000	26736	85	1	1	80021	10	9	10	80000	10	80000	0	10	80019	21	43	0	80019	0	0	2	61	80040	6	0	58	43	19	1	5020	2	16	0	2	3	26720	0	13	5	80000	10	26716	26738	26716	26737	26737
80024	26736	201	1	0	1	1	1	0	0	0	0	67	0	1	0	3	26722	2	7	0	19	25	80010	10	80000	10	80000	50	1167985	0	0	49	23656	26737	26736	16681	3	16716	80010	20	80000	20	160000	26737	85	1	1	80021	10	9	10	80000	10	80000	0	10	80019	20	43	0	80058	1	0	2	61	80040	6	0	58	0	19	1	5020	4	16	0	4	4	26734	13	13	0	80000	10	26738	26716	26716	26716	26740
80024	26785	202	1	0	0	1	0	0	0	0	0	66	0	0	0	2	26700	2	7	7	19	25	80010	10	80000	10	80000	50	1179956	0	1	49	23635	26736	26715	16682	3	16717	80010	20	80000	20	160000	26737	64	1	1	80021	10	9	10	80000	10	80000	0	10	80019	19	43	0	80059	0	0	0	63	80040	0	1	60	43	19	1	5020	3	16	0	4	4	26733	0	13	5	80000	10	26737	26715	26716	26716	26737
80024	26736	201	1	0	1	1	0	0	0	0	0	66	0	0	0	2	26721	3	0	0	19	25	80010	10	80000	10	80000	50	1167744	0	1	49	23657	26714	26736	16681	3	16716	80010	20	80000	20	160000	26715	85	1	1	80021	10	9	10	80000	10	80000	0	10	80019	20	43	0	80059	0	0	0	61	80000	6	1	18	43	19	1	5020	3	16	0	4	4	26712	13	13	5	80000	10	26738	26737	26715	26737	26738
80024	26805	200	1	0	0	0	1	0	0	0	0	66	0	0	0	1	26721	3	7	7	20	25	80010	10	80000	10	80000	50	1166960	0	0	49	23634	26736	26715	16660	3	16716	80010	20	80000	20	160000	26736	85	1	1	80021	10	9	10	80000	10	80000	0	10	80019	19	0	0	80149	1	17	0	61	80040	6	1	58	43	19	2	5020	3	16	0	5	5	26733	13	13	5	80000	10	26737	26738	26715	26715	26716
80024	26737	201	1	0	1	0	0	0	0	0	0	67	0	1	0	2	26723	2	7	7	0	25	80010	10	80000	10	80000	50	1165550	0	1	49	23656	26737	26736	16681	3	16695	80010	20	80000	20	160000	26737	64	1	1	80021	10	9	10	80000	10	80000	0	10	80019	19	43	0	80059	1	0	2	61	80000	0	1	58	0	19	2	5020	4	16	0	4	4	26738	0	13	5	80000	10	26740	26738	26718	26738	26737
80024	26737	201	1	0	0	0	0	0	1	0	0	76	0	1	0	3	26722	2	7	7	19	25	80010	10	80000	10	80000	50	1172549	0	1	49	23635	26736	26736	16682	3	16717	80010	20	80000	20	160000	26736	85	1	1	80021	10	9	10	80000	10	80000	0	10	80020	20	43	0	80019	0	0	1	64	80040	0	0	58	0	19	2	5020	4	16	0	4	4	26734	0	13	0	80000	10	26738	26719	26738	26739	26737
80024	26816	201	1	0	1	0	1	0	0	0	0	67	0	0	0	1	26721	3	7	7	20	25	80010	10	80000	10	80000	50	1166960	0	1	49	23656	26737	26737	16681	3	16716	80010	20	80000	20	160000	26737	64	1	1	80021	10	9	10	80000	10	80000	0	10	80019	19	43	0	80058	0	0	0	63	80040	6	1	19	0	19	1	5020	4	16	0	4	5	26734	0	13	0	80000	10	26737	26738	26738	26738	26715
80024	26736	201	1	0	1	1	1	0	0	0	0	21	0	0	0	3	26700	2	0	7	1	25	80010	10	80000	10	80000	50	1168158	0	1	49	23656	26737	26737	16681	3	16716	80010	20	80000	20	160000	26717	86	1	1	80021	10	9	10	80000	10	80000	0	10	80021	21	43	0	80019	0	0	0	60	80039	6	1	59	43	19	0	5020	2	16	0	4	4	26733	0	0	5	80000	10	26737	26737	26737	26716	26716

LDRSW (register, uxtw)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations