Firestorm: PRFM (register, PSTL1KEEP) measurements

Code:

  prfm pstl1keep, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	1e	3a	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	1601	12	36	16	34	0	2480	112	1560	878	25	1000	1000	1000	69496	1	1577	1590	1313	3	1468	1000	1000	1000	1567	1580	1	1	1001	227	2267	2299	3281	0	2437	2271	1000	73	2	16	2	2	1521	1000	1606	1611	1608	1595	1598
1004	1602	12	34	18	35	0	2455	128	1594	924	25	1000	1000	1000	69319	1	1559	1631	1282	3	1479	1000	1000	1000	1576	1570	1	1	1001	255	2281	2292	3266	0	2460	2288	1000	73	2	16	2	2	1538	1000	1599	1624	1599	1621	1638
1004	1623	12	33	17	35	0	2446	132	1574	913	25	1000	1000	1000	69263	1	1598	1595	1319	3	1482	1000	1000	1000	1583	1586	1	1	1001	274	2308	2282	3282	0	2455	2276	1000	73	2	16	2	2	1517	1000	1601	1599	1569	1604	1606
1004	1611	12	33	17	35	0	2502	113	1618	883	25	1000	1000	1000	70236	1	1603	1598	1303	3	1483	1000	1000	1000	1590	1576	1	1	1001	223	2263	2257	3281	0	2498	2282	1000	73	2	16	2	2	1519	1000	1572	1642	1613	1620	1597
1004	1609	12	35	18	33	0	2461	127	1575	885	25	1000	1000	1000	69423	1	1582	1600	1325	3	1484	1000	1000	1000	1602	1559	1	1	1001	256	2299	2273	3286	0	2445	2286	1000	73	2	16	2	2	1515	1000	1611	1622	1607	1619	1619
1004	1618	12	33	15	34	0	2463	113	1595	885	25	1000	1000	1000	69463	1	1586	1616	1313	3	1494	1000	1000	1000	1592	1565	1	1	1001	246	2276	2254	3285	0	2472	2288	1000	73	2	16	2	2	1524	1000	1612	1594	1578	1594	1631
1004	1595	12	34	16	34	0	2465	138	1603	872	25	1000	1000	1000	69238	1	1587	1614	1307	3	1459	1000	1000	1000	1619	1580	1	1	1001	255	2313	2293	3267	0	2446	2282	1000	73	2	16	2	2	1511	1000	1596	1587	1620	1596	1595
1004	1606	12	34	15	34	0	2468	137	1581	891	25	1000	1000	1000	68956	1	1597	1583	1287	3	1440	1000	1000	1000	1586	1601	1	1	1001	249	2267	2310	3273	0	2482	2293	1000	73	2	16	2	2	1487	1000	1644	1604	1636	1595	1637
1004	1575	12	35	16	34	1	2460	141	1621	868	25	1000	1000	1000	69507	1	1624	1600	1327	3	1480	1000	1000	1000	1634	1567	1	1	1001	249	2277	2286	3307	0	2469	2285	1000	73	2	16	2	2	1499	1000	1613	1580	1594	1611	1603
1004	1580	12	37	18	35	0	2464	118	1583	887	25	1000	1000	1000	68388	1	1592	1606	1318	3	1453	1000	1000	1000	1589	1603	1	1	1001	236	2290	2406	3307	1	2471	2299	1000	73	2	16	2	2	1507	1000	1569	1626	1600	1602	1599

Test 2: throughput

Code:

  prfm pstl1keep, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5757

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	bb	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	15703	117	342	183	0	347	24563	0	9977	15624	9887	25	20202	10229	10000	10100	10000	134595	739834	0	27	49	12727	15899	15630	13012	3	13191	20100	10200	10000	10200	10000	15716	156	1	1	20201	100	99	2421	100	10100	100	22740	22703	32751	0	0	24678	22656	10000	0	0	1310	2	16	1	1	15609	10117	10000	10100	15821	15905	15925	15994	15843
20204	15898	118	352	184	0	351	24530	196	9986	15862	9903	25	20224	10199	10000	10100	10000	132749	736388	0	49	49	12688	15688	15870	13116	3	13280	20100	10200	10000	10200	10000	15780	155	1	1	20201	100	99	2479	100	10100	100	22732	22801	32784	1	0	24526	22764	10000	0	0	1310	1	16	1	1	15637	10117	10000	10100	15862	15690	15863	15725	15758
20204	15739	118	344	183	0	336	24386	0	9936	15700	9768	25	20241	10202	10000	10100	10000	131757	738940	0	43	49	12757	15748	15660	13121	3	13297	20100	10200	10000	10200	10000	15622	157	1	1	20201	100	99	2377	100	10100	100	22696	22796	32866	0	0	24618	22840	10000	0	0	1310	1	16	1	1	15738	10141	10000	10100	15753	15732	15759	15796	15748
20204	15770	118	346	184	0	347	24419	0	9942	15854	9770	25	20217	10211	10000	10100	10000	132433	744509	0	33	49	12565	15816	15802	12998	3	13247	20100	10200	10000	10200	10000	15763	165	1	1	20201	100	99	2361	100	10100	100	22711	22749	32817	0	0	24670	22720	10000	0	0	1310	1	16	1	1	15626	10120	10000	10100	15775	15866	15665	15862	15722
20204	15846	119	345	181	0	342	24339	0	9937	15649	9815	25	20184	10199	10000	10100	10000	132303	738698	1	35	49	12690	15800	15685	13110	3	13303	20100	10200	10000	10200	10000	15736	156	1	1	20201	100	99	2490	100	10100	100	22738	22877	32807	0	0	24304	22794	10000	0	0	1310	1	17	1	1	15800	10093	10000	10100	15751	15820	15705	15691	15763
20204	15858	118	344	185	0	345	24355	0	9749	15804	9874	25	20229	10217	10000	10100	10000	133217	737079	1	37	49	12750	15889	15794	13043	3	13296	20100	10200	10000	10200	10000	15711	156	1	1	20201	100	99	2467	100	10100	100	22776	22755	32859	0	0	24571	22744	10000	0	0	1310	1	16	1	1	15684	10093	10000	10100	15716	15790	15769	15874	15657
20204	15753	117	355	183	0	346	24453	0	9849	15874	9702	25	20242	10175	10000	10100	10000	132589	733991	0	36	49	12723	15759	15828	13044	3	13231	20100	10200	10000	10200	10000	15745	156	1	1	20201	100	99	2537	100	10100	100	22663	22625	32703	0	0	24437	22686	10000	0	0	1310	1	16	1	1	15626	10126	10000	10100	15757	15733	15740	15653	15804
20204	15842	119	340	183	0	346	24556	0	9862	15716	9802	25	20199	10202	10000	10100	10000	132594	739488	1	33	49	12835	15757	15724	13090	3	13106	20100	10200	10000	10200	10000	15837	147	1	1	20201	100	99	2564	100	10100	100	22753	22710	32711	0	0	24347	22618	10000	0	0	1310	1	17	1	1	15631	10108	10000	10100	15676	15848	15889	15689	15816
20204	15636	118	347	184	0	346	24353	0	9936	15669	9783	25	20187	10223	10000	10100	10000	133107	733006	0	39	49	12576	15621	15754	13103	3	13207	20100	10200	10000	10200	10000	15894	157	1	1	20201	100	99	2458	100	10100	100	22671	22714	32593	1	0	24507	22718	10000	0	0	1310	1	16	1	1	15556	10090	10000	10100	15740	15876	15817	15709	15653
20204	15746	118	344	186	0	338	24592	0	9846	15690	9607	25	20211	10241	10000	10100	10000	131392	740434	0	23	49	12535	15595	15791	13035	3	13193	20100	10200	10000	10200	10000	15769	156	1	1	20201	100	99	2400	100	10100	100	22841	22675	32791	8	0	24548	22641	10000	0	0	1310	1	16	1	1	15474	10108	10000	10100	15754	15757	15757	15705	15779

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5725

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	15614	117	357	180	357	24760	0	9967	15631	9761	25	20130	10142	10000	10010	10000	132080	730498	0	0	46	49	12607	15769	15714	12918	3	13192	20010	10020	10000	10020	10000	15637	144	1	1	20021	10	9	2319	10	10010	10	22859	22858	32978	1	24499	22946	10000	1270	2	16	1	1	15634	10141	0	0	10000	10010	15663	15818	15700	15805	15664
20024	15652	118	358	188	351	24687	0	9844	15733	9726	25	20148	10106	10000	10010	10000	132628	737894	0	0	49	49	12634	15803	15763	13005	3	13170	20010	10020	10000	10020	10000	15620	157	1	1	20021	10	9	2396	10	10010	10	23029	23029	32844	0	24698	22975	10000	1270	1	16	1	1	15575	10147	0	0	10000	10010	15672	15607	15811	15625	15680
20024	15674	119	357	183	356	24576	0	9863	15693	9733	25	20151	10097	10000	10010	10000	131776	739915	0	0	44	49	12679	15671	15760	12921	3	13164	20010	10020	10000	10020	10000	15642	148	1	1	20021	10	9	2450	10	10010	10	23031	23054	32980	0	24723	22924	10000	1270	1	16	1	1	15473	10123	0	0	10000	10010	15698	15715	15800	15591	15557
20024	15760	118	359	177	349	24546	0	9919	15781	9782	25	20133	10121	10000	10010	10000	133165	736750	0	0	38	49	12606	15630	15714	13007	3	13124	20010	10020	10000	10020	10000	15684	145	1	1	20021	10	9	2375	10	10010	10	22965	22972	32967	0	24499	22931	10000	1270	1	16	1	1	15504	10123	0	0	10000	10010	15785	15700	15760	15615	15653
20024	15742	117	350	180	358	24674	0	9872	15740	9605	25	20142	10163	10000	10010	10000	132938	739706	0	0	58	49	12556	15717	15713	12944	3	13229	20010	10020	10000	10020	10000	15683	143	1	1	20021	10	9	2358	10	10010	10	22990	22862	32859	0	24676	22847	10000	1271	1	16	1	1	15564	10126	0	0	10000	10010	15633	15751	15751	15631	15629
20024	15751	118	352	179	350	24567	0	9865	15811	9789	25	20133	10154	10000	10010	10000	132759	730090	0	0	53	49	12648	15857	15691	13012	3	13210	20010	10020	10000	10020	10000	15757	141	1	1	20021	10	9	2418	10	10010	10	22929	22892	33079	0	24584	22849	10000	1270	1	16	1	1	15567	10123	0	0	10000	10010	15754	15696	15829	15707	15715
20024	15932	118	352	184	354	24535	0	9855	15657	9863	25	20121	10157	10000	10010	10000	131358	741070	0	0	53	49	12563	15612	15636	13072	3	13110	20010	10020	10000	10020	10000	15697	150	1	1	20021	10	9	2462	10	10010	10	22916	22945	32879	0	24752	22861	10000	1270	1	15	1	1	15629	10156	0	0	10000	10010	15721	15668	15723	15749	15751
20024	15690	117	351	179	352	24702	0	9932	15800	9892	25	20151	10133	10000	10010	10000	134051	741790	0	0	53	49	12680	15592	15702	13041	3	13113	20010	10020	10000	10020	10000	15685	154	1	1	20021	10	9	2341	10	10010	10	23103	22818	32986	0	24606	22924	10000	1270	1	16	1	1	15590	10144	0	0	10000	10010	15823	15760	15711	15615	15506
20024	15592	119	355	183	355	24539	0	9851	15682	9740	25	20133	10124	10000	10010	10000	133026	734756	0	0	46	49	12552	15636	15735	13036	3	13143	20010	10020	10000	10020	10000	15596	143	1	1	20021	10	9	2383	10	10010	10	23108	22921	32755	0	24690	22802	10000	1270	1	16	2	1	15595	10114	0	0	10000	10010	15601	15619	15678	15665	15639
20024	15685	118	353	185	361	24592	0	9958	15662	9659	25	20151	10148	10000	10010	10000	132723	732830	0	1	38	49	12605	15774	15589	12909	3	13139	20010	10020	10000	10020	10000	15718	147	2	1	20021	10	9	2562	10	10010	10	22775	22905	32923	0	24431	23083	10000	1270	1	16	1	1	15523	10147	0	0	10000	10010	15779	15727	15653	15722	15542

Test 3: throughput

Code:

  prfm pstl1keep, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5487

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10204	15504	115	321	163	315	24604	1250	15483	9525	25	10100	100	10000	100	10000	500	722344	49	12431	15462	15465	13970	7	14166	10109	200	10016	200	10016	15476	12296	1	1	10201	100	99	2758	100	100	100	22666	22664	32633	1	24445	22557	10000	1	1	1	717	0	16	0	0	15457	10000	100	15386	15485	15467	15500	15466
10204	15414	116	326	167	318	24559	1292	15448	9560	25	10100	100	10000	100	10000	500	725195	49	12413	15474	15431	13942	6	14124	10208	202	10000	200	10000	15452	12203	1	1	10201	100	99	2730	100	100	100	22666	22695	32626	0	24464	22602	10000	1	1	1	722	2	24	2	2	15350	10000	100	15417	15404	15518	15393	15480
10204	15473	115	316	160	320	24360	1283	15479	9576	25	10100	100	10000	100	10000	500	723087	49	12433	15485	15458	14025	6	14065	10100	200	10000	200	10000	15491	12226	1	1	10201	100	99	2683	100	100	100	22644	22702	32525	0	24385	22632	10000	1	1	1	722	2	24	2	2	15374	10000	100	15511	15495	15519	15476	15401
10204	15517	115	318	163	314	24428	1226	15470	9524	25	10100	100	10000	100	10000	500	724081	49	12388	15516	15430	13995	6	14215	10100	200	10000	200	10000	15436	12308	1	1	10201	100	99	2720	100	100	100	22711	22666	32652	0	24501	22653	10000	1	1	1	722	2	24	2	2	15408	10000	100	15455	15454	15436	15382	15564
10204	15607	116	320	160	321	24474	1335	15505	9489	25	10100	100	10000	100	10000	500	728467	49	12335	15485	15517	13945	6	14194	10100	200	10000	200	10000	15457	12254	1	1	10201	100	99	2769	100	100	100	22650	22614	32716	0	24461	22730	10000	1	1	1	722	2	24	2	2	15426	10000	100	15496	15394	15523	15476	15420
10204	15481	116	321	162	317	24451	1243	15410	9489	25	10100	100	10000	100	10000	500	725589	49	12423	15447	15387	14000	6	14139	10100	200	10000	200	10000	15487	12280	1	1	10201	100	99	2711	100	100	100	22635	22629	32640	0	24569	22694	10000	1	1	1	722	2	24	2	2	15376	10000	100	15457	15454	15518	15470	15476
10204	15521	115	319	163	322	24458	1202	15448	9597	25	10100	100	10000	100	10000	500	723703	49	12326	15518	15495	13999	6	14206	10100	200	10000	200	10000	15455	12172	1	1	10201	100	99	2741	100	100	100	22611	22693	32595	0	24450	22694	10000	1	1	1	722	2	24	2	2	15318	10000	100	15534	15490	15485	15430	15402
10204	15491	116	323	163	321	24542	1264	15446	9570	25	10100	100	10000	100	10000	500	728193	49	12367	15475	15466	14022	6	14161	10100	200	10000	200	10000	15418	12267	1	1	10201	100	99	2659	100	100	100	22716	22692	32658	0	24470	22615	10000	1	1	1	722	2	24	2	2	15398	10000	100	15484	15447	15419	15504	15409
10204	15504	116	319	161	319	24447	1270	15541	9560	25	10100	100	10000	100	10000	500	725749	49	12414	15328	15573	14039	6	14102	10100	200	10000	200	10000	15457	12251	1	1	10201	100	99	2707	100	100	100	22580	22680	32624	0	24466	22650	10000	1	1	1	722	2	24	2	2	15362	10000	100	15459	15497	15463	15516	15438
10204	15464	116	321	162	320	24350	1231	15559	9535	25	10100	100	10000	100	10000	500	722348	49	12312	15470	15417	14009	6	14209	10100	200	10000	200	10000	15552	12183	1	1	10201	100	99	2719	100	100	100	22693	22641	32719	0	24428	22667	10000	1	1	1	722	2	24	2	2	15388	10000	100	15547	15464	15505	15501	15461

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5533

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10024	15513	115	292	145	290	23889	1361	15537	9642	25	10010	10	10000	10	10000	50	728300	1	49	12529	15574	15576	14153	3	14306	10010	20	10000	20	10000	15474	15499	1	1	10021	10	9	2673	10	10	10	22229	22167	32224	0	23910	22244	10000	640	3	16	3	3	15367	10000	10	15567	15532	15658	15428	15558
10024	15498	116	296	145	291	23947	1357	15471	9641	25	10010	10	10000	10	10000	50	725868	1	49	12475	15605	15515	14064	3	14277	10010	20	10000	20	10000	15571	15428	1	1	10021	10	9	2713	10	10	10	22268	22209	32232	0	23972	22266	10000	640	3	16	3	3	15484	10000	10	15544	15616	16025	15610	15524
10024	15542	117	290	146	291	23923	1318	15520	9519	25	10010	10	10000	10	10000	50	725528	1	49	12440	15557	15571	14172	3	14237	10010	20	10000	20	10000	15449	15488	1	1	10021	10	9	2659	10	10	10	22195	22245	32215	0	23998	22228	10000	640	3	16	3	3	15451	10000	10	15584	15491	15521	15510	15413
10024	15600	117	288	147	290	23969	1293	15532	9630	25	10010	10	10000	10	10000	50	727338	1	49	12538	15583	15533	14214	3	14230	10010	20	10000	20	10000	15369	15443	1	1	10021	10	9	2691	10	10	10	22270	22283	32208	0	23970	22162	10000	640	3	16	3	3	15418	10000	10	15638	15621	15614	15549	15546
10024	15481	116	292	145	292	23998	1332	15446	9545	25	10010	10	10000	10	10000	50	727298	1	49	12387	15521	15613	14109	3	14203	10010	20	10000	20	10000	15444	15449	1	1	10021	10	9	2698	10	10	10	22284	22314	32131	1	24017	22232	10000	640	3	16	3	3	15402	10000	10	15520	15585	15588	15450	15640
10024	15441	117	287	145	294	24054	1315	15715	9600	25	10010	10	10000	10	10000	50	733022	0	49	12675	15476	15591	14165	3	14422	10120	20	10121	20	10000	15550	15511	1	1	10021	10	9	2701	10	10	10	22239	22243	32306	0	23983	22184	10000	640	3	16	3	3	15408	10000	10	15543	15510	15647	15631	15594
10024	15540	117	294	144	291	24057	1364	15575	9528	25	10010	10	10000	10	10000	50	724878	1	49	12489	15544	15593	14130	3	14280	10010	20	10000	20	10000	15434	15472	1	1	10021	10	9	2673	10	10	10	22225	22213	32288	0	24040	22203	10000	640	3	16	3	3	15481	10000	10	15470	15555	15601	15603	15496
10024	15505	116	290	144	292	24038	1351	15623	9551	25	10010	10	10000	10	10000	50	726836	1	49	12424	15515	15544	14137	3	14302	10010	20	10000	20	10000	15485	15454	1	1	10021	10	9	2646	10	10	10	22301	22252	32286	1	23964	22153	10000	640	3	16	3	3	15426	10000	10	15551	15561	15539	15548	15552
10024	15499	116	288	145	284	23979	1347	15552	9590	25	10010	10	10000	10	10000	50	722695	1	49	12370	15611	15499	14173	3	14329	10010	20	10000	20	10000	15484	15480	1	1	10021	10	9	2706	10	10	10	22236	22216	32234	0	23875	22185	10000	640	3	16	3	3	15360	10000	10	15505	15539	15580	15541	15547
10024	15608	116	292	146	290	23925	1310	15495	9542	25	10010	10	10000	10	10000	50	728843	1	49	12363	15435	15584	14048	3	14259	10010	20	10000	20	10000	15477	15518	1	1	10021	10	9	2617	10	10	10	22299	22247	32295	0	23969	22276	10000	640	3	16	3	3	15465	10000	10	15555	15474	15560	15506	15512

PRFM (register, PSTL1KEEP)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations