Firestorm: ASR (register, 64-bit) measurements

Code:

  asr x0, x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1035	8	0	0	61	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	0	61	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	0	61	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	27	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	61	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	61	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	0	61	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	6	61	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	243	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	84	61	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	0	61	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036

Test 2: Latency 1->2

Code:

  asr x0, x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	0	0	82	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	84	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	786	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	76	0	0	0	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	84	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	84	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	1	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	103	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	640	4	41	6	5	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	640	6	41	7	4	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	12	640	6	41	6	6	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	470	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	15	640	5	41	5	3	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	191	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	640	5	41	6	4	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	640	6	41	5	4	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	147	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	7	15	640	6	41	6	4	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	182	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	640	5	41	6	7	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	124	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	640	5	41	6	6	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	142	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	18	640	6	41	7	5	9940	10000	10010	10036	10036	10036	10036	10036

Test 3: Latency 1->3

Code:

  asr x0, x1, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	0	82	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	1	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	617	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	835	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	1	2295	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	1	0	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	195	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	81	0	0	84	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	124	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	4	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	12	710	1	37	2	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4d	50	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	103	9863	10019	25	10010	10010	10010	88784	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	3	640	2	41	3	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	145	9863	10019	25	10010	10010	10010	88784	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	4	0	0	640	2	41	3	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	76	214	9863	0	25	10010	10010	10010	88784	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	12	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9863	0	25	10010	10010	10010	88784	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9863	0	25	10010	10010	10010	88784	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	1	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9863	0	25	10010	10010	10010	88784	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	3	640	2	41	3	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	781	9863	0	25	10010	10010	10010	88784	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	3	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	124	9863	0	25	10010	10010	10010	88784	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	3	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9863	0	25	10010	10010	10010	88784	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	3	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9863	0	25	10010	10010	10010	88784	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036

Test 4: throughput

Count: 8

Code:

  asr x0, x8, x9
  asr x1, x8, x9
  asr x2, x8, x9
  asr x3, x8, x9
  asr x4, x8, x9
  asr x5, x8, x9
  asr x6, x8, x9
  asr x7, x8, x9

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.1673

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	13419	101	0	203	25	80100	80100	80100	400500	49	10306	13386	13386	3323	0	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	5111	6	19	5	5	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	100	0	35	25	80100	80100	80100	400500	49	10306	13386	13386	3323	0	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	2	3	5111	5	19	5	2	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	100	0	164	25	80100	80100	80100	400500	49	10306	13386	13386	3323	0	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	1	0	5111	5	19	6	3	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	101	0	35	25	80100	80100	80100	400500	49	10306	13386	13386	3323	0	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	5111	4	19	5	5	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	100	0	35	25	80100	80100	80100	400500	49	10306	13386	13386	3323	0	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	5111	4	19	6	5	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	100	0	35	25	80100	80100	80100	400500	49	10306	13386	13386	3323	0	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	5111	4	19	5	3	13383	80000	80100	13392	13392	13387	13387	13387
80204	13386	100	0	77	25	80100	80100	80100	400500	49	10306	13386	13386	3323	0	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	5111	4	19	4	3	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	100	0	77	25	80100	80100	80100	400500	49	10306	13386	13386	3323	0	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	1	3	5111	4	19	5	4	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	101	0	144	25	80100	80100	80100	400500	49	10306	13386	13386	3323	0	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	5111	3	19	3	3	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	103	0	35	25	80100	80100	80100	400500	49	10306	13386	13386	3323	0	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	3	5111	4	19	5	5	13383	80000	80100	13387	13387	13387	13387	13387

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.1671

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	d9	da	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? int retires (ef)	f5	f6	f7	f8	fd
80024	13386	100	0	3	0	723	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	11	19	8	0	6	6	13368	80000	0	80010	13372	13372	13372	13372	13372
80024	13371	100	0	0	0	415	25	80010	80010	80010	400050	1	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	2	19	6	0	2	2	13368	80000	0	80010	13372	13433	13372	13372	13372
80024	13371	100	0	0	0	465	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	160554	13371	39	1	1	80021	10	9	10	80010	10	0	2	0	5020	2	19	6	0	2	6	13368	80000	0	80010	13372	13372	13372	13372	13372
80024	13371	100	0	0	0	77	25	80137	80010	80010	400050	1	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13433	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	2	19	8	0	2	2	13368	80000	0	80010	13372	13372	13372	13372	13372
80024	13371	100	0	0	0	58	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	5022	2	19	6	0	2	2	13368	80000	0	80010	13372	13372	13372	13372	13372
80024	13371	100	0	0	0	58	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	2	19	4	0	6	2	13368	80000	0	80010	13372	13372	13372	13372	13372
80024	13371	100	0	0	0	190	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	2	19	6	0	2	2	13368	80000	0	80010	13372	13372	13372	13372	13372
80024	13371	100	0	0	0	79	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	2	19	6	0	6	2	13368	80000	0	80010	13372	13372	13372	13372	13372
80024	13371	100	0	0	0	277	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	4	19	6	0	2	2	13368	80000	0	80010	13372	13372	13372	13372	13372
80024	13371	100	0	0	0	100	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	2	19	6	0	2	2	13368	80000	0	80010	13372	13372	13372	13372	13372

ASR (register, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations