Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SB

Test 1: uops

Code:

  sb

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 4.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)0318191e1f3f51schedule uop (52)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)6066696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)8283flush restart other nonspec (84)85inst all (8c)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acbccfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)f5f6f7f8fd
40042702820200541000270132202510001000100050001260004923948270282702826000626010100010002702827028111001002000001000100073116112700010002702927029270292702927029
4004270282030001000270132202510001000100050001260004923948270282702826000326010100010002702827028111001002000001021100073116112700010002702927029270292702927029
4004270282030001000270132202510001000100050001260004923948270282702826000326010100010002702827028111001002000001000100073116112700010002702927029270292702927029
4004270282020001176270132202510001000100050001260004923948270282702826000326010100010002702827028111001002000001000100073116112700010002702927029270292702927029
40042702820300361000270132202510001000100050001260004923948270282702826000326010100010002702827028111001002000001000100073116112700010002702927029270292702927029
400427028202001411088270132202510001000100050001260004923948270282702826000326010100010002702827028111001002000001000100073116112700010002702927029270292702927029
4004270282020001000270132202510001000100050001260004923948270282702826000326010100010002702827028111001002000001000100073116112700010002702927029270292702927029
40042702820200391000270132202510001000100050001260004923948270282702826000326010100010002702827028111001002000011000100073116112700010002702927029270292702927029
40042702820200151000270132202510001000100050001260004923948270282702826000326010100010002702827028111001002000001000100073116112700010002702927029270292702927029
40042702820200151000270132202510001000100050001260004923948270282702826000326010100010002702827028111001002000001000100073116112700010002702927029270292702927029

Test 2: throughput

Code:

  sb

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 27.0135

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6066696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fst unit uop (a7)l1d cache writeback (a8)a9acbcc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)? int retires (ef)f5f6f7f8fd
40204270139202300000100000270120220124101001001000010010000500500001260099492670550270135270135260099326011710102200100002002701352160951110201100991001001002000000100001000000007101171127010610000100270136270136270136270136270136
402042701352024000051100000270120220124101001001000010010000500500001260099492670550270135270135260099326011710100200100002002701352160951110201100991001001002000000100001000000007101171127010610000100270136270136270136270136270136
40204270135202300000100000270120220124101001001000010010000500500001260099492670550270135270135260099326011710100200100002002701352160951110201100991001001002000010100001000000017101171127010610000100270136270136270136270136270136
402042701352057000015100000270120220124101001001000010010000500500001260099492670550270135270135260099326011710100200100002002701352160951110201100991001001002000000100001000000007101171127010610000100270136270136270136270136270136
40204270135202400000100000270120220124101001001000010010000500500000260099492670550270135270135260099326011710100200100002002701352160951110201100991001001002000230100151000000007101171127010610000100270136270136270165270136270136
40204270135202400000100000270120220124101001001000010010000500500001260099492670550270135270164260099326011710100200100002002701352160951110201100991001001002000000100001000000007101171127010610000100270165270136270136270136270136
40204270135202400000100000270120220124101001001000210010000500500001260099492670550270135270135260099326011710100200100002002701352160951110201100991001001002000000100001000000007101171127010610000100270136270136270136270136270136
40204270135202300000100000270120220124101001001000010010000500500001260099492670550270135270135260099326013510100200100002002701352160951110201100991001001002000040100031000000007101171127010610000100270136270136270136270136270136
40204270135202400000100000270120220124101001001000010010000500500001260099492670550270135270135260099326011710100200100002002701352160951110201100991001001002000000100001000000007101171127010610000100270136270136270165270136270136
40204270135202400000100000270120220124101001001000010010000500500000260099492670550270135270135260099326011710100200100042002701352160951110201100991001001002000000100001000000007101171127010610000100270136270136270136270136270163

1000 unrolls and 10 iterations

Result (median cycles for code): 27.0045

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6066696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acbcc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)? int retires (ef)f5f6f7f8fd
4002427004920280101000100002700592200341001010100001010000505000002600094926696502700452700742600093260027100102010000202700452700451110021109101010000200000010000100000000640617662700161000010270046270046270046270046270046
4002427004520230000000100002700302200341001010100001010000505000002600094926696502700452700452600093260027100102010000202700452700451110021109101010000200000010000100000000640617662700161000010270046270046270046270046270046
4002427004520220000000100002700302200341001010100001010002505000012600094926696502700452700452600093260027100102010000202700452700451110021109101010000200000010006100000000640617662700161000010270046270075270046270046270046
400242700452023000000456100002700302200341001010100001010000505000002600094926696502700452700742600093260027100102010000202700452700451110021109101010000200001010357100000000640617662700161000010270046270046270046270046270046
4002427004520220000000100002700302200341001010100001010000505000002600094926696502700452700452600093260027100102010000202700452700451110021109101010000200000010390100000000640617662700161000010270046270046270046270046270046
4002527004520230000000100002700302200341001010100001010000505000012600094926696502700452700452600093260027100102010000202700452700451110021109101010000200010010036100000000656617662700161000010270046270046270046270046270046
40024270045202300000036100002700302200341001010100001010000505000022600094926696502700452700452600093260027100102010000202700452700451110021109101010000200000010366100000000640617662700161000010270046270046270046270046270046
4002427023620220000000100002700302200341001010100001010000505000002600094926696502700452700452600099260027100102010000202700452700451110021109101010000200000010399100000000640717662700161000010270046270046270046270046270046
4002427004520220000000100002700302200341001010100001010000505000002600094926696502700452700452600093260027100102010000202700452700451110021109101010000200002010000100000000656517672700161000010270046270046270046270046270046
4002427004520230000000100002700302200341001010100001010000505000002600094926696502700452700452600093260027100102010000202700452700451110021109101010000200000010000100000000640617662700161000010270046270046270046270046270046