Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SBC (32-bit)

Test 1: uops

Code:

  sbc w0, w0, w1
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)1e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100410357000619172510001000100062250103510358053882100010003000103510411100110000073327339901000100010361036103610361036
100410357000619172510001000100062250103510358053882100010003000103510411100110004073327339901000100010361036103610361036
100410357000619172510001000100062250103510358053882100010003000103510411100110000073327339901000100010361036103610361036
100410357000619172510001000100062250103510358053882100010003000103510411100110000073327339901000100010361036103610361036
100410357000619172510001000100062250103510358053882100010003000103510411100110000073327339901000100010361036103610361036
100410357000619172510001000100062250103510358053882100010003000103510411100110001073327339901000100010361036103610361036
100410358000619172510001000100062250103510358053882100010003000103510411100110003073327339901000100010361036103610361036
100410358000619172510001000100062250103510358053882100010003000103510411100110002073327339901000100010361036103610361036
100410357000619172510001000100062250103510358053882100010003000103510411100110004073327339901000100010361036103610361036
100410357000619172510001000100062250103510358053882100010003000103510411100110004073327339901000100010361036103610361036

Test 2: Latency 1->2

Code:

  sbc w0, w0, w1
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03mmu table walk instruction (07)18191e1f3a3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204100357500012192039499202510100101001012564715214969551003510035865638732101001020030200100351021110201100991001010010000071012711999210000101001003610036100361003610036
10204100357500018006199202510100101001010064715214969551003510035865638732101001020030200100351091110201100991001010010000071012711999210000101001003610036100361003610036
1020410035751000006199202510100101001010064715214969551003510035865638732101001020030200100351091110201100991001010010001071012711999210000101001003610036100361003610036
102041003575000150010399202510100101001010064715214969551003510035865738732101251020030200100351021110201100991001010010000071212711999210000101001003610036100361003610036
102041003575000150010399202510100101001010064715214969551003510035865638732102801020030200100351021110201100991001010010000071012711999210000101001003610036100361003610036
1020410035750000006199202510100101001010064715204969551003510035865638732101001020030200100351021110201100991001010010020371012711999210000101001003610036100361003610036
102041003575000120061992025101001010010100647152149695510035100358656387321010010200302001003510211102011009910010100100000714140111006210000101001003610036100361003610036
10204100357500072006199202510100101001010064715204969551003510035865638732101001020030200100351021110201100991001010010000071012711999310000101001003610036100361003610036
1020410035750000006199202510100101001010064715214969551003510035865638732101001020030200100351021110201100991001010010000071012711999210000101001003610036100361003610036
1020410035750000006199202510100101001010064715204969551003510035865638732101001020030200100351021110201100991001010010000071012711999210000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e1f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024100357600849918251001010010100106472461496955100351003586783875410010100203002010035104111002110910100101000064022722999310000100101003610036100361003610036
10024100357500619918251001010010100106472461496955100351003586783875410010100203002010035104111002110910100101000064022722999310000100101003610036100361003610036
10024100357500619918251001010010100106472461496955100351003586783875410010100203002010035104111002110910100101000064022722999310000100101003610036100361003610036
10024100357500619918251001010010100106472461496955100351003586783875410010100203002010035104111002110910100101000064032722999310000100101003610036100361003610036
10024100357500619918251001010010100106472461496955100351003586783875410010100203002010035104111002110910100101000064022722999310000100101003610036100361003610036
100241003575001269918251001010010100106472461496955100351003586783875410010100203002010035104111002110910100101000064032722999310000100101003610036100361003610036
1002410035750014799182510010100101001064724614969551003510035867838754100101002030020100351041110021109101001010160064032722999310000100101003610036100361003610036
100241003575001039918251001010010100106472461496955100351003586783875410010100203002010035104111002110910100101010064032722999310000100101003610036100361003610036
100241003575001469918251001010010100106472461496955100351003586783875410010100203002010035104111002110910100101000064022722999310000100101003610036100361003610036
10024100357500619918251001010010100106472461496955100351003586783875410010100203002010035104111002110910100101000064022722999310000100101003610036100361003610036

Test 3: Latency 1->3

Code:

  sbc w0, w1, w0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6061696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102041003575636199202510100101001010064715201049695510035100358656687581010010200302001003510211102011009910010100100071010012711999210000101001003610036100361003610036
10204100357506199202510142101001010064715210496955100351003586563873210100102003020010035102111020110099100101001000710101012711999210000101001003610036100361003610036
10204100357512619920251010010100101006471521049695510035100358656387321010010200302001003510211102011009910010100100071001012711999210000101001003610036100361003610036
102041003575061992025101001010010100647152110496955100351003586563873210100102003020010035102111020110099100101001000710101012711999210000101001003610036100361003610036
102041003575061992025101001010010100647152110496955100351003586563873210100102003020010035102111020110099100101001000710101012711999210000101001003610036100361003610036
102041003575061992025101001010010100647152110496955100351016886563873210100102003020010035102111020110099100101001000710101012711999210000101001003610036100361003610036
102041003575961992025101001010010100647152110496955100351003586563873210100102003020010035102111020110099100101001000710101012711999210000101001003610036100361003610036
10204100357508299202510100101001010064715211049695510035100358656387321010010200302001003510211102011009910010100100071010012711999210000101001003610036100361003610036
10204100357506199202510100101001010064715211049695510035100358656387321010010200302001003510211102011009910010100100071010512711999210000101001003610036100361003610036
10204100357506199202510100101001010064715211049695510035100358656387321010010200302001003510211102011009910010100100071010512711999210000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)a9branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1002410035750619918251001010010100106472461496955100351003586783875410010100203002010035104111002110910100101000064042734999310000100101003610036100361003610036
1002410035756619918251001010010100106472460496955100351003586783875410010100203002010035104111002110910100101000064042743999310000100101003610036100361003610036
1002410035750829918251001010010100106472461496955100351003586783875410010100203002010035104111002110910100101000064032734999310000100101003610036100361003610036
100241003575165619918251001010010100106472461496955100351003586783875410010100203002010035104111002110910100101000064032744999310000100101003610036100361003610036
1002410035750619918251001010010100106472461496955100351003586783875410010100203002010035104111002110910100101000064042734999310000100101003610036100361003610036
1002410035750619918251001010010100106472461496955100351003586783875410010100203002010035104111002110910100101000064042744999310000100101003610036100361003610036
1002410035750619918251001010010100106472461496955100351003586783875410010100203002010035104111002110910100101000064032734999310000100101003610036100361003610036
10024100357618619918251001010010100106472461496955100351003586783875410010100203002010035104111002110910100101000064042743999310000100101003610036100361003610036
10024100357515619918251001010010100106472461496955100351003586783875410010100203002010035104111002110910100101000064042744999310000100101003610036100361003610036
1002410035753619918251001010010100106472461496955100351003586783875410010100203002010035104111002110910100101000064042734999310000100101003610036100361003610036

Test 4: Latency 1->4

Chain cycles: 1

Code:

  sbc w0, w1, w2
  tst x0, 1
  mov x0, 1
  mov x1, 2
  mov x2, 3

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03191e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst int alu (97)l1d tlb access (a0)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
202042003515003982199264520200202002020012976500491695520035200351740631748120200202004020020035104112020110099201000000001310128111999220100101002003620036200362003620036
20204200351500661199262520200202002020012976501491695520035200351740631748120200202004020020035104112020110099201000000001310128111999220100101002003620036200362003620036
202042003515001261199262520200202002020012976501491695520035200351740631748120200202004020020035104112020110099201000000001310128111999220100101002003620036200362003620036
202042003515005761199262520200202002020012976501491695520035200351740631748120200202004020020035104112020110099201000000001310128111999220100101002003620036200362003620036
202042003515000726199262520200202002020012976501491695520035200351740631748120297202004020020035104112020110099201000000001310128111999220100101002003620036200362003620036
20204200351500061199262520200202002020012976501491695520035200351740631748120200202004020020035104112020110099201000000001310128111999220100101002003620036200362003620036
20204200351500361199262520200202002020012976501491695520035200351740631748120200202004020020035104112020110099201000000001310128111999220100101002003620036200362003620036
20204200351500061199262520200202002020012976501491695520035200351740631748120200202004020020035104112020110099201000000001310128111999220100101002003620036200362003620036
20204200351500061199262520200202002020012976501491695520035200351740631748120200202004020020035104112020110099201000000001310128111999220100101002003620036200362003620036
20204200351500061199262520200202002020012976501491695520035200351740631748120200202004020020035104112020110099201000000001310128111999220100101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst int alu (97)l1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
200242003515000611991825200202002020020129729704916955200352003517428317504200202002040020200351041120021109200100001270127111999520010100102003620036200362003620036
2002420035150063611991825200202002020020129729704916955200352003517428317504200202002040020200351041120021109200100001270127111999520010100102003620036200362003620036
2002420035150048611991825200202002020020129729709816955200352003517428317504200202002040020200351041120021109200100001270127111999520010100102003620036200362003620036
2002420035150093611991825200202002020020129729714916955200352003517428317504200202002040020200351041120021109200100001270127111999520010100102003620036200362003620036
200242003515008161199182520020200202002012972971491695520035200351742831750420020200204002020035104112002110920010009571270127111999520010100102003620036200362003620036
2002420035150054611991825200202002020020129729704916955200352003517428317504200202002040020200351041120021109200100001270227111999520010100102003620036200362003620036
2002420035150081611991825200202002020020129729704916955200352003517428317504200202002040020200351041120021109200100001270127111999520010100102003620036200362006720036
2002420035150099611991825200202002020020129729704916955200352003517428317504200202002040020200351041120021109200100001270127111999520010100102003620036200362003620036
200242003515000611991825200202002020020129729704916955200352003517428317504200202002040020200351041120021109200100001270127111999520010100102003620036200362003620036
2002420035150018611991825200202002020020129729704916955200352003517428317504200202002040020200351041120021109200100001270127111999520010100102003620036200362003620036

Test 5: throughput

Count: 8

Code:

  sbc w0, w8, w9
  sbc w1, w8, w9
  sbc w2, w8, w9
  sbc w3, w8, w9
  sbc w4, w8, w9
  sbc w5, w8, w9
  sbc w6, w8, w9
  sbc w7, w8, w9
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)181e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
802042674020000000036258010080100801004797990492365626736267361667231669180100802002402002673666118020110099100801001000005110419222673280000801002673726737267372673726737
802042673620100000036258010080100801004797990492365626736267361667231669180100802002402002673666118020110099100801001000005110219222673280000801002673726737267372673726737
80204267362000000003625801878010080100479799149236562673626736166723166918010080200240200267366611802011009910080100100022805110219232673280000801002673726737267372673726737
802042673620100000036258010080100801004797991492365626736267361667231669180100802002402002673666118020110099100801001000005110237222673280000801002673726737267372673726737
802042673620000000036258010080100801004797991492365626736267361667231669180100802002402002673666118020110099100801001000005110219222673280000801002673726737267372673726737
802042673620000000036258010080100801004797990492365626736267361667231669180100802002402002673666118020110099100801001000005110219222673280000801002673726737267372673726737
802042673620000000036258010080100801004797990492365626736267361667231669180100802002402002673666118020110099100801001000005110219222673280000801002673726737267372673726737
802042673620000000036258010080100801004797991492365626736267361667231669180100802002402002673666118020110099100801001000005110219222673280000801002673726737267372673726737
8020426736200000000701258010080100801004797990492365626736267361667231669180100802002402002673666118020110099100801001000005110219222673280000801002673726737267372673726737
802042673620000000036258010080100801004797990492365626736267361667231669180100802002402002673666118020110099100801001004005110219222673280000801002673726737267372673726737

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)5f60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
800242672320000001236258001080010800104720590149236262670626706166653166848001080020240020267066611800211091080010100005020318112670280000800102675526707267072670726707
80024267062000000636258001080010800104720590149236262670626706166653166848001080315240020267066611800211091080010100005020118112670280000800102670726707268942670726707
80024267062000000636258001080010800104720590149236262670626706166653166848001080020240020267066611800211091080010100005020118112670280000800102670726707267072670726707
80024267062000100036258001080010800105026920149236262670626706166653166848001080020240020267066611800211091080010100005020118112670280000800102670726707267072670726707
80024267062000000636258001080010800104720590149236262670626706166653166848001080020240020267066611800211091080010100005020118112670280000800102670726707267072670726707
80024267062000000036258001080010800104720590149236262679926706166653166848001080020240020267066611800211091080010100005020118112670280000800102670726707267072670726707
80024267062000000336258001080010800104647110149236262670626706166653166848001080020240020267066611800211091080010100005066118112670280000800102670726707267072670726707
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