Firestorm: CRC32W measurements

Code:

  crc32w w0, w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	3033	22	61	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	2000	3033	380	1	1	1001	1000	0	0	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	22	61	1922	25	1000	1000	1000	81440	1	40	3033	3033	2760	3	2891	1000	1000	2000	3033	380	1	1	1001	1000	0	3	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	61	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	2000	3033	380	1	1	1001	1000	0	0	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	22	156	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	2000	3033	380	1	1	1001	1000	0	0	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	61	1922	25	1000	1000	1000	81440	1	40	3033	3033	2760	3	2891	1000	1000	2000	3033	380	1	1	1001	1000	0	0	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	61	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	2000	3033	380	1	1	1001	1000	0	0	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	61	1922	25	1000	1000	1000	81440	1	40	3033	3033	2760	3	2891	1000	1000	2000	3033	380	1	1	1001	1000	1	0	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	61	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	2000	3033	380	1	1	1001	1000	38	0	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	22	61	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	2000	3033	380	1	1	1001	1000	0	0	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	61	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	2000	3033	380	1	1	1001	1000	4	0	73	1	16	1	1	2939	1000	1000	3034	3034	3034	3034	3034

Test 2: Latency 1->2

Code:

  crc32w w0, w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30033	225	0	61	19922	25	10100	10154	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	20200	30164	690	1	1	10201	100	99	100	10100	100	3	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	61	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	20200	30033	374	1	1	10201	100	99	100	10100	100	12	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	224	0	61	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	20200	30033	374	1	1	10201	100	99	100	10100	100	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	224	0	251	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	20200	30033	374	1	1	10201	100	99	100	10100	100	0	724	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	536	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	20200	30033	374	1	1	10201	100	99	100	10100	100	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	61	19922	25	10137	10148	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	20200	30033	374	1	1	10201	100	99	100	10100	100	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	224	0	61	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	20200	30033	374	1	1	10201	100	99	100	10100	100	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	61	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	20200	30033	374	1	1	10201	100	99	100	10100	100	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	233	0	61	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	20200	30033	374	1	1	10201	100	99	100	10100	100	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	224	0	1114	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	20200	30033	374	1	1	10201	100	99	100	10100	100	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30033	225	0	0	0	61	19922	25	10010	10010	10010	828490	0	49	26953	0	30033	30033	28632	3	28763	10010	10020	20020	30033	380	1	1	10021	10	9	10	10010	10	1	0	3	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	61	19922	25	10010	10010	10010	828490	0	49	26953	0	30033	30033	28632	3	28763	10010	10020	20020	30033	380	1	1	10021	10	9	10	10010	10	0	0	3	640	2	16	2	2	29939	10009	10010	30077	30034	30034	30034	30034
10024	30077	224	1	1	0	61	19922	25	10010	10010	10010	828490	0	49	26953	0	30033	30033	28647	3	28763	10010	10020	20020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	61	19922	25	10010	10010	10010	828490	0	49	26953	0	30033	30033	28632	3	28763	10010	10020	20020	30033	380	1	1	10021	10	9	10	10010	10	1	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	12	61	19922	25	10010	10010	10010	828490	0	49	26953	0	30033	30033	28632	3	28763	10010	10020	20020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	82	19922	25	10010	10010	10010	828490	0	49	26953	0	30033	30033	28632	3	28763	10010	10020	20020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	536	19922	25	10010	10010	10010	828490	0	49	26953	0	30033	30033	28632	3	28763	10010	10020	20020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	84	19922	25	10010	10010	10010	828490	0	49	26953	0	30033	30033	28632	3	28763	10010	10020	20020	30033	380	1	1	10021	10	9	10	10010	10	0	0	6	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	61	19922	25	10010	10010	10010	828490	0	49	26953	0	30033	30033	28632	3	28763	10010	10020	20020	30033	380	2	1	10021	10	9	10	10010	10	0	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	61	19922	25	10010	10010	10010	828490	0	49	26953	0	30033	30033	28632	3	28763	10010	10020	20020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	640	2	19	2	2	29939	10000	10010	30034	30034	30034	30034	30034

Test 3: Latency 1->3

Code:

  crc32w w0, w1, w0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30033	225	0	0	0	0	61	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	20200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	16	1	1	29939	10018	10100	30034	30034	30034	30034	30034
10204	30033	224	0	0	0	0	61	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	20200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	0	726	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	20200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	0	61	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	20200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	0	61	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	20200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30168	30034
10204	30249	224	1	0	0	0	61	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	20200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	0	61	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	20200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	0	61	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	20200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	224	0	0	0	0	61	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	20200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	0	61	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	20200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	16	1	1	29993	10000	10100	30034	30034	30034	30034	30034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30033	225	0	0	0	61	19922	25	10010	10010	10010	828490	49	26953	30033	30033	28632	3	28763	10010	10020	20020	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	29939	10007	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	61	19922	25	10010	10010	10010	828490	49	26953	30033	30033	28632	3	28763	10010	10020	20020	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	224	0	0	0	61	19922	25	10010	10010	10010	828490	49	26953	30033	30033	28632	3	28763	10010	10020	20020	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	224	0	0	0	61	19922	25	10010	10010	10010	828490	49	26953	30033	30033	28632	3	28763	10010	10069	20020	30033	380	1	1	10021	10	9	10	10010	10	0	3	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	224	0	0	0	61	19922	25	10010	10010	10010	828490	49	26953	30033	30033	28632	3	28763	10010	10020	20020	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	61	19922	25	10010	10010	10010	828490	49	26953	30033	30033	28632	3	28763	10010	10020	20020	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	61	19922	25	10010	10010	10010	828490	49	26953	30033	30033	28632	3	28763	10010	10020	20020	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	61	19922	25	10010	10010	10010	828490	49	26953	30033	30033	28632	3	28763	10010	10020	20020	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	61	19922	25	10010	10010	10010	828490	49	26953	30033	30033	28632	3	28763	10010	10020	20020	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	224	0	0	0	61	19922	25	10010	10010	10010	828490	49	26953	30033	30033	28632	3	28763	10010	10020	20020	30033	380	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	29939	10000	10010	30034	30034	30034	30034	30034

Test 4: throughput

Count: 8

Code:

  crc32w w0, w8, w9
  crc32w w1, w8, w9
  crc32w w2, w8, w9
  crc32w w3, w8, w9
  crc32w w4, w8, w9
  crc32w w5, w8, w9
  crc32w w6, w8, w9
  crc32w w7, w8, w9

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80035	600	0	0	0	2132	25	80100	80100	80100	400500	1	49	76955	0	80035	80035	69964	0	3	69993	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	3	16	1	1	80031	80000	80100	80036	80036	80036	80036	80095
80204	80035	599	0	0	9	231	25	80100	80100	80100	400500	1	49	76955	0	80035	80035	69964	0	3	69993	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	0	2660	25	80100	80100	80100	400500	1	49	76955	0	80035	80035	69964	0	3	69993	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	0	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	0	2033	25	80100	80100	80100	400500	1	49	76955	0	80035	80035	69964	0	3	69993	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	600	0	0	0	2635	25	80100	80100	80100	400500	1	49	76955	0	80035	80035	69964	0	3	69993	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	183	0	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	1	0	2651	25	80100	80100	80100	400500	1	49	76955	0	80035	80035	69964	0	3	69993	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	621	0	0	0	2694	25	80100	80100	80100	400500	1	49	76955	0	80035	80035	69964	0	3	69993	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	0	2064	25	80100	80100	80100	400500	1	49	76955	0	80035	80035	69964	0	3	69993	80100	80200	160200	80035	164	1	1	80202	100	99	100	80100	100	0	0	0	0	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	0	1945	25	80100	80100	80100	400500	1	49	76955	0	80035	80035	69964	0	3	69993	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	0	67	25	80100	80100	80100	400500	1	49	76955	0	80035	80035	69996	0	3	69993	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	80035	599	0	0	0	0	0	0	0	0	46	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	160020	80035	164	2	1	80021	10	9	10	80010	10	0	3	2	1	162	0	0	0	5020	17	16	12	12	80070	80000	80010	80036	80036	80036	80036	80073
80024	80035	599	0	0	0	0	0	0	0	0	236	25	80010	80010	80010	400050	1	49	77315	80035	80035	69986	3	70015	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	2	114	0	0	0	5020	6	16	10	6	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	599	0	0	0	0	0	0	0	0	711	25	80010	80010	80010	400488	1	49	76955	80035	80035	69986	3	70015	80010	80020	160020	80035	336	1	1	80021	10	9	10	80010	10	0	0	0	0	48	0	0	0	5020	10	16	10	6	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	620	0	1	0	0	0	0	0	0	324	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	10	16	6	10	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	599	0	0	0	0	1	0	348	0	711	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	6	6	0	0	0	5020	6	16	6	10	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	599	0	0	0	0	0	0	3	0	46	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	150	0	0	0	5020	6	16	10	10	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	600	0	0	0	0	0	0	0	0	1833	25	80010	80010	80010	400050	0	49	76955	80074	80035	69986	3	70045	80010	80064	160020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	1	27	0	0	0	5020	10	16	10	6	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	599	0	0	0	0	0	0	0	0	1593	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	160084	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	3	0	0	0	5020	10	16	6	10	80071	80000	80010	80082	80036	80036	80036	80036
80024	80035	599	0	0	0	0	0	0	0	0	711	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	3	222	0	0	0	5020	10	16	10	6	80032	80000	80010	80036	80036	80036	80074	80036
80024	80035	600	0	0	0	0	0	0	0	0	46	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	123	0	0	0	5020	10	16	10	6	80032	80000	80010	80036	80036	80036	80036	80036

CRC32W

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations