Firestorm: STLLRH measurements

Code:

  stllrh w0, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	1f	22	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	1080	8	0	0	0	1	1065	16	25	1000	1000	1000	45152	1	1028	1080	811	3	938	1000	1000	2000	1080	1080	1	1	1001	1000	1000	1000	60	0	1000	0	0	1000	60	73	2	16	2	2	1077	0	15	11	1000	1081	1081	1081	1081	1081
1004	1080	7	0	0	1	1	1065	16	25	1000	1000	1000	45152	0	1028	1080	778	3	905	1000	1000	2000	1080	1080	1	1	1001	1000	1000	1000	60	10	1000	0	0	1000	60	73	2	16	2	2	1077	15	15	11	1000	1081	1081	1081	1081	1048
1004	1080	8	0	0	0	0	1065	16	25	1000	1000	1000	45152	0	1028	1080	811	3	905	1000	1000	2000	1080	1080	1	1	1001	1000	1000	1000	60	10	1000	0	0	1000	60	73	2	16	2	2	1077	15	15	11	1000	1081	1081	1081	1081	1048
1004	1080	8	0	0	1	0	1065	16	25	1000	1000	1000	45152	0	995	1080	811	3	938	1000	1000	2000	1047	1080	1	1	1001	1000	1000	1000	60	10	1000	0	0	1000	60	73	2	16	2	2	1077	15	15	11	1000	1081	1081	1081	1081	1081
1004	1080	8	0	0	1	0	1065	16	25	1000	1000	1000	45152	0	1028	1080	811	3	938	1000	1000	2000	1080	1047	1	1	1001	1000	1000	1000	0	0	1000	2	0	1000	0	73	2	16	2	2	1044	0	0	0	1000	1081	1081	1081	1081	1081
1004	1080	8	1	0	1	1	1065	16	25	1000	1000	1000	43568	0	1028	1080	811	3	938	1000	1000	2000	1080	1080	1	1	1001	1000	1000	1000	60	10	1000	0	0	1000	60	73	2	16	2	2	1077	15	15	11	1000	1081	1081	1081	1081	1081
1004	1080	8	1	0	1	0	1065	16	25	1000	1000	1000	45152	0	1028	1080	811	3	938	1000	1000	2000	1080	1047	1	1	1001	1000	1000	1000	60	10	1000	0	0	1000	60	73	2	16	2	2	1077	0	15	11	1000	1081	1081	1081	1048	1048
1004	1080	8	0	0	1	0	1065	16	25	1000	1000	1000	45152	0	1028	1080	811	3	938	1000	1000	2000	1080	1080	1	1	1001	1000	1000	1000	60	10	1000	0	0	1000	60	73	2	16	2	2	1077	15	15	11	1000	1081	1081	1081	1081	1081
1004	1080	8	0	0	0	1	1065	16	25	1000	1000	1000	45152	0	1028	1080	778	3	938	1000	1000	2000	1080	1080	1	1	1001	1000	1000	1000	60	10	1000	0	0	1000	60	73	2	16	2	2	1077	15	15	11	1000	1081	1048	1081	1081	1081
1004	1047	8	0	0	1	0	1065	0	25	1000	1000	1000	45152	0	1028	1080	811	3	938	1000	1000	2000	1047	1080	1	1	1001	1000	1000	1000	60	10	1000	0	0	1000	60	73	2	16	2	2	1077	15	15	11	1000	1081	1081	1081	1081	1081

Test 2: throughput

Code:

  stllrh w0, [x6]
  add x6, x6, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0164

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	20	22	29	3a	3e	3f	40	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20206	10362	77	0	0	6	6	27	1	0	8	12	10167	31	73	25	20102	10102	10000	10104	10000	225440	474008	1	0	49	7056	10112	10155	7497	7	7708	20104	10208	10008	10208	20016	10159	123	1	1	20201	100	99	100	10000	10100	10000	100	10027	0	223	3	64	31	10001	2	33	18	7	10033	2	192	1	1	1	1317	0	16	0	0	10269	10002	92	61	0	10000	10100	10143	10178	10167	10158	10143
20204	10164	76	0	0	30	3	35	1	0	11	0	10151	29	54	25	20103	10102	10000	10104	10000	324639	487485	1	1	49	7130	10103	10164	7503	6	7595	20104	10208	10008	10208	20016	10139	123	1	1	20201	100	99	100	10000	10100	10000	100	10032	12	290	1	148	24	10011	3	33	24	9	10031	1	192	1	1	1	1317	0	16	0	0	10198	10002	79	72	10	10000	10100	10182	10162	10213	10203	10191
20204	10186	76	0	0	6	6	33	1	0	12	0	10146	29	121	25	20102	10102	10000	10104	10000	370021	471176	1	1	49	7108	10130	10117	7542	6	7593	20104	10208	10008	10208	20016	10122	123	1	1	20201	100	99	100	10000	10100	10000	100	10027	0	204	6	84	47	10003	2	24	16	12	10025	3	230	1	1	1	1318	0	16	0	0	10156	10002	77	84	0	10000	10100	10177	10331	10202	10259	10135
20204	10157	77	0	0	12	2	25	1	0	12	0	10149	25	123	25	20100	10105	10000	10104	10000	325919	471800	1	0	49	7101	10226	10374	7471	7	7615	20104	10208	10008	10208	20016	10141	123	1	1	20201	100	99	100	10000	10100	10000	100	10027	0	192	5	76	33	10004	1	33	24	12	10037	2	186	1	1	1	1318	0	16	0	0	10139	10000	64	71	56	10000	10100	10156	10167	10156	10149	10158
20204	10157	76	0	0	6	3	24	0	0	5	24	10144	16	70	25	20103	10104	10000	10104	10000	250089	472232	1	0	49	7108	10124	10181	7588	6	7641	20104	10208	10008	10208	20016	10186	123	1	1	20201	100	99	100	10000	10100	10000	100	10022	0	262	4	100	31	10001	2	29	8	11	10048	4	128	1	1	1	1317	0	16	0	0	10131	10002	94	75	4	10000	10100	10167	10180	10182	10156	10145
20204	10166	76	0	0	12	3	19	1	0	18	0	10151	23	45	25	20102	10102	10000	10104	10000	325342	471800	1	1	49	7140	10109	10157	7495	6	7610	20104	10208	10008	10208	20016	10134	123	1	1	20201	100	99	100	10000	10100	10000	100	10021	0	127	4	91	33	10003	3	41	16	13	10032	3	283	1	1	1	1318	0	16	0	0	10189	10002	62	69	17	10000	10100	10265	10145	10179	10143	10141
20204	10228	77	0	0	12	3	24	1	0	12	0	10129	19	98	25	20104	10108	10000	10104	10000	323967	473192	1	1	49	7215	10234	10234	7503	6	7594	20104	10208	10008	10208	20016	10139	123	1	1	20201	100	99	100	10000	10100	10000	100	10030	0	255	8	66	33	10002	2	45	24	16	10019	2	128	1	1	1	1317	0	16	0	0	10161	10002	96	71	17	10000	10100	10135	10188	10147	10167	10160
20204	10177	76	0	0	6	8	45	1	0	9	28	10187	12	114	25	20103	10104	10000	10104	10000	368437	472232	1	0	49	7096	10118	10160	7513	7	7615	20104	10208	10008	10208	20016	10181	123	1	1	20201	100	99	100	10000	10100	10000	100	10027	0	134	4	74	30	10003	3	33	12	7	10024	4	167	1	1	1	1318	0	16	0	0	10185	10002	92	59	16	10000	10100	10219	10248	10219	10257	10177
20204	10134	76	0	0	6	3	27	1	0	13	0	10163	25	90	25	20102	10100	10000	10104	10000	239005	473576	1	1	49	7102	10092	10136	7473	7	7586	20104	10208	10008	10208	20016	10185	123	1	1	20201	100	99	100	10000	10100	10000	100	10041	0	229	3	78	24	10011	0	39	28	1	10033	1	230	1	1	1	1317	0	16	0	0	10141	10002	107	84	0	10000	10100	10158	10165	10157	10167	10163
20204	10162	76	0	1	0	2	25	0	0	12	0	10161	25	44	25	20104	10104	10000	10104	10000	213260	472040	1	4	49	7079	10108	10183	7520	7	7659	20104	10208	10008	10208	20016	10145	123	1	1	20201	100	99	100	10000	10100	10000	100	10034	0	262	6	82	29	10003	2	43	24	16	10041	3	191	1	1	1	1317	0	16	0	0	10131	10000	62	87	0	10000	10100	10143	10156	10165	10112	10162

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0188

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	20	22	3a	3e	3f	40	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20026	10503	77	2	2	2	2	0	0	21	20	39	3	19	0	10185	31	131	25	20011	10010	10000	10010	10000	307840	473240	1	1	0	49	7295	10160	10222	7518	3	7721	20010	10020	10000	10020	20000	10224	124	1	1	20021	10	9	10	10000	10010	10000	10	10043	16	197	4	76	27	10019	3	2	39	24	31	10034	14	224	14	0	1270	1	16	1	1	10144	10000	75	102	5	10000	10010	10144	10223	10147	10194	10334
20024	10293	77	2	3	2	2	0	0	12	12	27	1	14	32	10293	20	81	25	20010	10010	10000	10010	10000	386778	475592	0	1	0	49	7166	10206	10277	7566	3	7651	20010	10020	10000	10020	20000	10167	124	1	1	20021	10	9	10	10000	10010	10000	10	10047	16	139	3	70	27	10016	3	0	27	34	29	10028	11	192	7	0	1270	1	16	1	1	10204	10000	92	87	20	10000	10010	10165	10156	10189	10156	10294
20024	10231	78	1	1	1	0	0	0	18	10	27	1	15	0	10149	33	123	25	20010	10010	10000	10010	10000	243439	474200	0	1	0	49	7112	10127	10212	7613	3	7740	20010	10020	10000	10020	20000	10190	124	1	1	20021	10	9	10	10000	10010	10000	10	10049	8	289	4	80	33	10010	1	1	59	48	23	10041	9	166	7	1	1270	1	15	1	1	10154	10000	97	89	9	10000	10010	10189	10179	10169	10202	10272
20024	10164	77	1	1	1	1	0	0	6	18	33	1	8	32	10219	20	130	25	20010	10010	10000	10010	10000	218904	478952	0	1	0	49	7130	10150	10187	7565	3	7692	20010	10020	10000	10020	20000	10144	124	1	1	20021	10	9	10	10000	10010	10000	10	10052	7	160	5	76	40	10015	1	1	51	36	13	10041	9	291	7	2	1270	1	16	1	1	10180	10000	111	60	11	10000	10010	10208	10167	10181	10191	10202
20024	10157	76	1	1	1	1	0	0	18	19	39	1	18	0	10213	37	118	25	20010	10010	10000	10010	10000	364369	476408	0	1	0	49	7121	10116	10157	7531	3	7678	20010	10020	10000	10020	20000	10202	124	1	1	20021	10	9	10	10000	10010	10000	10	10032	7	128	4	80	63	10010	3	1	45	22	19	10034	8	205	7	2	1270	1	16	1	1	10175	10000	110	87	2	10000	10010	10187	10177	10187	10183	10215
20024	10251	77	1	0	0	1	0	0	6	19	44	2	8	0	10161	31	88	25	20010	10010	10000	10010	10000	289324	474536	0	1	0	49	7110	10120	10166	7541	3	7668	20010	10020	10000	10020	20000	10166	124	1	1	20021	10	9	10	10000	10010	10000	10	10041	7	288	6	66	39	10010	2	1	39	36	19	10033	10	378	7	1	1270	1	15	1	1	10163	10000	79	86	11	10000	10010	10160	10191	10204	10186	10186
20024	10186	76	1	0	0	1	0	0	6	10	45	1	21	0	10171	47	124	25	20010	10010	10000	10010	10000	318720	474536	0	1	0	49	7232	10090	10143	7513	3	7722	20010	10020	10000	10020	20000	10241	124	1	1	20021	10	9	10	10000	10010	10000	10	10044	20	282	0	112	32	10018	3	2	44	0	12	10021	9	164	7	1	1270	1	16	2	1	10177	10000	92	87	74	10000	10010	10189	10220	10187	10182	10189
20024	10210	76	1	0	0	1	0	0	12	14	33	1	13	0	10188	49	85	25	20010	10010	10000	10010	10000	84059	477032	1	0	0	49	7235	10279	10273	7622	3	7727	20010	10020	10000	10020	20000	10167	124	1	1	20021	10	9	10	10000	10010	10000	10	10033	7	196	7	64	31	10011	1	3	33	18	21	10030	8	165	7	2	1270	1	15	1	1	10153	10000	156	115	39	10000	10010	10187	10198	10252	10164	10189
20024	10164	77	0	0	0	1	0	0	6	12	33	1	10	0	10142	25	80	25	20010	10010	10000	10010	10000	354488	472088	0	1	0	49	7167	10134	10176	7543	3	7666	20010	10020	10000	10020	20000	10157	124	1	1	20021	10	9	10	10000	10010	10000	10	10029	7	160	2	47	39	10008	1	0	34	16	12	10021	10	165	7	1	1270	1	16	1	1	10152	10000	77	69	20	10000	10010	10177	10165	10135	10143	10184
20024	10161	76	1	1	1	1	0	0	6	10	30	1	13	0	10161	25	102	25	20010	10010	10000	10010	10000	384332	472232	0	1	1	49	7130	10061	10137	7495	3	7756	20010	10020	10000	10020	20000	10276	124	1	1	20021	10	9	10	10000	10010	10000	10	10035	8	165	2	64	33	10020	4	1	44	0	8	10029	9	166	7	1	1270	1	16	1	1	10223	10000	169	147	58	10000	10010	10289	10309	10324	10288	10355

Test 3: throughput

Code:

  stllrh w0, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0080

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	19	1e	1f	22	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10205	10080	76	0	0	0	0	0	0	1	1	0	10065	16	25	10100	100	10000	100	10000	500	468152	1	49	7008	10036	10055	8676	6	8792	10100	200	10008	200	20016	10088	7959	1	1	10201	100	99	100	10000	100	10000	100	10016	16	60	5	2	10014	0	1	14	10000	0	60	0	0	1	1	1	717	0	16	0	0	10044	15	15	11	10000	100	10081	10081	10048	10081	10081
10204	10047	75	0	0	0	0	0	3	1	0	0	10065	16	25	10100	100	10000	100	10000	500	468152	1	49	7008	10036	10088	8676	6	8792	10100	200	10008	200	20016	10092	7959	1	1	10201	100	99	100	10000	100	10000	100	10015	14	60	5	1	10014	0	1	15	10000	0	60	0	0	1	1	1	717	0	16	0	0	10077	15	15	0	10000	100	10048	10081	10081	10048	10081
10204	10080	75	0	0	0	0	0	0	0	0	0	10065	0	25	10100	100	10000	100	10000	500	468152	1	49	7008	10036	10088	8643	6	8759	10100	200	10008	200	20016	10090	7926	1	1	10201	100	99	100	10000	100	10000	100	10014	14	60	4	0	10014	0	0	14	10000	0	60	0	0	1	1	1	717	0	16	0	0	10077	15	15	11	10000	100	10081	10048	10081	10081	10081
10204	10080	76	0	0	0	1	0	6	21	0	0	10073	0	25	10100	100	10000	100	10000	500	468540	1	49	7000	9995	10080	8668	6	8784	10100	200	10008	200	20016	10080	7951	1	1	10201	100	99	100	10000	100	10000	100	10000	0	60	10	0	10000	0	0	0	10000	0	0	0	0	1	1	1	717	0	16	0	0	10077	15	15	11	10000	100	10048	10048	10081	10081	10081
10204	10080	75	0	0	0	0	0	15	1	0	0	10032	16	25	10100	100	10000	100	10000	500	468152	1	49	7000	10028	10080	8668	6	8784	10100	200	10008	200	20016	10080	7951	1	1	10201	100	99	100	10000	100	10000	100	10000	0	60	10	0	10000	0	0	0	10000	14	60	14	1	1	1	1	717	0	16	0	0	10052	15	15	12	10000	100	10089	10089	10089	10089	10089
10204	10055	76	1	1	0	0	0	0	1	0	0	10065	0	25	10100	100	10000	100	10000	500	468152	1	49	7000	10028	10047	8668	6	8784	10100	200	10008	200	20016	10080	7918	1	1	10201	100	99	100	10000	100	10000	100	10000	0	60	10	0	10000	0	0	0	10000	14	60	14	0	1	1	1	717	0	16	0	0	10052	15	15	10	10000	100	10056	10056	10056	10056	10089
10204	10055	75	1	0	0	0	0	0	0	0	0	10065	16	25	10100	100	10000	100	10000	500	468152	1	49	6977	10036	10088	8676	6	8792	10100	200	10008	200	20016	10055	7959	1	1	10201	100	99	100	10000	100	10000	100	10015	14	60	0	1	10014	0	0	17	10000	0	60	0	0	1	1	1	717	0	16	0	0	10077	15	15	11	10000	100	10048	10048	10081	10048	10081
10204	10080	75	0	0	0	0	0	0	15	0	0	10073	3	25	10100	100	10000	100	10000	500	468542	1	49	7000	10028	10080	8668	6	8784	10100	200	10008	200	20016	10080	7951	1	1	10201	100	99	100	10000	100	10000	100	10000	0	60	10	0	10000	0	0	0	10000	15	0	14	1	1	1	1	717	0	16	0	0	10085	15	0	0	10000	100	10056	10089	10089	10089	10089
10204	10055	75	1	0	1	0	0	45	0	0	0	10032	16	25	10100	100	10000	100	10000	500	468152	1	49	7008	10036	10088	8676	6	8792	10100	200	10008	200	20016	10088	7959	1	1	10201	100	99	100	10000	100	10000	100	10014	14	60	6	0	10014	0	0	14	10001	0	60	0	0	1	1	1	717	0	16	0	0	10077	15	15	11	10000	100	10081	10081	10081	10081	10081
10204	10047	75	0	0	0	0	0	24	1	0	0	10065	16	25	10100	100	10000	100	10000	500	468152	1	49	7008	10003	10088	8676	6	8792	10100	200	10008	200	20016	10055	7959	1	1	10201	100	99	100	10000	100	10000	100	10015	15	0	4	0	10014	1	0	14	10000	0	60	0	0	1	1	1	717	0	16	0	0	10044	15	15	0	10000	100	10081	10048	10048	10081	10048

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0084

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	1f	22	23	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10025	10084	75	0	0	1	0	0	10032	0	25	10010	10	10000	10	10000	50	468344	0	49	7070	10032	10084	8687	3	8814	10010	20	10000	20	20000	10047	10084	1	1	10021	10	9	10	10000	10	10000	10	10000	60	14	10000	10	0	10000	60	640	3	16	2	2	10081	19	19	15	10000	10	10085	10085	10085	10085	10087
10024	10084	76	0	0	0	1	0	10069	20	25	10010	10	10000	10	10000	50	468344	1	49	7004	10032	10084	8650	3	8814	10010	20	10000	20	20000	10047	10047	1	1	10021	10	9	10	10000	10	10000	10	10000	60	14	10000	0	0	10000	0	640	2	16	2	2	10081	19	19	15	10000	10	10085	10085	10085	10085	10087
10024	10084	75	0	0	1	0	0	10069	20	25	10010	10	10000	10	10000	50	468344	1	49	7004	10032	10084	8687	3	8814	10010	20	10000	20	20000	10084	10084	1	1	10021	10	9	10	10000	10	10000	10	10000	60	14	10000	6	3	10000	60	640	2	16	2	2	10081	0	19	15	10000	10	10085	10085	10085	10085	10087
10024	10084	75	0	0	1	0	0	10069	20	25	10010	10	10000	10	10324	50	466568	1	49	6967	10032	10084	8650	3	8814	10010	20	10000	20	20000	10084	10084	1	1	10021	10	9	10	10000	10	10000	10	10000	60	14	10000	5	0	10000	60	640	2	16	2	2	10081	19	19	15	10000	10	10048	10048	10085	10085	10085
10024	10084	76	0	0	1	0	0	10069	20	25	10010	10	10000	10	10000	50	468344	1	49	7004	10032	10084	8687	3	8814	10010	20	10000	20	20000	10047	10084	1	1	10021	10	9	10	10000	10	10000	10	10000	60	14	10000	0	0	10000	0	640	2	16	2	2	10081	19	19	0	10000	10	10085	10085	10085	10085	10085
10024	10086	75	0	0	1	1	0	10069	0	25	10010	10	10000	10	10000	50	468344	0	49	7004	10032	10084	8687	3	8777	10010	20	10000	20	20000	10084	10084	1	1	10021	10	9	10	10000	10	10000	10	10000	60	0	10000	0	0	10000	60	640	2	16	2	2	10081	19	0	15	10000	10	10048	10085	10048	10048	10048
10024	10084	76	0	0	1	0	0	10069	20	25	10010	10	10000	10	10000	50	466568	1	49	7004	10032	10047	8687	3	8814	10010	20	10000	20	20000	10084	10047	1	1	10021	10	9	10	10000	10	10000	10	10000	60	14	10000	0	0	10000	0	640	2	16	2	2	10081	19	19	15	10000	10	10048	10085	10089	10087	10085
10024	10084	75	0	6	1	0	0	10069	22	25	10010	10	10000	10	10000	50	468344	0	49	6967	10032	10047	8687	3	8814	10010	20	10000	20	20000	10084	10047	1	1	10021	10	9	10	10000	10	10000	10	10000	0	14	10000	2	21	10000	60	640	2	16	2	2	10081	0	0	15	10000	10	10050	10048	10085	10085	10085
10024	10084	75	0	0	1	0	0	10069	0	25	10010	10	10000	10	10000	50	466568	0	49	7004	10032	10084	8687	3	8814	10010	20	10000	20	20000	10084	10047	1	1	10021	10	9	10	10000	10	10000	10	10000	60	14	10000	10	0	10000	0	640	2	16	2	2	10044	19	19	15	10000	10	10085	10087	10085	10085	10048
10024	10047	76	0	0	0	0	0	10069	20	25	10010	10	10000	10	10000	50	468344	0	49	6967	10032	10084	8687	3	8814	10010	20	10000	20	20000	10084	10047	1	1	10021	10	9	10	10000	10	10000	10	10000	60	14	10000	0	0	10000	0	640	2	16	2	2	10044	0	0	15	10000	10	10085	10085	10048	10048	10087

STLLRH

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations