Firestorm: MVN (register, lsl, 64-bit) measurements

Code:

  mvn x0, x0, lsl #17

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	2035	15	0	82	1000	1735	25	2000	2000	1000	32570	0	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1735	25	2000	2000	1000	32570	0	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1735	25	2000	2000	1000	32570	0	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1735	25	2000	2000	1000	32570	0	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	103	1000	1735	25	2000	2000	1000	32570	0	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	0	75	2	63	2	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1735	25	2000	2000	1000	32570	0	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1735	25	2000	2000	1000	32570	0	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	247	1000	1735	25	2000	2000	1000	32570	1	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	0	73	1	67	2	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1735	25	2000	2000	1000	32570	0	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	82	1000	1735	25	2000	2000	1000	32570	0	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036

Test 2: Latency 1->2

Code:

  mvn x0, x0, lsl #17

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20035	150	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	10200	20035	42	1	1	10201	100	99	100	10100	100	0	0	12	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	10200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	103	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	10200	20035	42	1	1	10201	100	99	100	10100	100	0	0	3	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	10200	20035	42	1	1	10201	100	99	100	10100	100	2	0	7988	710	1	59	1	2	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	155	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	10200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	10200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	10200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	10200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	10200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	10200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20035	150	0	61	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	10020	20035	42	1	1	10021	10	9	10	10010	10	0	640	3	63	4	3	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	10020	20035	42	1	1	10021	10	9	10	10010	10	0	640	4	63	3	4	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	3721	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	10020	20035	42	1	1	10021	10	9	10	10010	10	0	640	4	63	4	3	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	631	10000	19743	25	20010	20010	10010	185310	1	49	16955	20035	20035	18451	3	18718	10010	10020	10020	20035	42	1	1	10021	10	9	10	10010	10	0	640	4	63	4	3	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	10020	20035	42	1	1	10021	10	9	10	10010	10	0	640	3	63	3	4	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	10020	20035	42	1	1	10021	10	9	10	10010	10	0	640	3	63	3	4	19792	20023	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	10020	20035	42	1	1	10021	10	9	10	10010	10	0	640	4	63	4	3	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	10020	20035	42	1	1	10021	10	9	10	10010	10	0	640	3	63	4	3	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	10020	20035	42	1	1	10021	10	9	10	10010	10	0	640	4	63	3	4	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	10020	20035	42	1	1	10021	10	9	10	10010	10	0	640	3	63	4	3	19792	20000	10010	20036	20036	20036	20036	20036

Test 3: throughput

Count: 8

Code:

  mvn x0, x8, lsl #17
  mvn x1, x8, lsl #17
  mvn x2, x8, lsl #17
  mvn x3, x8, lsl #17
  mvn x4, x8, lsl #17
  mvn x5, x8, lsl #17
  mvn x6, x8, lsl #17
  mvn x7, x8, lsl #17

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26882	201	0	0	0	0	0	0	558	80514	25426	200	161484	161292	81738	181682	49	24002	27083	27139	16659	62	16797	81512	81900	81696	27082	39	7	1	80201	100	99	100	80100	100	0	4	3	0	1	730	2	2	2	5308	0	2	88	1	1	27005	161507	80100	27094	27099	27096	27099	27099
80204	27150	204	1	1	6	7	795	616	2161	80598	25467	248	161769	161657	81515	195184	49	24191	27212	27208	16620	89	16835	81938	82116	82120	27096	39	10	1	80201	100	99	100	80100	100	4	0	0	1	0	6573	2	2	2	5327	0	1	110	2	3	27203	162223	80100	27386	27382	27435	27097	27387
80204	27445	205	0	0	11	10	1398	880	411	80000	25931	31	160100	160100	80100	170077	49	23664	26744	26744	16572	6	16669	80100	80857	80200	26744	39	1	1	80201	100	99	100	80100	100	4	2	2	0	0	7295	1	1	1	5364	0	2	143	4	3	27393	162200	80100	27337	27226	27210	27447	27157
80204	27156	213	1	0	0	0	0	0	102	80000	25931	31	160100	160100	80100	170077	49	23664	26744	26744	16572	6	16669	80100	80200	80200	26744	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5120	0	2	46	2	2	26731	160000	80100	26745	26745	26745	26745	26745
80204	26744	207	0	0	0	0	0	0	97	80000	25931	31	160100	160100	80100	170077	49	23664	26744	26744	16572	6	16669	80100	80200	80200	26802	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	6	1	1	1	5120	24	0	16	0	0	26729	160082	80100	26733	26733	26733	26733	26733
80204	26732	231	0	0	0	0	240	0	28	80031	26146	28	160182	160182	80262	161906	49	23652	26732	26731	16651	8	16661	80262	80376	80376	26732	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5129	0	0	16	0	0	26729	160082	80100	26733	26733	26733	26733	26733
80204	26732	200	0	0	0	0	183	0	28	80031	26146	28	160182	160182	80262	161906	49	23651	26732	26732	16651	8	16661	80262	80376	80376	26732	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5129	0	0	16	0	0	26729	160082	80100	26733	26733	26733	26733	26733
80204	26732	200	0	0	0	0	444	0	28	80031	26146	28	160182	160182	80262	161906	49	23652	26732	26732	16651	8	16661	80262	80376	80376	26732	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5129	0	0	16	0	0	26729	160082	80100	26733	26733	26733	26733	26733
80204	26732	200	0	0	0	0	246	0	28	80031	26146	28	160182	160182	80262	161906	49	23652	26732	26732	16651	8	16661	80262	80376	80376	26732	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5129	0	0	16	0	0	26729	160082	80100	26733	26785	26733	26733	26733
80204	26731	200	0	0	0	0	261	0	28	80031	26146	28	160182	160182	80262	161906	49	23652	26732	26732	16651	8	16661	80262	80376	80376	26732	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5129	0	0	16	0	0	26729	160082	80100	26733	26733	26733	26733	26733

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	19	1e	1f	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	26717	200	0	0	0	243	0	61	80000	21280	25	160010	160010	80363	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	3	22	1	1	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	0	27	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	1	22	1	1	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	0	399	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	1	22	1	1	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	0	12	108	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	1	22	1	1	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	0	30	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	1	22	1	1	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	0	30	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	1	22	1	1	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	0	24	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	1	22	1	1	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	0	339	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	1	22	1	1	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	0	24	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	1	22	1	1	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	0	327	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	1	22	1	1	26704	160000	80010	26712	26712	26712	26712	26712

MVN (register, lsl, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations